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AMD-GCN5.md

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5th generation Graphics Core Next architecture, code name: Vega.
9 generation of AMD GFX IP.

Examples

  • Radeon RX Vega 56, 64
  • Radeon VII

References

  1. Vega Instruction Set Architecture, [backup]
  2. RDNA Architecture - difference between GCN and RDNA
  3. The AMD Radeon VII Review
  4. Vega Whitepaper
  5. Vega 7nm ISA

Notes

Specs

  • Cache: [2]

    • Instruction Cache: 32KB per 4 CUs, line: 32B, Read-only
    • Scalar Cache: 16KB per 4 CUs, line: 32B, Read-only
    • L1 Cache: 16KB per CU, line: 64B, Read-only
    • L2 Cache: 4MB, line: 64B, Read/Write

  • Compressed read from: CU (storage image), Render Backend (texture sampling). [2]

  • Compressed write from: Render Backend (render target). [2]

  • Decompression: write to storage image, in present queue. [2]

  • Texture Unit: [2]

    • Load addressing: 4 to 16 (coalesced) addresses/clk
    • Load data processing: 4 to 16 (coalesced) dwords/clk
    • Store addressing: 4 to 16 (coalesced) addresses/clk
    • Store data processing: 4 to 16 (coalesced) dwords/clk
    • Filtering 64bit texels: 2 components/clk