+ ArtCNN
++ Single-Image Super-Resolution Convolutional Neural Networks as GLSL shaders for mpv. The model is relatively simple with a + feed-forward architecture, a single long-skip connection and a pixel shuffle layer to upscale the feature maps. Different degradation models + and dataset preparation steps were used to tackle different problems, and the model is offered in various flavours. +
+ View Project +
@@ -190,8 +208,8 @@ Projects
Chroma From Luma Prediction
- CfL is a GLSL shader that implements chroma upscaling based on the closed least squares solution for linear regression, inspired by the adoption of the same technique in modern video codecs. - Since a simple linear regression obviously doesn't take into account pixel distance, the prediction is mixed with the output of a normal resampling filter based on how high the + CfL is a GLSL shader that implements chroma upscaling based on the closed least squares solution for linear regression, inspired by the adoption of the same technique in modern video codecs. + Since a simple linear regression obviously doesn't take into account pixel distance, the prediction is mixed with the output of a normal resampling filter based on how high the correlation between luma and chroma is.
View Project @@ -224,7 +242,7 @@Joint Bilateral
Pixel Clipper
- Pixel Clipper is a GLSL shader for anti-ringing. It limits pixel magnitude after resampling to avoid overshooting and haloing. + Pixel Clipper is a GLSL shader for anti-ringing. It limits pixel magnitude after resampling to avoid overshooting and haloing.
View ProjectOSEE
SP-VDSR
- SP-VDSR is a shallow convolutional neural network based on both VDSR and ESPCN. The rationale was making VDSR faster employing ESPCN's depth-to-space sub-pixel convolution to upsample + SP-VDSR is a shallow convolutional neural network based on both VDSR and ESPCN. The rationale was making VDSR faster employing ESPCN's depth-to-space sub-pixel convolution to upsample the residuals. The trained network is relatively shallow with only 5 convolutional layers of 8 kernels each.
View Project @@ -273,9 +291,9 @@SP-VDSR
Maestro
- Maestro is a 5 stage pipeline implementation of the RV32I ISA strongly inspired by David Patterson's and John Hennessy's Computer Organization and Design RISC-V Edition.
+ Maestro is a 5 stage pipeline implementation of the RV32I ISA strongly inspired by David Patterson's and John Hennessy's Computer Organization and Design RISC-V Edition.
The project is entirely academic, it's written in VHDL in a beginner-friendly way so computer architecture students can also learn about hardware design.
- The core is very good at demonstrating how to build simple workarounds for problems encountered within pipelined in-order CPU cores such as hazards and stalls.
+ The core is very good at demonstrating how to build simple workarounds for problems encountered within pipelined in-order CPU cores such as hazards and stalls.
Maestro
EDC testbench
The environmental data collector is a Cubsat-compatible payload capable of decoding up to 12 ARGOS-2 PTT signals.
- During my internship I was in charge of developing a way of simulating the system to catch bugs and evaluate its performance. The testbench was composed of a hardware in the loop test-routine
+ During my internship I was in charge of developing a way of simulating the system to catch bugs and evaluate its performance. The testbench was composed of a hardware in the loop test-routine
and the required code to emulate an on-board-computer utilising an x86 Workstation running Matlab as a master, an Arduino Due as an I²C bridge and a Rohde&Schwarz SMBV100A Vector Signal Generator.