From e0b2179f19b1df1900f4bf988d3f7635ae9ccbb0 Mon Sep 17 00:00:00 2001
From: Edward Guan <nooop3.lau@gmail.com>
Date: Sun, 10 Jul 2022 12:13:57 +0800
Subject: [PATCH] Fix CI error about:
 [1](https://github.com/rust-lang/stdarch/pull/1183)
 [2](https://github.com/rust-lang/rust/issues/93332)

---
 ci-user/riscv/src/asm.rs             |  8 ++++----
 ci-user/riscv/src/lib.rs             |  2 +-
 ci-user/riscv/src/register/macros.rs | 12 ++++++------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/ci-user/riscv/src/asm.rs b/ci-user/riscv/src/asm.rs
index fe1ad56..79d08ba 100644
--- a/ci-user/riscv/src/asm.rs
+++ b/ci-user/riscv/src/asm.rs
@@ -7,7 +7,7 @@ macro_rules! instruction {
         pub unsafe fn $fnname() {
             match () {
                 #[cfg(all(riscv, feature = "inline-asm"))]
-                () => asm!($asm),
+                () => core::arch::asm!($asm),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
                 () => {
@@ -58,7 +58,7 @@ instruction!(
 pub unsafe fn sfence_vma(asid: usize, addr: usize) {
     match () {
         #[cfg(all(riscv, feature = "inline-asm"))]
-        () => asm!("sfence.vma {0}, {1}", in(reg) asid, in(reg) addr),
+        () => core::arch::asm!("sfence.vma {0}, {1}", in(reg) asid, in(reg) addr),
 
         #[cfg(all(riscv, not(feature = "inline-asm")))]
         () => {
@@ -87,7 +87,7 @@ mod hypervisor_extension {
                 match () {
                     #[cfg(all(riscv, feature = "inline-asm"))]
                     // Since LLVM does not recognize the two registers, we assume they are placed in a0 and a1, correspondingly.
-                    () => asm!($asm, in("x10") rs1, in("x11") rs2),
+                    () => core::arch::asm!($asm, in("x10") rs1, in("x11") rs2),
 
                     #[cfg(all(riscv, not(feature = "inline-asm")))]
                     () => {
@@ -112,7 +112,7 @@ mod hypervisor_extension {
                     #[cfg(all(riscv, feature = "inline-asm"))]
                     () => {
                         let mut result : usize;
-                        asm!($asm, inlateout("x10") rs1 => result);
+                        core::arch::asm!($asm, inlateout("x10") rs1 => result);
                         return result;
                     }
 
diff --git a/ci-user/riscv/src/lib.rs b/ci-user/riscv/src/lib.rs
index 4f2ec2e..5eff6e0 100644
--- a/ci-user/riscv/src/lib.rs
+++ b/ci-user/riscv/src/lib.rs
@@ -14,7 +14,7 @@
 //! - Wrappers around assembly instructions like `WFI`.
 
 #![no_std]
-#![cfg_attr(feature = "inline-asm", feature(asm))]
+#![feature(asm_const)]
 extern crate bare_metal;
 #[macro_use]
 extern crate bitflags;
diff --git a/ci-user/riscv/src/register/macros.rs b/ci-user/riscv/src/register/macros.rs
index 5bf04c5..8e1f37e 100644
--- a/ci-user/riscv/src/register/macros.rs
+++ b/ci-user/riscv/src/register/macros.rs
@@ -7,7 +7,7 @@ macro_rules! read_csr {
                 #[cfg(all(riscv, feature = "inline-asm"))]
                 () => {
                     let r: usize;
-                    asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
+                    core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
                     r
                 }
 
@@ -36,7 +36,7 @@ macro_rules! read_csr_rv32 {
                 #[cfg(all(riscv32, feature = "inline-asm"))]
                 () => {
                     let r: usize;
-                    asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
+                    core::arch::asm!("csrrs {0}, {1}, x0", out(reg) r, const $csr_number);
                     r
                 }
 
@@ -102,7 +102,7 @@ macro_rules! write_csr {
         unsafe fn _write(bits: usize) {
             match () {
                 #[cfg(all(riscv, feature = "inline-asm"))]
-                () => asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
+                () => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
                 () => {
@@ -128,7 +128,7 @@ macro_rules! write_csr_rv32 {
         unsafe fn _write(bits: usize) {
             match () {
                 #[cfg(all(riscv32, feature = "inline-asm"))]
-                () => asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
+                () => core::arch::asm!("csrrw x0, {1}, {0}", in(reg) bits, const $csr_number),
 
                 #[cfg(all(riscv32, not(feature = "inline-asm")))]
                 () => {
@@ -178,7 +178,7 @@ macro_rules! set {
         unsafe fn _set(bits: usize) {
             match () {
                 #[cfg(all(riscv, feature = "inline-asm"))]
-                () => asm!("csrrs x0, {1}, {0}", in(reg) bits, const $csr_number),
+                () => core::arch::asm!("csrrs x0, {1}, {0}", in(reg) bits, const $csr_number),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
                 () => {
@@ -204,7 +204,7 @@ macro_rules! clear {
         unsafe fn _clear(bits: usize) {
             match () {
                 #[cfg(all(riscv, feature = "inline-asm"))]
-                () => asm!("csrrc x0, {1}, {0}", in(reg) bits, const $csr_number),
+                () => core::arch::asm!("csrrc x0, {1}, {0}", in(reg) bits, const $csr_number),
 
                 #[cfg(all(riscv, not(feature = "inline-asm")))]
                 () => {