lc3.def

/*									tab:8
 *
 * lc3.def - definition file for the LC-3 ISA
 *
 * "Copyright (c) 2003 by Steven S. Lumetta."
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written 
 * agreement is hereby granted, provided that the above copyright notice
 * and the following two paragraphs appear in all copies of this software,
 * that the files COPYING and NO_WARRANTY are included verbatim with
 * any distribution, and that the contents of the file README are included
 * verbatim as part of a file named README with any distribution.
 * 
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE TO ANY PARTY FOR DIRECT, 
 * INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT 
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE AUTHOR 
 * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE AUTHOR SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT 
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
 * A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" 
 * BASIS, AND THE AUTHOR NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, 
 * UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
 *
 * Author:	    Steve Lumetta
 * Version:	    1
 * Creation Date:   18 October 2003
 * Filename:	    lc3.def
 * History:
 *	SSL	1	18 October 2003
 *		Copyright notices and Gnu Public License marker added.
 */



/* Field access macros for instruction code. */

#define INST	REG (R_IR)

#define I_DR    F_DR (INST)
#define I_SR1   F_SR1 (INST)
#define I_SR2   F_SR2 (INST)
#define I_BaseR I_SR1
#define I_SR    I_DR    /* for stores */
#define I_CC    F_CC (INST)
#define I_vec8  F_vec8 (INST)

#define I_imm5  F_imm5 (INST)
#define I_imm6  F_imm6 (INST)
#define I_imm9  F_imm9 (INST)
#define I_imm11 F_imm11 (INST)


/* Macro to set condition codes (used in instruction code). */

#define SET_CC() {                  \
    REG (R_PSR) &= ~0x0E00;         \
    if ((REG (I_DR) & 0x8000) != 0) \
	REG (R_PSR) |= 0x0800;      \
    else if (REG (I_DR) == 0)       \
	REG (R_PSR) |= 0x0400;      \
    else                            \
	REG (R_PSR) |= 0x0200;      \
}


/*
 * Instruction definition macro format
 * 
 * DEF_INST(name,format,mask,match,flags,code)
 *
 * name   -- mnemonic operand name for disassembly
 * format -- instruction format (operands to print in disassembly)
 * mask   -- bit vector of bits that must match for this instruction
 * match  -- values of bits to match in instruction
 * flags  -- flags for instruction types
 * code   -- operations to execute for instruction
 *
 *
 * 
 * Pseudo-op definition macro format (disassembly only)
 *
 * DEF_POP(name,format,mask,match)   fields are same as DEF_INST above
 *
 */

DEF_INST (ADD, FMT_RRR, 0xF038, 0x1000, FLG_NONE, {
    REG (I_DR) = (REG (I_SR1) + REG (I_SR2)) & 0xFFFF;
    SET_CC ();
}); 

DEF_INST (ADD, FMT_RRI, 0xF020, 0x1020, FLG_NONE, {
    REG (I_DR) = (REG (I_SR1) + I_imm5) & 0xFFFF;
    SET_CC ();
});

DEF_INST (AND, FMT_RRR, 0xF038, 0x5000, FLG_NONE, {
    REG (I_DR) = REG (I_SR1) & REG (I_SR2);
    SET_CC ();
});

DEF_INST (AND, FMT_RRI, 0xF020, 0x5020, FLG_NONE, {
    REG (I_DR) = REG (I_SR1) & I_imm5;
    SET_CC ();
});

DEF_P_OP (NOP, FMT_, 0xFFFF, 0x0000);
DEF_P_OP (.FILL, FMT_A, 0xFF00, 0x0000);
DEF_P_OP (NOP, FMT_, 0xF1FF, 0x0000);
DEF_P_OP (NOP, FMT_, 0xFE00, 0x0000);

DEF_INST (BR, FMT_CL, 0xF000, 0x0000, FLG_NONE, {
    if ((REG (R_PSR) & I_CC) != 0)
	REG (R_PC) = (REG (R_PC) + I_imm9) & 0xFFFF;
});

DEF_P_OP (RET, FMT_, 0xFFFF, 0xC1C0);

DEF_INST (JMP, FMT_R, 0xFE3F, 0xC000, FLG_NONE, {
    if (I_BaseR == R_R7) {
        ADD_FLAGS (FLG_RETURN);
    }
    REG (R_PC) = REG (I_BaseR);
});

DEF_INST (JSR, FMT_L, 0xF800, 0x4800, FLG_SUBROUTINE, {
    REG (R_R7) = REG (R_PC);
    REG (R_PC) = (REG (R_PC) + I_imm11) & 0xFFFF;
});

/* JSRR -- note that definition does not match second edition of book,
   but intention is to change in 3rd+ printing or 3rd edition. */
DEF_INST (JSRR, FMT_R, 0xFE3F, 0x4000, FLG_SUBROUTINE, {
    int tmp = REG (I_BaseR);
    REG (R_R7) = REG (R_PC);
    REG (R_PC) = tmp;
});

DEF_INST (LD, FMT_RL, 0xF000, 0x2000, FLG_NONE, {
    REG (I_DR) = read_memory ((REG (R_PC) + I_imm9) & 0xFFFF);
    SET_CC ();
});

DEF_INST (LDI, FMT_RL, 0xF000, 0xA000, FLG_NONE, {
    REG (I_DR) = read_memory (read_memory ((REG (R_PC) + I_imm9) & 0xFFFF));
    SET_CC ();
});

DEF_INST (LDR, FMT_RRI6, 0xF000, 0x6000, FLG_NONE, {
    REG (I_DR) = read_memory ((REG (I_BaseR) + I_imm6) & 0xFFFF);
    SET_CC ();
});

DEF_INST (LEA, FMT_RL, 0xF000, 0xE000, FLG_NONE, {
    REG (I_DR) = (REG (R_PC) + I_imm9) & 0xFFFF;
    SET_CC ();
});

DEF_INST (NOT, FMT_RR, 0xF03F, 0x903F, FLG_NONE, {
    REG (I_DR) = (REG (I_SR1) ^ 0xFFFF);
    SET_CC ();
}); 

/* RTI */
DEF_P_OP (RTI, FMT_, 0xFFFF, 0x8000);
/* Illegal without privilege mode, so left out...caught by illegal 
   instruction detection for now. */

DEF_INST (ST, FMT_RL, 0xF000, 0x3000, FLG_NONE, {
    write_memory ((REG (R_PC) + I_imm9) & 0xFFFF, REG (I_SR));
});

DEF_INST (STI, FMT_RL, 0xF000, 0xB000, FLG_NONE, {
    write_memory (read_memory ((REG (R_PC) + I_imm9) & 0xFFFF), REG (I_SR));
});

DEF_INST (STR, FMT_RRI6, 0xF000, 0x7000, FLG_NONE, {
    write_memory ((REG (I_BaseR) + I_imm6) & 0xFFFF, REG (I_SR));
});

DEF_P_OP (GETC,  FMT_, 0xFFFF, 0xF020);
DEF_P_OP (OUT,   FMT_, 0xFFFF, 0xF021);
DEF_P_OP (PUTS,  FMT_, 0xFFFF, 0xF022);
DEF_P_OP (IN,    FMT_, 0xFFFF, 0xF023);
DEF_P_OP (PUTSP, FMT_, 0xFFFF, 0xF024);
DEF_P_OP (HALT,  FMT_, 0xFFFF, 0xF025);

DEF_INST (TRAP, FMT_V, 0xFF00, 0xF000, FLG_SUBROUTINE, {
    REG (R_R7) = REG (R_PC);
    REG (R_PC) = read_memory (I_vec8);
});

/* for anything else, assume that it's data... */
DEF_P_OP (.FILL, FMT_16, 0x0000, 0x0000);

/* Undefine the field access macros. */
#undef INST
#undef I_DR
#undef I_SR1
#undef I_SR2
#undef I_BaseR
#undef I_SR
#undef I_CC
#undef I_vec8
#undef I_imm5
#undef I_imm6
#undef I_imm9
#undef I_imm11

/* Undefine operation macro. */
#undef SET_CC