From 8c6a50ee885121704fedd45c18d0a9dcc376ce3f Mon Sep 17 00:00:00 2001 From: Rosie Yohannan Date: Fri, 26 Oct 2018 10:51:01 +0100 Subject: [PATCH] update sdaccel --- addition/glide.lock | 11 - addition/glide.yaml | 2 +- .../ReconfigureIO/sdaccel/framework.go | 10 +- .../ReconfigureIO/sdaccel/smi/protocol.go | 146 ++- .../sdaccel/verilog/sda_kernel_ctrl_param.v | 303 ------ .../sdaccel/verilog/sda_kernel_ctrl_reg.v | 357 ------- .../sdaccel/verilog/sda_kernel_ctrl_reg_sel.v | 651 ------------ .../verilog/sda_kernel_reset_handler.v | 259 ----- .../sdaccel/verilog/sda_kernel_wrapper_gmem.v | 390 -------- histogram-array/glide.lock | 9 - histogram-array/glide.yaml | 4 +- .../ReconfigureIO/sdaccel/framework.go | 10 +- .../ReconfigureIO/sdaccel/smi/protocol.go | 146 ++- .../sdaccel/verilog/sda_kernel_ctrl_param.v | 303 ------ .../sdaccel/verilog/sda_kernel_ctrl_reg.v | 357 ------- .../sdaccel/verilog/sda_kernel_ctrl_reg_sel.v | 651 ------------ .../verilog/sda_kernel_reset_handler.v | 259 ----- .../sdaccel/verilog/sda_kernel_wrapper_gmem.v | 390 -------- histogram-parallel/glide.lock | 12 - histogram-parallel/glide.yaml | 2 +- .../ReconfigureIO/sdaccel/framework.go | 10 +- .../ReconfigureIO/sdaccel/smi/protocol.go | 146 ++- .../sdaccel/verilog/sda_kernel_ctrl_param.v | 303 ------ .../sdaccel/verilog/sda_kernel_ctrl_reg.v | 357 ------- .../sdaccel/verilog/sda_kernel_ctrl_reg_sel.v | 651 ------------ .../verilog/sda_kernel_reset_handler.v | 259 ----- .../sdaccel/verilog/sda_kernel_wrapper_gmem.v | 390 -------- memcopy/glide.lock | 12 - memcopy/glide.yaml | 2 +- .../ReconfigureIO/sdaccel/framework.go | 10 +- .../ReconfigureIO/sdaccel/smi/protocol.go | 146 ++- .../sdaccel/verilog/sda_kernel_ctrl_param.v | 303 ------ .../sdaccel/verilog/sda_kernel_ctrl_reg.v | 357 ------- .../sdaccel/verilog/sda_kernel_ctrl_reg_sel.v | 651 ------------ .../verilog/sda_kernel_reset_handler.v | 259 ----- .../sdaccel/verilog/sda_kernel_wrapper_gmem.v | 390 -------- scripts/files/glide.lock | 11 - scripts/files/glide.yaml | 2 +- .../ReconfigureIO/sdaccel/.gitignore | 16 + .../ReconfigureIO/sdaccel/.travis.yml | 36 + .../ReconfigureIO/sdaccel/CODE_OF_CONDUCT.md | 46 + .../github.com/ReconfigureIO/sdaccel/LICENSE | 29 + .../github.com/ReconfigureIO/sdaccel/Makefile | 28 + .../ReconfigureIO/sdaccel/README.md | 43 + .../sdaccel/axi/arbitrate/axiarbitrate.go | 428 ++++++++ .../ReconfigureIO/sdaccel/axi/axi.go | 1 + .../sdaccel/axi/memory/aximemory.go | 934 ++++++++++++++++++ .../sdaccel/axi/protocol/axiprotocol.go | 98 ++ .../ReconfigureIO/sdaccel/cmd/fix/doc.go | 37 + .../ReconfigureIO/sdaccel/cmd/fix/fix.go | 848 ++++++++++++++++ .../ReconfigureIO/sdaccel/cmd/fix/main.go | 258 +++++ .../ReconfigureIO/sdaccel/cmd/fix/sdaccel.go | 31 + .../ReconfigureIO/sdaccel/control/control.go | 70 ++ .../ReconfigureIO/sdaccel/docker-compose.yml | 7 + .../ReconfigureIO/sdaccel/framework.go | 10 + .../ReconfigureIO/sdaccel/xcl/fake.go | 220 +++++ .../ReconfigureIO/sdaccel/xcl/xcl.c | 496 ++++++++++ .../ReconfigureIO/sdaccel/xcl/xcl.go | 313 ++++++ .../ReconfigureIO/sdaccel/xcl/xcl.h | 239 +++++ 59 files changed, 4626 insertions(+), 8093 deletions(-) delete mode 100644 addition/glide.lock delete mode 100644 addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v delete mode 100644 addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v delete mode 100644 addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v delete mode 100644 addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v delete mode 100644 addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v delete mode 100644 histogram-array/glide.lock delete mode 100644 histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v delete mode 100644 histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v delete mode 100644 histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v delete mode 100644 histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v delete mode 100644 histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v delete mode 100644 histogram-parallel/glide.lock delete mode 100644 histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v delete mode 100644 histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v delete mode 100644 histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v delete mode 100644 histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v delete mode 100644 histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v delete mode 100644 memcopy/glide.lock delete mode 100644 memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v delete mode 100644 memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v delete mode 100644 memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v delete mode 100644 memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v delete mode 100644 memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v delete mode 100644 scripts/files/glide.lock create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.gitignore create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.travis.yml create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/CODE_OF_CONDUCT.md create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/LICENSE create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/Makefile create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/README.md create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/arbitrate/axiarbitrate.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/axi.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/memory/aximemory.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/protocol/axiprotocol.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/doc.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/fix.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/main.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/sdaccel.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/control/control.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/docker-compose.yml create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/framework.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/fake.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.c create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.go create mode 100644 scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.h diff --git a/addition/glide.lock b/addition/glide.lock deleted file mode 100644 index 4c1cab7..0000000 --- a/addition/glide.lock +++ /dev/null @@ -1,11 +0,0 @@ -hash: 41a07f75fbdf1e4320e20ff25013946d9e42ae156470619ddb490fdd73a04732 -updated: 2018-08-24T16:57:02.046053+01:00 -imports: -- name: github.com/ReconfigureIO/sdaccel - version: 59bbcfa609e6dbc4af7ae0fbae373844f0a8ca3e - subpackages: - - axi/memory - - axi/protocol - - smi - - xcl -testImports: [] diff --git a/addition/glide.yaml b/addition/glide.yaml index ab1940a..3df5d83 100644 --- a/addition/glide.yaml +++ b/addition/glide.yaml @@ -1,7 +1,7 @@ package: . import: - package: github.com/ReconfigureIO/sdaccel - version: ~0.18.0 + version: ~0.20.1 subpackages: - axi/memory - axi/protocol diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/framework.go b/addition/vendor/github.com/ReconfigureIO/sdaccel/framework.go index abd3c23..ba4a82c 100644 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/framework.go +++ b/addition/vendor/github.com/ReconfigureIO/sdaccel/framework.go @@ -1,10 +1,8 @@ +// +// TODO: This no longer does anything useful, so should be deleted once it is +// no longer referenced by example code. +// package sdaccel -// #include verilog/sda_kernel_reset_handler.v -// #include verilog/sda_kernel_ctrl_reg_sel.v -// #include verilog/sda_kernel_ctrl_reg.v -// #include verilog/sda_kernel_ctrl_param.v -// #include verilog/sda_kernel_wrapper_gmem.v - func init() { } diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go b/addition/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go index 6d00f95..3d76a63 100644 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go +++ b/addition/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go @@ -68,24 +68,31 @@ type Flit64 struct { // TODO: Update once there is a fix for the channel size compiler limitation. // func ForwardFrame64( + forwardReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + forwardDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - go func() { - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } - }() + doForward := <-forwardReq + for doForward { + go func() { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } + }() - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + forwardDone <- true + doForward = <-forwardReq } } @@ -98,22 +105,29 @@ func ForwardFrame64( // TODO: Update once there is a fix for the channel size compiler limitation. // func AssembleFrame64( + assembleReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + assembleDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } + doAssemble := <-assembleReq + for doAssemble { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + assembleDone <- true + doAssemble = <-assembleReq } } @@ -1387,18 +1401,24 @@ func WriteBurstUInt64( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt64( + thisWriteOk := writeSingleBurstUInt64( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1427,18 +1447,24 @@ func WriteBurstUInt32( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt32( + thisWriteOk := writeSingleBurstUInt32( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1467,18 +1493,24 @@ func WriteBurstUInt16( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt16( + thisWriteOk := writeSingleBurstUInt16( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1505,18 +1537,24 @@ func WriteBurstUInt8( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt8( + thisWriteOk := writeSingleBurstUInt8( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -2026,18 +2064,24 @@ func ReadBurstUInt64( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt64( + thisReadOk := readSingleBurstUInt64( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2066,18 +2110,24 @@ func ReadBurstUInt32( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt32( + thisReadOk := readSingleBurstUInt32( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2106,18 +2156,24 @@ func ReadBurstUInt16( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt16( + thisReadOk := readSingleBurstUInt16( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2144,17 +2200,23 @@ func ReadBurstUInt8( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt8( + thisReadOk := readSingleBurstUInt8( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v b/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v deleted file mode 100644 index 406a034..0000000 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v +++ /dev/null @@ -1,303 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implements the parameter RAM block which is provided on the AXI control bus -// for assigning kernel parameters prior to running kernel code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_param - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, - paramAddrValid, paramAddr, paramAddrStop, paramDataValid, paramData, - paramDataStop, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 12; - -// Specifies the base address of the parameter block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter ParamAddrBase = 64; - -// Specifies the upper address of the parameter block. -parameter ParamAddrTop = 4095; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; - -// Kernel interface parameter access signals. -input paramAddrValid; -input [31:0] paramAddr; -output paramAddrStop; -output paramDataValid; -output [31:0] paramData; -input paramDataStop; - -// System level signals. -input clk; -input srst; - -// Inferred RAM. -reg [31:0] ramArray [(ParamAddrTop-ParamAddrBase+1)/4-1:0]; - -// Pipelined register interface input inputs. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; -reg [RegAddrWidth-3:0] regAddr_q; - -// Pipelined register interface output inputs. -reg regAck_q; -reg regReadDone_q; -reg regReadValid_q; -reg [31:0] regRData_q; -reg [31:0] regReadData_q; -reg [31:0] regPipeData_q; - -// Pipelined parameter RAM access signals. -reg paramAddrValid_q; -reg [31:0] paramAddr_q; -reg paramDataValid_q; -reg [31:0] paramData_q; - -// Parameter RAM access backpressure signals. -wire pmAddrStop; -wire pmReadStop; -wire pmPipeStop; - -// Parameter RAM access pipeline. -reg [RegAddrWidth-3:0] pmAddr_q; -reg [1:0] pmAddrAlign_q; -reg pmAddrValid_q; -reg [31:0] pmReadData_q; -reg [1:0] pmReadAlign_q; -reg pmReadValid_q; -reg [31:0] pmPipeData_q; -reg [1:0] pmPipeAlign_q; -reg pmPipeValid_q; -reg [31:0] pmDataAligned; - -// Miscellaneous signals. -wire [RegAddrWidth-1:0] regParamAddrBase = ParamAddrBase [RegAddrWidth-1:0]; -wire [RegAddrWidth-1:0] regParamAddrTop = ParamAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipelined register input signals. Assumes that there are no back -// to back transactions, so we can use rising edge detection on the request line. -// verilator lint_off CMPCONST -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regWData_q <= regWData; - regWStrb_q <= regWStrb; - if ((regAddr < regParamAddrBase) || (regAddr > regParamAddrTop)) - begin - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regAddr_q <= regAddr[RegAddrWidth-1:2] - (ParamAddrBase/4); - end - end -end -// verilator lint_on CMPCONST - -// Implement pipelined register output signals. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regReadDone_q <= 1'b0; - regReadValid_q <= 1'b0; - regRData_q <= 32'b0; - end - else - begin - regAck_q <= regReadValid_q | regWriteReq_q; - regReadDone_q <= regReadReq_q; - regReadValid_q <= regReadDone_q; - regRData_q <= regReadValid_q ? regPipeData_q : 32'b0; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; - -// Implement pipelined parameter address inputs. -always @(posedge clk) -begin - if (srst) - begin - paramAddrValid_q <= 1'b0; - paramAddr_q <= 32'b0; - end - else if (paramAddrValid_q) - begin - paramAddrValid_q <= pmAddrStop; - end - else - begin - paramAddrValid_q <= paramAddrValid; - paramAddr_q <= paramAddr; - end -end - -assign paramAddrStop = paramAddrValid_q; - -// Implement the parameter data RAM access backpressure signals. -assign pmAddrStop = pmReadStop & pmAddrValid_q; -assign pmReadStop = pmPipeStop & pmReadValid_q; -assign pmPipeStop = paramDataValid_q & pmPipeValid_q; - -// Implement parameter access input pipeline. -always @(posedge clk) -begin - if (srst) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrValid_q <= 1'b0; - pmReadValid_q <= 1'b0; - pmPipeValid_q <= 1'b0; - end - else - begin - if (~pmAddrStop) - begin - pmAddrValid_q <= paramAddrValid_q; - if ((paramAddr_q < ParamAddrBase) || (paramAddr_q > ParamAddrTop)) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrAlign_q <= 2'b0; - end - else - begin - pmAddr_q <= paramAddr_q[RegAddrWidth-1:2] - (ParamAddrBase/4); - pmAddrAlign_q <= paramAddr_q[1:0]; - end - end - if (~pmReadStop) - begin - pmReadValid_q <= pmAddrValid_q; - pmReadAlign_q <= pmAddrAlign_q; - end - if (~pmPipeStop) - begin - pmPipeValid_q <= pmReadValid_q; - pmPipeAlign_q <= pmReadAlign_q; - end - end -end - -// Perform data alignment on read data. Uses the least significant bits of the -// parameter address to rotate the addressed byte into the LSB position. When -// combined with a suitable type cast in the kernel code, this allows byte and -// half word parameter values to be addressed on byte and half word boundaries. -always @(pmPipeAlign_q, pmPipeData_q) -begin - case (pmPipeAlign_q) - 2'b11 : pmDataAligned = {pmPipeData_q [23:0], pmPipeData_q [31:24]}; - 2'b10 : pmDataAligned = {pmPipeData_q [15:0], pmPipeData_q [31:16]}; - 2'b01 : pmDataAligned = {pmPipeData_q [7:0], pmPipeData_q [31:8]}; - default: pmDataAligned = pmPipeData_q; - endcase -end - -// Provide output pipeline register for read data. -always @(posedge clk) -begin - if (srst) - begin - paramDataValid_q <= 1'b0; - paramData_q <= 32'b0; - end - else if (paramDataValid_q) - begin - paramDataValid_q <= paramDataStop; - end - else - begin - paramDataValid_q <= pmPipeValid_q; - paramData_q <= pmDataAligned; - end -end - -assign paramDataValid = paramDataValid_q; -assign paramData = paramData_q; - -// Implement parameter RAM. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmReadStop) - begin - pmReadData_q <= ramArray [pmAddr_q]; - end - - // Register read pipeline is a single cycle delay. - regReadData_q <= ramArray [regAddr_q]; - - // Apply write enable strobes. - if (regWriteReq_q) - begin - if (regWStrb_q[0]) - ramArray [regAddr_q][7:0] <= regWData_q [7:0]; - if (regWStrb_q[1]) - ramArray [regAddr_q][15:8] <= regWData_q [15:8]; - if (regWStrb_q[2]) - ramArray [regAddr_q][23:16] <= regWData_q [23:16]; - if (regWStrb_q[3]) - ramArray [regAddr_q][31:24] <= regWData_q [31:24]; - end -end - -// Pipeline read data for improved timing. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmPipeStop) - begin - pmPipeData_q <= pmReadData_q; - end - - // Register read pipeline is a single cycle delay. - regPipeData_q <= regReadData_q; - -end - -endmodule diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v b/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v deleted file mode 100644 index e25deb8..0000000 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v +++ /dev/null @@ -1,357 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control registers. This is a set of -// four registers which are located at address offset 0 in the SDAccel kernel -// control register space. -// -// The control unit uses the standard register layout for the SDAccel control -// register. For the basic control register this is as follows: -// Bit 0: start signal (R/W) - Start processing data when this bit is set. -// The state of bit 0 will be cleared on start of processing. -// Bit 1: done signal (RO) - Asserted when the processing is done. -// The state of bit 1 will be cleared on reads. -// Bit 2: idle signal (RO) - Asserted when not processing any data. -// The state of bit 2 will be cleared on starting a new processing cycle. -// Bit 3: ready signal (RO) - Asserted when ready to start processing. -// The state of bit 3 will be cleared on starting a new processing cycle. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, goValid, - goHoldoff, doneValid, doneStop, kernelIntr, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 8; - -// Specifies the upper address of the reserved address block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter RegAddrTop = 63; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. The full register interface is implemented -// even though some of the register write bus is not used. -// verilator lint_off UNUSED -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; -// verilator lint_on UNUSED - -// Specify action go SELF control handshake signals. -output goValid; -input goHoldoff; - -// Specify action done SELF control handshake signals. -input doneValid; -output doneStop; - -// System level signals. -output kernelIntr; -input clk; -input srst; - -// Specify the register layout using byte offsets. Note that valid accesses -// must be aligned to 32-bit word boundaries. -parameter [31:0] - REG_ADDR_CTRL = 'h00, - REG_ADDR_GIE = 'h04, - REG_ADDR_IER = 'h08, - REG_ADDR_ISR = 'h0C; - -// Pipeline the register interface input signals. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg regWData0_q; -reg regWData1_q; -reg regWStrb0_q; -reg [RegAddrWidth-1:0] regAddr_q; - -// Specify the control register bit signals. -reg ctrlBitStart_d; -reg ctrlBitDone_d; -reg ctrlBitIdle_d; -reg ctrlBitReady_d; -reg goValid_d; - -reg ctrlBitStart_q; -reg ctrlBitDone_q; -reg ctrlBitIdle_q; -reg ctrlBitReady_q; -reg goValid_q; - -// Specify the interrupt enable register bit signals. -reg gieBitEnable_d; -reg ierBitDoneEn_d; -reg ierBitReadyEn_d; - -reg gieBitEnable_q; -reg ierBitDoneEn_q; -reg ierBitReadyEn_q; - -// Specify the interrupt status register bit signals. -reg isrBitDone_d; -reg isrBitReady_d; - -reg isrBitDone_q; -reg isrBitReady_q; - -// Specify the read pipeline signals. -reg regAck_d; -reg [31:0] regRData_d; - -reg regAck_q; -reg [31:0] regRData_q; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [RegAddrWidth-1:0] regAddrTop = RegAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipeined register read interface signals. Assumes that there are -// no back to back transactions, so we can use rising edge detection on the -// request line. -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData0_q <= 1'b0; - regWData1_q <= 1'b0; - regWStrb0_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regWData0_q <= regWData[0]; - regWData1_q <= regWData[1]; - regWStrb0_q <= regWStrb[0]; - regAddr_q <= regAddr; - end -end - -// Implement combinatorial logic for controlling register bit state. -always @(ctrlBitStart_q, ctrlBitDone_q, ctrlBitIdle_q, ctrlBitReady_q, - goValid_q, regReadReq_q, regWriteReq_q, regAddr_q, regWData0_q, regWStrb0_q, - goHoldoff, doneValid) -begin - - // Hold current state by default. - ctrlBitStart_d = ctrlBitStart_q; - ctrlBitDone_d = ctrlBitDone_q; - ctrlBitIdle_d = ctrlBitIdle_q; - ctrlBitReady_d = ctrlBitIdle_q & ~goHoldoff; - goValid_d = goValid_q; - - // Clear the 'done' bit on reads. - if (regReadReq_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitDone_d = 1'b0; - end - - // Assert the 'start' bit on register write requests. - if (regWriteReq_q & regWStrb0_q & regWData0_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitStart_d = 1'b1; - end - - // Attempt to initiate the SDAccel kernel operation. - if (ctrlBitStart_q & ctrlBitReady_q) - begin - if (goValid_q & ~goHoldoff) - begin - ctrlBitStart_d = 1'b0; - ctrlBitIdle_d = 1'b0; - ctrlBitReady_d = 1'b0; - goValid_d = 1'b0; - end - else - begin - goValid_d = 1'b1; - end - end - - // Detect completion of the SDAccel kernel operation. - if (~ctrlBitIdle_q & doneValid) - begin - ctrlBitDone_d = 1'b1; - ctrlBitIdle_d = 1'b1; - end - -end - -// Implement sequential logic for register bit values. -always @(posedge clk) -begin - if (srst) - begin - ctrlBitStart_q <= 1'b0; - ctrlBitDone_q <= 1'b0; - ctrlBitIdle_q <= 1'b1; - ctrlBitReady_q <= 1'b0; - goValid_q <= 1'b0; - end - else - begin - ctrlBitStart_q <= ctrlBitStart_d; - ctrlBitDone_q <= ctrlBitDone_d; - ctrlBitIdle_q <= ctrlBitIdle_d; - ctrlBitReady_q <= ctrlBitReady_d; - goValid_q <= goValid_d; - end -end - -assign goValid = goValid_q; -assign doneStop = ctrlBitIdle_q; - -// Implement combinatorial logic for interrupt enable registers. -always @(gieBitEnable_q, ierBitDoneEn_q, ierBitReadyEn_q, regWriteReq_q, - regAddr_q, regWData0_q, regWData1_q, regWStrb0_q) -begin - - // Hold current state by default. - gieBitEnable_d = gieBitEnable_q; - ierBitDoneEn_d = ierBitDoneEn_q; - ierBitReadyEn_d = ierBitReadyEn_q; - - // Set the global interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0])) - begin - gieBitEnable_d = regWData0_q; - end - - // Set the IP core interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0])) - begin - ierBitDoneEn_d = regWData0_q; - ierBitReadyEn_d = regWData1_q; - end -end - -// Implement combinatorial logic for interrupt status register. This is a bit -// unconventional in that it allows the software to set interrupt status bits -// by toggling them. However this matches the Xilinx implementation since it -// may be a requirement for their closed source OpenCL software. -always @(isrBitDone_q, isrBitReady_q, ierBitDoneEn_q, ierBitReadyEn_q, - regWriteReq_q, regAddr_q, regWData0_q, regWData1_q, regWStrb0_q, - ctrlBitDone_q, ctrlBitReady_q) -begin - - // Hold current state by default. - isrBitDone_d = isrBitDone_q; - isrBitReady_d = isrBitReady_q; - - // Toggle the ISR bits under software control. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0])) - begin - isrBitDone_d = isrBitDone_d ^ regWData0_q; - isrBitReady_d = isrBitReady_d ^ regWData1_q; - end - - // Assert the ISR bits on the 'done' and 'ready' signals. - isrBitDone_d = isrBitDone_d | ctrlBitDone_q; - isrBitReady_d = isrBitReady_d | ctrlBitReady_q; - - // Force ISR bits low if not enabled. - isrBitDone_d = isrBitDone_d & ierBitDoneEn_q; - isrBitReady_d = isrBitReady_d & ierBitReadyEn_q; - -end - -// Implement sequential logic for all interrupt registers. -always @(posedge clk) -begin - if (srst) - begin - gieBitEnable_q <= 1'b0; - ierBitDoneEn_q <= 1'b0; - ierBitReadyEn_q <= 1'b0; - isrBitDone_q <= 1'b0; - isrBitReady_q <= 1'b0; - end - else - begin - gieBitEnable_q <= gieBitEnable_d; - ierBitDoneEn_q <= ierBitDoneEn_d; - ierBitReadyEn_q <= ierBitReadyEn_d; - isrBitDone_q <= isrBitDone_d; - isrBitReady_q <= isrBitReady_d; - end -end - -// Implement combinatorial read register. -always @(regReadReq_q, regWriteReq_q, regAddr_q, ctrlBitIdle_q, ctrlBitDone_q, - ctrlBitStart_q, ctrlBitReady_q, gieBitEnable_q, ierBitDoneEn_q, - ierBitReadyEn_q, isrBitDone_q, isrBitReady_q, zeros, regAddrTop) -begin - - // Implement the read mux. - if (regReadReq_q) - begin - if (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0]) - regRData_d = {zeros[31:4], ctrlBitReady_q, - ctrlBitIdle_q, ctrlBitDone_q, ctrlBitStart_q}; - else if (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0]) - regRData_d = {zeros[31:1], gieBitEnable_q}; - else if (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], ierBitReadyEn_q, ierBitDoneEn_q}; - else if (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], isrBitReady_q, isrBitDone_q}; - else - regRData_d = zeros[31:0]; - end - else - begin - regRData_d = zeros[31:0]; - end - - // Acknowledge all accesses to the reserved register set. - if (regAddr_q <= regAddrTop) - regAck_d = regReadReq_q | regWriteReq_q; - else - regAck_d = 1'b0; - -end - -// Implement sequential read register. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regRData_q <= zeros[31:0]; - end - else - begin - regAck_q <= regAck_d; - regRData_q <= regRData_d; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; -assign kernelIntr = gieBitEnable_q & (isrBitDone_q | isrBitReady_q); - -endmodule diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v b/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v deleted file mode 100644 index 67e6ac0..0000000 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v +++ /dev/null @@ -1,651 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control register selection unit. It -// maps the specified number of AXI slave interface registers at the start of -// the AXI address space to simple wrapper control registers and then maps the -// remaining locations to the AXI interface handler in the generated code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg_sel - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiWValid, sAxiWReady, sAxiWData, - sAxiWStrb, sAxiBValid, sAxiBReady, sAxiBResp, sAxiARValid, sAxiARReady, - sAxiARAddr, sAxiRValid, sAxiRReady, sAxiRData, sAxiRResp, mAxiAWValid, - mAxiAWReady, mAxiAWAddr, mAxiWValid, mAxiWReady, mAxiWData, mAxiWStrb, - mAxiBValid, mAxiBReady, mAxiBResp, mAxiARValid, mAxiARReady, mAxiARAddr, - mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, regReq, regAck, regWriteEn, - regAddr, regWData, regWStrb, regRData, clk, srst); - -// Specifies the width of the AXI address bus. -parameter AddrWidth = 16; - -// Specifies the width of the local register set address bus. -parameter RegAddrWidth = 8; - -// Specify the upper address location which is mapped to the local register set. -parameter RegAddrTop = 255; - -// Slave side AXI write address channel signals. -input sAxiAWValid; -output sAxiAWReady; -input [AddrWidth-1:0] sAxiAWAddr; - -// Slave side AXI write data channel signals. -input sAxiWValid; -output sAxiWReady; -input [31:0] sAxiWData; -input [3:0] sAxiWStrb; - -// Slave side AXI write acknowledgement channel signals. -output sAxiBValid; -input sAxiBReady; -output [1:0] sAxiBResp; - -// Slave side AXI read address channel signals. -input sAxiARValid; -output sAxiARReady; -input [AddrWidth-1:0] sAxiARAddr; - -// Slave side AXI read data channel signals. -output sAxiRValid; -input sAxiRReady; -output [31:0] sAxiRData; -output [1:0] sAxiRResp; - -// Master side AXI write address channel signals. -output mAxiAWValid; -input mAxiAWReady; -output [AddrWidth-1:0] mAxiAWAddr; - -// Master side AXI write data channel signals. -output mAxiWValid; -input mAxiWReady; -output [31:0] mAxiWData; -output [3:0] mAxiWStrb; - -// Master side AXI write acknowledgement channel signals. -input mAxiBValid; -output mAxiBReady; -input [1:0] mAxiBResp; - -// Master side AXI read address channel signals. -output mAxiARValid; -input mAxiARReady; -output [AddrWidth-1:0] mAxiARAddr; - -// Slave side AXI read data channel signals. -input mAxiRValid; -output mAxiRReady; -input [31:0] mAxiRData; -input [1:0] mAxiRResp; - -// Master side simple register interface signals. -output regReq; -input regAck; -output regWriteEn; -output [RegAddrWidth-1:0] regAddr; -output [31:0] regWData; -output [3:0] regWStrb; -input [31:0] regRData; - -// System level signals. -input clk; -input srst; - -// AXI write address channel register signals. -wire sAxiAWPending; -reg sAxiAWClear; -wire [AddrWidth-1:0] sAxiAWAddrReg; -reg mAxiAWPush; -wire mAxiAWBlocked; -wire [AddrWidth-1:0] mAxiAWAddrReg; - -// AXI write data channel register signals. -wire sAxiWPending; -reg sAxiWClear; -wire [31:0] sAxiWDataReg; -wire [3:0] sAxiWStrbReg; -reg mAxiWPush; -wire mAxiWBlocked; -wire [31:0] mAxiWDataReg; -wire [3:0] mAxiWStrbReg; - -// AXI read address channel register signals. -wire sAxiARPending; -reg sAxiARClear; -wire [AddrWidth-1:0] sAxiARAddrReg; -reg mAxiARPush; -wire mAxiARBlocked; -wire [AddrWidth-1:0] mAxiARAddrReg; - -// AXI write response channel register signals. -wire mAxiBPending; -reg mAxiBClear; -wire [1:0] mAxiBRespReg; -reg sAxiBPush; -wire sAxiBBlocked; -reg [1:0] sAxiBRespReg; - -// AXI read response channel register signals. -wire mAxiRPending; -reg mAxiRClear; -wire [31:0] mAxiRDataReg; -wire [1:0] mAxiRRespReg; -reg sAxiRPush; -wire sAxiRBlocked; -reg [31:0] sAxiRDataReg; -reg [1:0] sAxiRRespReg; - -// Specify the state space used to select the AXI transaction mode. -parameter [3:0] - Idle = 0, - RegReadStart = 1, - RegReadActive = 2, - RegWriteStart = 3, - RegWriteActive = 4, - AxiReadStart = 5, - AxiReadActive = 6, - AxiWriteStart = 7, - AxiWriteData = 8, - AxiWriteActive = 9; - -// Specify AXI state machine registers. -reg [3:0] axiState_d; -reg regReq_d; -reg regWriteEn_d; -reg [RegAddrWidth-1:0] regAddr_d; -reg [31:0] regWData_d; -reg [3:0] regWStrb_d; - -reg [3:0] axiState_q; -reg regReq_q; -reg regWriteEn_q; -reg [RegAddrWidth-1:0] regAddr_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; - -// Miscellaneous signals. -wire [AddrWidth-1:0] regAddrTop = RegAddrTop [AddrWidth-1:0]; -integer i; - -// Instantiate input registers for slave side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiAWReg_u - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiAWPending, sAxiAWClear, - sAxiAWAddrReg, clk, srst); - -// Instantiate input registers for slave side AXI data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 4) sAxiWReg_u - (sAxiWValid, sAxiWReady, sAxiWData, sAxiWStrb, sAxiWPending, - sAxiWClear, sAxiWDataReg, sAxiWStrbReg, clk, srst); - -// Instantiate input registers for slave side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiARReg_u - (sAxiARValid, sAxiARReady, sAxiARAddr, sAxiARPending, sAxiARClear, - sAxiARAddrReg, clk, srst); - -// Instantiate input register for master side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(2) mAxiBReg_u - (mAxiBValid, mAxiBReady, mAxiBResp, mAxiBPending, mAxiBClear, mAxiBRespReg, - clk, srst); - -// Instantiate input register for master side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 2) mAxiRReg_u - (mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, mAxiRPending, - mAxiRClear, mAxiRDataReg, mAxiRRespReg, clk, srst); - -// Instantate output register for master side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiAWReg_u - (mAxiAWPush, mAxiAWBlocked, mAxiAWAddrReg, mAxiAWValid, mAxiAWReady, - mAxiAWAddr, clk, srst); - -// Instantiate output register for master side AXI write data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 4) mAxiWReg_u - (mAxiWPush, mAxiWBlocked, mAxiWDataReg, mAxiWStrbReg, mAxiWValid, - mAxiWReady, mAxiWData, mAxiWStrb, clk, srst); - -// Instantiate output register for master side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiARReg_u - (mAxiARPush, mAxiARBlocked, mAxiARAddrReg, mAxiARValid, mAxiARReady, - mAxiARAddr, clk, srst); - -// Instantiate output register for slave side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(2) sAxiBReg_u - (sAxiBPush, sAxiBBlocked, sAxiBRespReg, sAxiBValid, sAxiBReady, sAxiBResp, - clk, srst); - -// Instantiate output register for slave side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 2) sAxiRReg_u - (sAxiRPush, sAxiRBlocked, sAxiRDataReg, sAxiRRespReg, sAxiRValid, - sAxiRReady, sAxiRData, sAxiRResp, clk, srst); - -// Pass through AXI signals where possible. -assign mAxiAWAddrReg = sAxiAWAddrReg; -assign mAxiWDataReg = sAxiWDataReg; -assign mAxiWStrbReg = sAxiWStrbReg; -assign mAxiARAddrReg = sAxiARAddrReg; - -// Implement combinatorial logic for selecting AXI transaction mode. -always @(axiState_q, regReq_q, regWriteEn_q, regAddr_q, regWData_q, regWStrb_q, - sAxiAWPending, sAxiAWAddrReg, sAxiWPending, sAxiWDataReg, sAxiWStrbReg, - sAxiBBlocked, sAxiARPending, sAxiARAddrReg, sAxiRBlocked, mAxiRPending, - mAxiRDataReg, mAxiRRespReg, mAxiAWBlocked, mAxiWBlocked, mAxiBPending, - mAxiARBlocked, mAxiBRespReg, regAck, regRData, regAddrTop) -begin - - // Preserve current state by default. - axiState_d = axiState_q; - regReq_d = regReq_q; - regWriteEn_d = regWriteEn_q; - regAddr_d = regAddr_q; - regWData_d = regWData_q; - regWStrb_d = regWStrb_q; - - // Set default read assignment to register inputs with AXI 'OKAY' response. - sAxiRPush = 1'b0; - sAxiRDataReg = regRData; - sAxiRRespReg = 2'b0; - - // Set default write status assigment to AXI 'OKAY' response. - sAxiBPush = 1'b0; - sAxiBRespReg = 2'b0; - - // Disable AXI register clear strobes by default. - sAxiAWClear = 1'b0; - sAxiWClear = 1'b0; - sAxiARClear = 1'b0; - mAxiBClear = 1'b0; - mAxiRClear = 1'b0; - - // Disable AXI master push strobes by default. - mAxiAWPush = 1'b0; - mAxiWPush = 1'b0; - mAxiARPush = 1'b0; - - // Implement state machine. - case (axiState_q) - - // In the idle state, wait until the AXI write or read address inputs are - // ready. Writes are prioritised over reads. - // verilator lint_off CMPCONST - Idle : - begin - if (sAxiAWPending) - begin - if (sAxiAWAddrReg <= regAddrTop) - axiState_d = RegWriteStart; - else - axiState_d = AxiWriteStart; - end - else if (sAxiARPending) - begin - if (sAxiARAddrReg <= regAddrTop) - axiState_d = RegReadStart; - else - axiState_d = AxiReadStart; - end - end - // verilator lint_on CMPCONST - - // Initiate read transactions on the local register interface. - RegReadStart : - begin - if (~sAxiRBlocked) - begin - axiState_d = RegReadActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b0; - regAddr_d = sAxiARAddrReg [RegAddrWidth-1:0]; - end - end - - // Process active read requests. - RegReadActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiRPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Initiate write transactions to the local register interface. - RegWriteStart : - begin - if (sAxiWPending & ~sAxiBBlocked) - begin - axiState_d = RegWriteActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b1; - regAddr_d = sAxiAWAddrReg [RegAddrWidth-1:0]; - regWData_d = sAxiWDataReg; - regWStrb_d = sAxiWStrbReg; - end - end - - // Process active write requests. - RegWriteActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiBPush = 1'b1; - sAxiAWClear = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Initiate read transaction on the AXI master side. - AxiReadStart : - begin - if (~mAxiARBlocked) - begin - axiState_d = AxiReadActive; - mAxiARPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Complete read transaction from the AXI master side. - AxiReadActive : - begin - sAxiRDataReg = mAxiRDataReg; - sAxiRRespReg = mAxiRRespReg; - if (mAxiRPending & ~sAxiRBlocked) - begin - axiState_d = Idle; - sAxiRPush = 1'b1; - mAxiRClear = 1'b1; - end - end - - // Initiate write transaction on the AXI master side. - AxiWriteStart : - begin - if (~mAxiAWBlocked) - begin - axiState_d = AxiWriteData; - mAxiAWPush = 1'b1; - sAxiAWClear = 1'b1; - end - end - - // Forward write data to the AXI master side. - AxiWriteData : - begin - if (sAxiWPending & ~mAxiWBlocked) - begin - axiState_d = AxiWriteActive; - mAxiWPush = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Complete write transaction from the AXI master side. - AxiWriteActive : - begin - sAxiBRespReg = mAxiBRespReg; - if (mAxiBPending & ~sAxiBBlocked) - begin - axiState_d = Idle; - sAxiBPush = 1'b1; - mAxiBClear = 1'b1; - end - end - - // Map unknown states to Idle. - default : - begin - axiState_d = Idle; - end - endcase -end - -// Implement sequential logic for AXI transaction state machine. -always @(posedge clk) -begin - if (srst) - begin - axiState_q <= Idle; - regReq_q <= 1'b0; - regWriteEn_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q [i] <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - end - else - begin - axiState_q <= axiState_d; - regReq_q <= regReq_d; - regWriteEn_q <= regWriteEn_d; - regAddr_q <= regAddr_d; - regWData_q <= regWData_d; - regWStrb_q <= regWStrb_d; - end -end - -assign regReq = regReq_q; -assign regWriteEn = regWriteEn_q; -assign regAddr = regAddr_q; -assign regWData = regWData_q; -assign regWStrb = regWStrb_q; - -endmodule - -// -// Provides common implementation of single AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x1 - (axiValid, axiReady, axiDataIn, dataPending, dataClear, dataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth-1:0] axiDataIn; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth-1:0] dataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataClear_q; -reg axiReady_q; -reg [DataWidth-1:0] axiDataIn_q; - -integer i; - -// Implements a single AXI input register. -always @(posedge clk) -begin - if (srst | dataClear) - begin - dataClear_q <= 1'b1; - axiReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - axiDataIn_q [i] <= 1'b0; - end - else if (dataClear_q) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b1; - end - else if (axiReady_q & axiValid) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b0; - axiDataIn_q <= axiDataIn; - end -end - -assign axiReady = axiReady_q; -assign dataPending = ~(dataClear_q | axiReady_q); -assign dataOut = axiDataIn_q; - -endmodule - -// -// Provides common implementation of dual AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x2 - (axiValid, axiReady, axiDataIn1, axiDataIn2, dataPending, dataClear, - dataOut1, dataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth1-1:0] axiDataIn1; -input [DataWidth2-1:0] axiDataIn2; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth1-1:0] dataOut1; -output [DataWidth2-1:0] dataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] dataOut; - -// Instantiate the single input register module. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (axiValid, axiReady, {axiDataIn2, axiDataIn1}, dataPending, dataClear, - dataOut, clk, srst); - -assign dataOut1 = dataOut [DataWidth1-1:0]; -assign dataOut2 = dataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - -// -// Provides common implementation of single AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x1 - (dataPush, dataBlocked, dataIn, axiValid, axiReady, axiDataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth-1:0] dataIn; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth-1:0] axiDataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataReady_q; -reg [DataWidth-1:0] dataReg_q; - -integer i; - -// Implements a single AXI output register. -always @(posedge clk) -begin - if (srst) - begin - dataReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - dataReg_q [i] <= 1'b0; - end - else if (dataReady_q & axiReady) - begin - dataReady_q <= 1'b0; - end - else if (dataPush) - begin - dataReady_q <= 1'b1; - dataReg_q <= dataIn; - end -end - -assign dataBlocked = dataReady_q; -assign axiValid = dataReady_q; -assign axiDataOut = dataReg_q; - -endmodule - -// -// Provides common implementation of dual AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x2 - (dataPush, dataBlocked, dataIn1, dataIn2, axiValid, axiReady, axiDataOut1, - axiDataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth1-1:0] dataIn1; -input [DataWidth2-1:0] dataIn2; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth1-1:0] axiDataOut1; -output [DataWidth2-1:0] axiDataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] axiDataOut; - -// Instantiate the single output register module. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (dataPush, dataBlocked, {dataIn2, dataIn1}, axiValid, axiReady, - axiDataOut, clk, srst); - -assign axiDataOut1 = axiDataOut [DataWidth1-1:0]; -assign axiDataOut2 = axiDataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v b/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v deleted file mode 100644 index 925d6d3..0000000 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v +++ /dev/null @@ -1,259 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel reset handler. It provides support for -// managing kernel resets under control of the external 'go' and 'done' control -// signals. -// - -`timescale 1ns/1ps - -module sda_kernel_reset_handler - (regGoValid, regGoHoldoff, regDoneValid, regDoneStop, kernelGoValid, - kernelGoHoldoff, kernelDoneValid, kernelDoneStop, sysRstReq, wrapperReset, - kernelReset, clk); - -// Specifies the reset counter size. The kernel reset line will be asserted for -// the time it takes the counter to wrap. -parameter ResetCountSize = 5; - -// Specifies the length of the reset pipeline, which allows the synthesis tools -// to build a reset tree if required by using register duplication. -parameter ResetPipeLength = 8; - -// Derives the reset counter limit. -parameter ResetCountLimit = (1 << ResetCountSize) - 1; - -// Specify the reset controller state space. -parameter [2:0] - ResetIdle = 0, - ResetTimeout = 1, - KernelStarting = 2, - KernelRunning = 3, - KernelExited = 4; - -// Upstream register interface signals. -input regGoValid; -output regGoHoldoff; -output regDoneValid; -input regDoneStop; - -// Kernel control go output signals. -output kernelGoValid; -input kernelGoHoldoff; -input kernelDoneValid; -output kernelDoneStop; - -// Specifies the system reset request signal and generated resets. -input sysRstReq; -output wrapperReset; -output kernelReset; - -// Specifies the clock input. There is no standard synchronous reset. -input clk; - -// Reset control state machine signals. -reg [2:0] resetState_d; -reg [ResetCountSize-1:0] resetCount_d; -reg kernelReset_d; -reg regGoHoldoff_d; -reg regDoneValid_d; -reg kernelGoValid_d; -reg kernelDoneStop_d; - -reg [2:0] resetState_q; -reg [ResetCountSize-1:0] resetCount_q; -reg kernelReset_q; -reg regGoHoldoff_q; -reg regDoneValid_q; -reg kernelGoValid_q; -reg kernelDoneStop_q; - -// Implements a register with an explicit initialisation value, which will have -// the effect of forcing a reset cycle immediately after loading the FPGA -// netlist. Only works with devices that support bitstream initalisation. -reg resetHandlerEnabled_q = 1'b0; -reg wrapperReset_q; - -// Specifies the reset pipeline signals. -reg [ResetPipeLength-1:0] wrapperResetPipe_q; -reg [ResetPipeLength-1:0] kernelResetPipe_q; - -// Miscellaneous signals. -integer i; - -// Initiate automatic reset on FPGA bitstream load. -always @(posedge clk) -begin - if (sysRstReq | ~resetHandlerEnabled_q) - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b1; - end - else - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b0; - end -end - -// Implement combinatorial logic for reset control state machine. -always @(resetState_q, resetCount_q, kernelReset_q, regGoHoldoff_q, regDoneValid_q, - kernelGoValid_q, kernelDoneStop_q, regGoValid, regDoneStop, kernelGoHoldoff, - kernelDoneValid) -begin - - // Hold current state by default. - resetState_d = resetState_q; - resetCount_d = resetCount_q; - kernelReset_d = kernelReset_q; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - - // Implement state machine. - case (resetState_q) - - // Hold the reset state for the required timeout. - ResetTimeout : - begin - if (resetCount_q == ResetCountLimit [ResetCountSize-1:0]) - begin - resetState_d = ResetIdle; - end - resetCount_d = resetCount_q + 1; - end - - // Wait for the kernel to accept the go signal. - KernelStarting : - begin - if (kernelGoValid_q & ~kernelGoHoldoff) - begin - resetState_d = KernelRunning; - end - else - begin - kernelGoValid_d = 1'b1; - end - end - - // In the kernel runnning state, wait for the 'done' response. - KernelRunning : - begin - if (kernelDoneValid & ~kernelDoneStop_q) - begin - resetState_d = KernelExited; - end - else - begin - kernelDoneStop_d = 1'b0; - end - end - - // In the kernel exited state, notify the control registers and place the - // kernel in reset until the next go request is received. - KernelExited : - begin - if (regDoneValid_q & ~regDoneStop) - begin - resetState_d = ResetTimeout; - kernelReset_d = 1'b1; - end - else - begin - regDoneValid_d = 1'b1; - end - end - - // In the reset idle state, wait for a go request from the register block - // before releasing the kernel reset. - ResetIdle : - begin - if (regGoValid & ~regGoHoldoff_q) - begin - resetState_d = KernelStarting; - kernelReset_d = 1'b0; - end - else - begin - regGoHoldoff_d = 1'b0; - end - end - - // Treat the unreachable default state as a hard reset. This prevents the - // Xilinx tools from generating dangling nets if the state encoding is - // automatically converted to one-hot. - default: - begin - resetState_d = ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_d [i] = 1'b0; - kernelReset_d = 1'b1; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - end - endcase - -end - -// Implement sequential logic for reset control state machine. -always @(posedge clk) -begin - if (wrapperReset_q) - begin - resetState_q <= ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_q [i] <= 1'b0; - kernelReset_q <= 1'b1; - regGoHoldoff_q <= 1'b1; - regDoneValid_q <= 1'b0; - kernelGoValid_q <= 1'b0; - kernelDoneStop_q <= 1'b1; - end - else - begin - resetState_q <= resetState_d; - resetCount_q <= resetCount_d; - kernelReset_q <= kernelReset_d; - regGoHoldoff_q <= regGoHoldoff_d; - regDoneValid_q <= regDoneValid_d; - kernelGoValid_q <= kernelGoValid_d; - kernelDoneStop_q <= kernelDoneStop_d; - end -end - -assign regGoHoldoff = regGoHoldoff_q; -assign regDoneValid = regDoneValid_q; -assign kernelGoValid = kernelGoValid_q; -assign kernelDoneStop = kernelDoneStop_q; - -// Implement reset output pipelines. -always @(posedge clk) -begin - if (wrapperReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - wrapperResetPipe_q [i] <= 1'b1; - else - wrapperResetPipe_q <= { 1'b0, wrapperResetPipe_q [ResetPipeLength-1:1] }; -end - -always @(posedge clk) -begin - if (kernelReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - kernelResetPipe_q [i] <= 1'b1; - else - kernelResetPipe_q <= { 1'b0, kernelResetPipe_q [ResetPipeLength-1:1] }; -end - -assign wrapperReset = wrapperResetPipe_q [0]; -assign kernelReset = kernelResetPipe_q [0]; - -endmodule diff --git a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v b/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v deleted file mode 100644 index 95054a0..0000000 --- a/addition/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v +++ /dev/null @@ -1,390 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Provides the common wrapper code around an existing 'action' block so that it -// can be used in the context of an SDAccel 'kernel' block. This variant -// supports the complete set of control registers at AXI slave offset zero which -// are used to map the SDAccel run/status programming interface to the action -// block run/done SELF handshake lines. This wrapper implements a single AXI -// master interface which can access the shared global memory area on the FPGA -// card. -// - -`timescale 1ns/1ps - -// Can be redefined on the synthesis command line. -`ifndef AXI_SLAVE_ADDR_WIDTH -`define AXI_SLAVE_ADDR_WIDTH 16 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ADDR_WIDTH -`define AXI_MASTER_ADDR_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_DATA_WIDTH -`define AXI_MASTER_DATA_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ID_WIDTH -`define AXI_MASTER_ID_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_USER_WIDTH -`define AXI_MASTER_USER_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_CACHE_MASK -`define AXI_MASTER_CACHE_MASK 4'b0011 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_PARAM_MEM_ADDR_WIDTH -`define AXI_PARAM_MEM_ADDR_WIDTH 12 -`endif - -// Module name to be substituted in post-synthesis netlist. -module sda_kernel_wrapper_gmem - (s_axi_control_AWADDR, s_axi_control_AWVALID, s_axi_control_AWREADY, - s_axi_control_WDATA, s_axi_control_WSTRB, s_axi_control_WVALID, - s_axi_control_WREADY, s_axi_control_BRESP, s_axi_control_BVALID, - s_axi_control_BREADY, s_axi_control_ARADDR, s_axi_control_ARVALID, - s_axi_control_ARREADY, s_axi_control_RDATA, s_axi_control_RRESP, - s_axi_control_RVALID, s_axi_control_RREADY, m_axi_gmem_AWADDR, - m_axi_gmem_AWLEN, m_axi_gmem_AWSIZE, m_axi_gmem_AWBURST, m_axi_gmem_AWLOCK, - m_axi_gmem_AWREGION, m_axi_gmem_AWCACHE, m_axi_gmem_AWPROT, m_axi_gmem_AWQOS, - m_axi_gmem_AWID, m_axi_gmem_AWUSER, m_axi_gmem_AWVALID, m_axi_gmem_AWREADY, - m_axi_gmem_WDATA, m_axi_gmem_WSTRB, m_axi_gmem_WLAST, m_axi_gmem_WID, - m_axi_gmem_WUSER, m_axi_gmem_WVALID, m_axi_gmem_WREADY, m_axi_gmem_BRESP, - m_axi_gmem_BID, m_axi_gmem_BUSER, m_axi_gmem_BVALID, m_axi_gmem_BREADY, - m_axi_gmem_ARADDR, m_axi_gmem_ARLEN, m_axi_gmem_ARSIZE, m_axi_gmem_ARBURST, - m_axi_gmem_ARLOCK, m_axi_gmem_ARREGION, m_axi_gmem_ARCACHE, m_axi_gmem_ARPROT, - m_axi_gmem_ARQOS, m_axi_gmem_ARID, m_axi_gmem_ARUSER, m_axi_gmem_ARVALID, - m_axi_gmem_ARREADY, m_axi_gmem_RDATA, m_axi_gmem_RRESP, m_axi_gmem_RLAST, - m_axi_gmem_RID, m_axi_gmem_RUSER, m_axi_gmem_RVALID, m_axi_gmem_RREADY, - ap_clk, ap_rst_n, interrupt); - -// Specifies the AXI slave write address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_AWADDR; -input s_axi_control_AWVALID; -output s_axi_control_AWREADY; - -// Specifies the AXI slave write data signals. -input [31:0] s_axi_control_WDATA; -input [3:0] s_axi_control_WSTRB; -input s_axi_control_WVALID; -output s_axi_control_WREADY; - -// Specifies the AXI slave write response signals. -output [1:0] s_axi_control_BRESP; -output s_axi_control_BVALID; -input s_axi_control_BREADY; - -// Specifies the AXI slave read address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_ARADDR; -input s_axi_control_ARVALID; -output s_axi_control_ARREADY; - -// Specifies the AXI slave read data signals. -output [31:0] s_axi_control_RDATA; -output [1:0] s_axi_control_RRESP; -output s_axi_control_RVALID; -input s_axi_control_RREADY; - -// Specifies the AXI master write address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_AWADDR; -output [7:0] m_axi_gmem_AWLEN; -output [2:0] m_axi_gmem_AWSIZE; -output [1:0] m_axi_gmem_AWBURST; -output [1:0] m_axi_gmem_AWLOCK; -output [3:0] m_axi_gmem_AWCACHE; -output [2:0] m_axi_gmem_AWPROT; -output [3:0] m_axi_gmem_AWQOS; -output [3:0] m_axi_gmem_AWREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_AWID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_AWUSER; -output m_axi_gmem_AWVALID; -input m_axi_gmem_AWREADY; - -// Specifies the AXI master write data signals. -output [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_WDATA; -output [`AXI_MASTER_DATA_WIDTH/8-1:0] m_axi_gmem_WSTRB; -output m_axi_gmem_WLAST; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_WID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_WUSER; -output m_axi_gmem_WVALID; -input m_axi_gmem_WREADY; - -// Specifies the AXI master write response signals. -input [1:0] m_axi_gmem_BRESP; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_BID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_BUSER; -input m_axi_gmem_BVALID; -output m_axi_gmem_BREADY; - -// Specifies the AXI master read address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_ARADDR; -output [7:0] m_axi_gmem_ARLEN; -output [2:0] m_axi_gmem_ARSIZE; -output [1:0] m_axi_gmem_ARBURST; -output [1:0] m_axi_gmem_ARLOCK; -output [3:0] m_axi_gmem_ARCACHE; -output [2:0] m_axi_gmem_ARPROT; -output [3:0] m_axi_gmem_ARQOS; -output [3:0] m_axi_gmem_ARREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_ARID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_ARUSER; -output m_axi_gmem_ARVALID; -input m_axi_gmem_ARREADY; - -// Specifies the AXI master read data signals. -input [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_RDATA; -input [1:0] m_axi_gmem_RRESP; -input m_axi_gmem_RLAST; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_RID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_RUSER; -input m_axi_gmem_RVALID; -output m_axi_gmem_RREADY; - -// Specifies the system level I/O signals. -input ap_clk; -input ap_rst_n; - -// verilator lint_off SYMRSVDWORD -output interrupt; -// verilator lint_on SYMRSVDWORD - -// Reset management signals. -wire reg_go_valid; -wire reg_go_holdoff; -wire reg_done_valid; -wire reg_done_stop; -wire kernel_reset; -wire wrapper_reset; - -// AXI control interface master write address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_AWADDR; -wire [3:0] m_axi_control_AWCACHE; -wire [2:0] m_axi_control_AWPROT; -wire m_axi_control_AWVALID; -wire m_axi_control_AWREADY; - -// AXI control interface master write data signals. -wire [31:0] m_axi_control_WDATA; -wire [3:0] m_axi_control_WSTRB; -wire m_axi_control_WVALID; -wire m_axi_control_WREADY; - -// AXI control interface master write response signals. -wire [1:0] m_axi_control_BRESP; -wire m_axi_control_BVALID; -wire m_axi_control_BREADY; - -// AXI control interface master read address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_ARADDR; -wire [3:0] m_axi_control_ARCACHE; -wire [2:0] m_axi_control_ARPROT; -wire m_axi_control_ARVALID; -wire m_axi_control_ARREADY; - -// AXI control interface master read data signals. -wire [31:0] m_axi_control_RDATA; -wire [1:0] m_axi_control_RRESP; -wire m_axi_control_RVALID; -wire m_axi_control_RREADY; - -// AXI master interface intermediate signals. -wire [3:0] m_axi_gmem_local_ARCACHE; -wire [3:0] m_axi_gmem_local_AWCACHE; - -// Wrapper control register interface signals. -wire reg_req; -wire reg_ack; -wire reg_ack_0; -wire reg_ack_1; -wire reg_write_en; -wire [`AXI_PARAM_MEM_ADDR_WIDTH-1:0] reg_addr; -wire [31:0] reg_wdata; -wire [3:0] reg_wstrb; -wire [31:0] reg_rdata; -wire [31:0] reg_rdata_0; -wire [31:0] reg_rdata_1; - -// Kernel interface parameter access signals. -wire param_addr_valid; -wire [31:0] param_addr; -wire param_addr_stop; -wire param_data_valid; -wire [31:0] param_data; -wire param_data_stop; - -// Action control signals. -wire go_0Ready; -wire go_0Stop; -wire done_0Ready; -wire done_0Stop; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [31:0] m_axi_control_ext_AWADDR; -wire [31:0] m_axi_control_ext_ARADDR; - -// Tie off unused control interface signals. -assign m_axi_control_AWCACHE = 4'b0000; -assign m_axi_control_AWPROT = 3'b010; -assign m_axi_control_ARCACHE = 4'b0000; -assign m_axi_control_ARPROT = 3'b010; - -// Tie off upper bit of the lock signals for AXI3 backward compatibility. -assign m_axi_gmem_AWLOCK[1] = 1'b0; -assign m_axi_gmem_ARLOCK[1] = 1'b0; - -// Tie off unused WID signal -`ifndef AXI_MASTER_HAS_WID -assign m_axi_gmem_WID = `AXI_MASTER_ID_WIDTH'd0; -`endif - -// Apply cache mask to restrict memory access modes if required. The default -// is to restrict accesses to device mode only, as required by the AWS shell. -assign m_axi_gmem_ARCACHE = m_axi_gmem_local_ARCACHE & `AXI_MASTER_CACHE_MASK; -assign m_axi_gmem_AWCACHE = m_axi_gmem_local_AWCACHE & `AXI_MASTER_CACHE_MASK; - -// Instantiate the reset controller. -sda_kernel_reset_handler resetHandler_u - (reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, go_0Ready, - go_0Stop, done_0Ready, done_0Stop, ~ap_rst_n, wrapper_reset, kernel_reset, - ap_clk); - -// Instantiate the AXI slave register selection component. -sda_kernel_ctrl_reg_sel #(`AXI_SLAVE_ADDR_WIDTH, `AXI_PARAM_MEM_ADDR_WIDTH, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlRegSel_u - (s_axi_control_AWVALID, s_axi_control_AWREADY, s_axi_control_AWADDR, - s_axi_control_WVALID, s_axi_control_WREADY, s_axi_control_WDATA, - s_axi_control_WSTRB, s_axi_control_BVALID, s_axi_control_BREADY, - s_axi_control_BRESP, s_axi_control_ARVALID, s_axi_control_ARREADY, - s_axi_control_ARADDR, s_axi_control_RVALID, s_axi_control_RREADY, - s_axi_control_RDATA, s_axi_control_RRESP, m_axi_control_AWVALID, - m_axi_control_AWREADY, m_axi_control_AWADDR, m_axi_control_WVALID, - m_axi_control_WREADY, m_axi_control_WDATA, m_axi_control_WSTRB, - m_axi_control_BVALID, m_axi_control_BREADY, m_axi_control_BRESP, - m_axi_control_ARVALID, m_axi_control_ARREADY, m_axi_control_ARADDR, - m_axi_control_RVALID, m_axi_control_RREADY, m_axi_control_RDATA, - m_axi_control_RRESP, reg_req, reg_ack, reg_write_en, reg_addr, reg_wdata, - reg_wstrb, reg_rdata, ap_clk, wrapper_reset); - -// Instantiate the kernel control registers at slave address offset 0. -sda_kernel_ctrl_reg #(`AXI_PARAM_MEM_ADDR_WIDTH, 63) kernelCtrlReg_u - (reg_req, reg_ack_0, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_0, - reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, interrupt, ap_clk, - wrapper_reset); - -// Instantiate the kernel parameter memory. -sda_kernel_ctrl_param #(`AXI_PARAM_MEM_ADDR_WIDTH, 64, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlParam_u - (reg_req, reg_ack_1, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_1, - param_addr_valid, param_addr, param_addr_stop, param_data_valid, param_data, - param_data_stop, ap_clk, wrapper_reset); - -assign reg_ack = reg_ack_0 | reg_ack_1; -assign reg_rdata = reg_rdata_0 | reg_rdata_1 | zeros; - -// Extend the slave address bus widths to the standard 32 bit value for the -// action logic core. -assign m_axi_control_ext_AWADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_AWADDR}; -assign m_axi_control_ext_ARADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_ARADDR}; - -// Instantiate the simple generated action logic core. -teak__action__top__gmem kernelActionTop_u ( - .go_0Ready (go_0Ready), - .go_0Stop (go_0Stop), - .done_0Ready (done_0Ready), - .done_0Stop (done_0Stop), - .s_axi_araddr (m_axi_control_ext_ARADDR), - .s_axi_arcache (m_axi_control_ARCACHE), - .s_axi_arprot (m_axi_control_ARPROT), - .s_axi_arvalid (m_axi_control_ARVALID), - .s_axi_arready (m_axi_control_ARREADY), - .s_axi_rdata (m_axi_control_RDATA), - .s_axi_rresp (m_axi_control_RRESP), - .s_axi_rvalid (m_axi_control_RVALID), - .s_axi_rready (m_axi_control_RREADY), - .s_axi_awaddr (m_axi_control_ext_AWADDR), - .s_axi_awcache (m_axi_control_AWCACHE), - .s_axi_awprot (m_axi_control_AWPROT), - .s_axi_awvalid (m_axi_control_AWVALID), - .s_axi_awready (m_axi_control_AWREADY), - .s_axi_wdata (m_axi_control_WDATA), - .s_axi_wstrb (m_axi_control_WSTRB), - .s_axi_wvalid (m_axi_control_WVALID), - .s_axi_wready (m_axi_control_WREADY), - .s_axi_bresp (m_axi_control_BRESP), - .s_axi_bvalid (m_axi_control_BVALID), - .s_axi_bready (m_axi_control_BREADY), - .m_axi_gmem_awaddr (m_axi_gmem_AWADDR), - .m_axi_gmem_awlen (m_axi_gmem_AWLEN), - .m_axi_gmem_awsize (m_axi_gmem_AWSIZE), - .m_axi_gmem_awburst (m_axi_gmem_AWBURST), - .m_axi_gmem_awlock (m_axi_gmem_AWLOCK[0]), - .m_axi_gmem_awcache (m_axi_gmem_local_AWCACHE), - .m_axi_gmem_awprot (m_axi_gmem_AWPROT), - .m_axi_gmem_awqos (m_axi_gmem_AWQOS), - .m_axi_gmem_awregion (m_axi_gmem_AWREGION), - .m_axi_gmem_awid (m_axi_gmem_AWID), - .m_axi_gmem_awuser (m_axi_gmem_AWUSER), - .m_axi_gmem_awvalid (m_axi_gmem_AWVALID), - .m_axi_gmem_awready (m_axi_gmem_AWREADY), - .m_axi_gmem_wdata (m_axi_gmem_WDATA), - .m_axi_gmem_wstrb (m_axi_gmem_WSTRB), - .m_axi_gmem_wlast (m_axi_gmem_WLAST), -`ifdef AXI_MASTER_HAS_WID - .m_axi_gmem_wid (m_axi_gmem_WID), -`endif - .m_axi_gmem_wuser (m_axi_gmem_WUSER), - .m_axi_gmem_wvalid (m_axi_gmem_WVALID), - .m_axi_gmem_wready (m_axi_gmem_WREADY), - .m_axi_gmem_bresp (m_axi_gmem_BRESP), - .m_axi_gmem_bid (m_axi_gmem_BID), - .m_axi_gmem_buser (m_axi_gmem_BUSER), - .m_axi_gmem_bvalid (m_axi_gmem_BVALID), - .m_axi_gmem_bready (m_axi_gmem_BREADY), - .m_axi_gmem_araddr (m_axi_gmem_ARADDR), - .m_axi_gmem_arlen (m_axi_gmem_ARLEN), - .m_axi_gmem_arsize (m_axi_gmem_ARSIZE), - .m_axi_gmem_arburst (m_axi_gmem_ARBURST), - .m_axi_gmem_arlock (m_axi_gmem_ARLOCK[0]), - .m_axi_gmem_arcache (m_axi_gmem_local_ARCACHE), - .m_axi_gmem_arprot (m_axi_gmem_ARPROT), - .m_axi_gmem_arqos (m_axi_gmem_ARQOS), - .m_axi_gmem_arregion (m_axi_gmem_ARREGION), - .m_axi_gmem_arid (m_axi_gmem_ARID), - .m_axi_gmem_aruser (m_axi_gmem_ARUSER), - .m_axi_gmem_arvalid (m_axi_gmem_ARVALID), - .m_axi_gmem_arready (m_axi_gmem_ARREADY), - .m_axi_gmem_rdata (m_axi_gmem_RDATA), - .m_axi_gmem_rresp (m_axi_gmem_RRESP), - .m_axi_gmem_rlast (m_axi_gmem_RLAST), - .m_axi_gmem_rid (m_axi_gmem_RID), - .m_axi_gmem_ruser (m_axi_gmem_RUSER), - .m_axi_gmem_rvalid (m_axi_gmem_RVALID), - .m_axi_gmem_rready (m_axi_gmem_RREADY), - .paramaddr_0Ready (param_addr_valid), - .paramaddr_0Data (param_addr), - .paramaddr_0Stop (param_addr_stop), - .paramdata_0Ready (param_data_valid), - .paramdata_0Data (param_data), - .paramdata_0Stop (param_data_stop), - .clk (ap_clk), - .reset (kernel_reset) -); - -endmodule diff --git a/histogram-array/glide.lock b/histogram-array/glide.lock deleted file mode 100644 index 25d5b27..0000000 --- a/histogram-array/glide.lock +++ /dev/null @@ -1,9 +0,0 @@ -hash: 3eff1e675bfd0433d6dac08348dfc485662a334118561916fc1264bf1e2f80a9 -updated: 2018-08-27T21:49:06.420902+01:00 -imports: -- name: github.com/ReconfigureIO/sdaccel - version: 59bbcfa609e6dbc4af7ae0fbae373844f0a8ca3e - subpackages: - - smi - - xcl -testImports: [] diff --git a/histogram-array/glide.yaml b/histogram-array/glide.yaml index 9b4cbc3..af4dac5 100644 --- a/histogram-array/glide.yaml +++ b/histogram-array/glide.yaml @@ -1,8 +1,8 @@ package: . import: - package: github.com/ReconfigureIO/sdaccel - version: ~0.18.0 - subpakages: + version: ~0.20.1 + subpackages: - axi/arbitrate - axi/memory - axi/protocol diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/framework.go b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/framework.go index abd3c23..ba4a82c 100644 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/framework.go +++ b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/framework.go @@ -1,10 +1,8 @@ +// +// TODO: This no longer does anything useful, so should be deleted once it is +// no longer referenced by example code. +// package sdaccel -// #include verilog/sda_kernel_reset_handler.v -// #include verilog/sda_kernel_ctrl_reg_sel.v -// #include verilog/sda_kernel_ctrl_reg.v -// #include verilog/sda_kernel_ctrl_param.v -// #include verilog/sda_kernel_wrapper_gmem.v - func init() { } diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go index 6d00f95..3d76a63 100644 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go +++ b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go @@ -68,24 +68,31 @@ type Flit64 struct { // TODO: Update once there is a fix for the channel size compiler limitation. // func ForwardFrame64( + forwardReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + forwardDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - go func() { - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } - }() + doForward := <-forwardReq + for doForward { + go func() { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } + }() - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + forwardDone <- true + doForward = <-forwardReq } } @@ -98,22 +105,29 @@ func ForwardFrame64( // TODO: Update once there is a fix for the channel size compiler limitation. // func AssembleFrame64( + assembleReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + assembleDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } + doAssemble := <-assembleReq + for doAssemble { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + assembleDone <- true + doAssemble = <-assembleReq } } @@ -1387,18 +1401,24 @@ func WriteBurstUInt64( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt64( + thisWriteOk := writeSingleBurstUInt64( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1427,18 +1447,24 @@ func WriteBurstUInt32( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt32( + thisWriteOk := writeSingleBurstUInt32( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1467,18 +1493,24 @@ func WriteBurstUInt16( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt16( + thisWriteOk := writeSingleBurstUInt16( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1505,18 +1537,24 @@ func WriteBurstUInt8( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt8( + thisWriteOk := writeSingleBurstUInt8( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -2026,18 +2064,24 @@ func ReadBurstUInt64( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt64( + thisReadOk := readSingleBurstUInt64( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2066,18 +2110,24 @@ func ReadBurstUInt32( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt32( + thisReadOk := readSingleBurstUInt32( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2106,18 +2156,24 @@ func ReadBurstUInt16( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt16( + thisReadOk := readSingleBurstUInt16( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2144,17 +2200,23 @@ func ReadBurstUInt8( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt8( + thisReadOk := readSingleBurstUInt8( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v deleted file mode 100644 index 406a034..0000000 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v +++ /dev/null @@ -1,303 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implements the parameter RAM block which is provided on the AXI control bus -// for assigning kernel parameters prior to running kernel code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_param - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, - paramAddrValid, paramAddr, paramAddrStop, paramDataValid, paramData, - paramDataStop, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 12; - -// Specifies the base address of the parameter block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter ParamAddrBase = 64; - -// Specifies the upper address of the parameter block. -parameter ParamAddrTop = 4095; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; - -// Kernel interface parameter access signals. -input paramAddrValid; -input [31:0] paramAddr; -output paramAddrStop; -output paramDataValid; -output [31:0] paramData; -input paramDataStop; - -// System level signals. -input clk; -input srst; - -// Inferred RAM. -reg [31:0] ramArray [(ParamAddrTop-ParamAddrBase+1)/4-1:0]; - -// Pipelined register interface input inputs. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; -reg [RegAddrWidth-3:0] regAddr_q; - -// Pipelined register interface output inputs. -reg regAck_q; -reg regReadDone_q; -reg regReadValid_q; -reg [31:0] regRData_q; -reg [31:0] regReadData_q; -reg [31:0] regPipeData_q; - -// Pipelined parameter RAM access signals. -reg paramAddrValid_q; -reg [31:0] paramAddr_q; -reg paramDataValid_q; -reg [31:0] paramData_q; - -// Parameter RAM access backpressure signals. -wire pmAddrStop; -wire pmReadStop; -wire pmPipeStop; - -// Parameter RAM access pipeline. -reg [RegAddrWidth-3:0] pmAddr_q; -reg [1:0] pmAddrAlign_q; -reg pmAddrValid_q; -reg [31:0] pmReadData_q; -reg [1:0] pmReadAlign_q; -reg pmReadValid_q; -reg [31:0] pmPipeData_q; -reg [1:0] pmPipeAlign_q; -reg pmPipeValid_q; -reg [31:0] pmDataAligned; - -// Miscellaneous signals. -wire [RegAddrWidth-1:0] regParamAddrBase = ParamAddrBase [RegAddrWidth-1:0]; -wire [RegAddrWidth-1:0] regParamAddrTop = ParamAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipelined register input signals. Assumes that there are no back -// to back transactions, so we can use rising edge detection on the request line. -// verilator lint_off CMPCONST -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regWData_q <= regWData; - regWStrb_q <= regWStrb; - if ((regAddr < regParamAddrBase) || (regAddr > regParamAddrTop)) - begin - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regAddr_q <= regAddr[RegAddrWidth-1:2] - (ParamAddrBase/4); - end - end -end -// verilator lint_on CMPCONST - -// Implement pipelined register output signals. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regReadDone_q <= 1'b0; - regReadValid_q <= 1'b0; - regRData_q <= 32'b0; - end - else - begin - regAck_q <= regReadValid_q | regWriteReq_q; - regReadDone_q <= regReadReq_q; - regReadValid_q <= regReadDone_q; - regRData_q <= regReadValid_q ? regPipeData_q : 32'b0; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; - -// Implement pipelined parameter address inputs. -always @(posedge clk) -begin - if (srst) - begin - paramAddrValid_q <= 1'b0; - paramAddr_q <= 32'b0; - end - else if (paramAddrValid_q) - begin - paramAddrValid_q <= pmAddrStop; - end - else - begin - paramAddrValid_q <= paramAddrValid; - paramAddr_q <= paramAddr; - end -end - -assign paramAddrStop = paramAddrValid_q; - -// Implement the parameter data RAM access backpressure signals. -assign pmAddrStop = pmReadStop & pmAddrValid_q; -assign pmReadStop = pmPipeStop & pmReadValid_q; -assign pmPipeStop = paramDataValid_q & pmPipeValid_q; - -// Implement parameter access input pipeline. -always @(posedge clk) -begin - if (srst) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrValid_q <= 1'b0; - pmReadValid_q <= 1'b0; - pmPipeValid_q <= 1'b0; - end - else - begin - if (~pmAddrStop) - begin - pmAddrValid_q <= paramAddrValid_q; - if ((paramAddr_q < ParamAddrBase) || (paramAddr_q > ParamAddrTop)) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrAlign_q <= 2'b0; - end - else - begin - pmAddr_q <= paramAddr_q[RegAddrWidth-1:2] - (ParamAddrBase/4); - pmAddrAlign_q <= paramAddr_q[1:0]; - end - end - if (~pmReadStop) - begin - pmReadValid_q <= pmAddrValid_q; - pmReadAlign_q <= pmAddrAlign_q; - end - if (~pmPipeStop) - begin - pmPipeValid_q <= pmReadValid_q; - pmPipeAlign_q <= pmReadAlign_q; - end - end -end - -// Perform data alignment on read data. Uses the least significant bits of the -// parameter address to rotate the addressed byte into the LSB position. When -// combined with a suitable type cast in the kernel code, this allows byte and -// half word parameter values to be addressed on byte and half word boundaries. -always @(pmPipeAlign_q, pmPipeData_q) -begin - case (pmPipeAlign_q) - 2'b11 : pmDataAligned = {pmPipeData_q [23:0], pmPipeData_q [31:24]}; - 2'b10 : pmDataAligned = {pmPipeData_q [15:0], pmPipeData_q [31:16]}; - 2'b01 : pmDataAligned = {pmPipeData_q [7:0], pmPipeData_q [31:8]}; - default: pmDataAligned = pmPipeData_q; - endcase -end - -// Provide output pipeline register for read data. -always @(posedge clk) -begin - if (srst) - begin - paramDataValid_q <= 1'b0; - paramData_q <= 32'b0; - end - else if (paramDataValid_q) - begin - paramDataValid_q <= paramDataStop; - end - else - begin - paramDataValid_q <= pmPipeValid_q; - paramData_q <= pmDataAligned; - end -end - -assign paramDataValid = paramDataValid_q; -assign paramData = paramData_q; - -// Implement parameter RAM. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmReadStop) - begin - pmReadData_q <= ramArray [pmAddr_q]; - end - - // Register read pipeline is a single cycle delay. - regReadData_q <= ramArray [regAddr_q]; - - // Apply write enable strobes. - if (regWriteReq_q) - begin - if (regWStrb_q[0]) - ramArray [regAddr_q][7:0] <= regWData_q [7:0]; - if (regWStrb_q[1]) - ramArray [regAddr_q][15:8] <= regWData_q [15:8]; - if (regWStrb_q[2]) - ramArray [regAddr_q][23:16] <= regWData_q [23:16]; - if (regWStrb_q[3]) - ramArray [regAddr_q][31:24] <= regWData_q [31:24]; - end -end - -// Pipeline read data for improved timing. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmPipeStop) - begin - pmPipeData_q <= pmReadData_q; - end - - // Register read pipeline is a single cycle delay. - regPipeData_q <= regReadData_q; - -end - -endmodule diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v deleted file mode 100644 index e25deb8..0000000 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v +++ /dev/null @@ -1,357 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control registers. This is a set of -// four registers which are located at address offset 0 in the SDAccel kernel -// control register space. -// -// The control unit uses the standard register layout for the SDAccel control -// register. For the basic control register this is as follows: -// Bit 0: start signal (R/W) - Start processing data when this bit is set. -// The state of bit 0 will be cleared on start of processing. -// Bit 1: done signal (RO) - Asserted when the processing is done. -// The state of bit 1 will be cleared on reads. -// Bit 2: idle signal (RO) - Asserted when not processing any data. -// The state of bit 2 will be cleared on starting a new processing cycle. -// Bit 3: ready signal (RO) - Asserted when ready to start processing. -// The state of bit 3 will be cleared on starting a new processing cycle. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, goValid, - goHoldoff, doneValid, doneStop, kernelIntr, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 8; - -// Specifies the upper address of the reserved address block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter RegAddrTop = 63; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. The full register interface is implemented -// even though some of the register write bus is not used. -// verilator lint_off UNUSED -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; -// verilator lint_on UNUSED - -// Specify action go SELF control handshake signals. -output goValid; -input goHoldoff; - -// Specify action done SELF control handshake signals. -input doneValid; -output doneStop; - -// System level signals. -output kernelIntr; -input clk; -input srst; - -// Specify the register layout using byte offsets. Note that valid accesses -// must be aligned to 32-bit word boundaries. -parameter [31:0] - REG_ADDR_CTRL = 'h00, - REG_ADDR_GIE = 'h04, - REG_ADDR_IER = 'h08, - REG_ADDR_ISR = 'h0C; - -// Pipeline the register interface input signals. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg regWData0_q; -reg regWData1_q; -reg regWStrb0_q; -reg [RegAddrWidth-1:0] regAddr_q; - -// Specify the control register bit signals. -reg ctrlBitStart_d; -reg ctrlBitDone_d; -reg ctrlBitIdle_d; -reg ctrlBitReady_d; -reg goValid_d; - -reg ctrlBitStart_q; -reg ctrlBitDone_q; -reg ctrlBitIdle_q; -reg ctrlBitReady_q; -reg goValid_q; - -// Specify the interrupt enable register bit signals. -reg gieBitEnable_d; -reg ierBitDoneEn_d; -reg ierBitReadyEn_d; - -reg gieBitEnable_q; -reg ierBitDoneEn_q; -reg ierBitReadyEn_q; - -// Specify the interrupt status register bit signals. -reg isrBitDone_d; -reg isrBitReady_d; - -reg isrBitDone_q; -reg isrBitReady_q; - -// Specify the read pipeline signals. -reg regAck_d; -reg [31:0] regRData_d; - -reg regAck_q; -reg [31:0] regRData_q; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [RegAddrWidth-1:0] regAddrTop = RegAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipeined register read interface signals. Assumes that there are -// no back to back transactions, so we can use rising edge detection on the -// request line. -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData0_q <= 1'b0; - regWData1_q <= 1'b0; - regWStrb0_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regWData0_q <= regWData[0]; - regWData1_q <= regWData[1]; - regWStrb0_q <= regWStrb[0]; - regAddr_q <= regAddr; - end -end - -// Implement combinatorial logic for controlling register bit state. -always @(ctrlBitStart_q, ctrlBitDone_q, ctrlBitIdle_q, ctrlBitReady_q, - goValid_q, regReadReq_q, regWriteReq_q, regAddr_q, regWData0_q, regWStrb0_q, - goHoldoff, doneValid) -begin - - // Hold current state by default. - ctrlBitStart_d = ctrlBitStart_q; - ctrlBitDone_d = ctrlBitDone_q; - ctrlBitIdle_d = ctrlBitIdle_q; - ctrlBitReady_d = ctrlBitIdle_q & ~goHoldoff; - goValid_d = goValid_q; - - // Clear the 'done' bit on reads. - if (regReadReq_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitDone_d = 1'b0; - end - - // Assert the 'start' bit on register write requests. - if (regWriteReq_q & regWStrb0_q & regWData0_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitStart_d = 1'b1; - end - - // Attempt to initiate the SDAccel kernel operation. - if (ctrlBitStart_q & ctrlBitReady_q) - begin - if (goValid_q & ~goHoldoff) - begin - ctrlBitStart_d = 1'b0; - ctrlBitIdle_d = 1'b0; - ctrlBitReady_d = 1'b0; - goValid_d = 1'b0; - end - else - begin - goValid_d = 1'b1; - end - end - - // Detect completion of the SDAccel kernel operation. - if (~ctrlBitIdle_q & doneValid) - begin - ctrlBitDone_d = 1'b1; - ctrlBitIdle_d = 1'b1; - end - -end - -// Implement sequential logic for register bit values. -always @(posedge clk) -begin - if (srst) - begin - ctrlBitStart_q <= 1'b0; - ctrlBitDone_q <= 1'b0; - ctrlBitIdle_q <= 1'b1; - ctrlBitReady_q <= 1'b0; - goValid_q <= 1'b0; - end - else - begin - ctrlBitStart_q <= ctrlBitStart_d; - ctrlBitDone_q <= ctrlBitDone_d; - ctrlBitIdle_q <= ctrlBitIdle_d; - ctrlBitReady_q <= ctrlBitReady_d; - goValid_q <= goValid_d; - end -end - -assign goValid = goValid_q; -assign doneStop = ctrlBitIdle_q; - -// Implement combinatorial logic for interrupt enable registers. -always @(gieBitEnable_q, ierBitDoneEn_q, ierBitReadyEn_q, regWriteReq_q, - regAddr_q, regWData0_q, regWData1_q, regWStrb0_q) -begin - - // Hold current state by default. - gieBitEnable_d = gieBitEnable_q; - ierBitDoneEn_d = ierBitDoneEn_q; - ierBitReadyEn_d = ierBitReadyEn_q; - - // Set the global interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0])) - begin - gieBitEnable_d = regWData0_q; - end - - // Set the IP core interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0])) - begin - ierBitDoneEn_d = regWData0_q; - ierBitReadyEn_d = regWData1_q; - end -end - -// Implement combinatorial logic for interrupt status register. This is a bit -// unconventional in that it allows the software to set interrupt status bits -// by toggling them. However this matches the Xilinx implementation since it -// may be a requirement for their closed source OpenCL software. -always @(isrBitDone_q, isrBitReady_q, ierBitDoneEn_q, ierBitReadyEn_q, - regWriteReq_q, regAddr_q, regWData0_q, regWData1_q, regWStrb0_q, - ctrlBitDone_q, ctrlBitReady_q) -begin - - // Hold current state by default. - isrBitDone_d = isrBitDone_q; - isrBitReady_d = isrBitReady_q; - - // Toggle the ISR bits under software control. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0])) - begin - isrBitDone_d = isrBitDone_d ^ regWData0_q; - isrBitReady_d = isrBitReady_d ^ regWData1_q; - end - - // Assert the ISR bits on the 'done' and 'ready' signals. - isrBitDone_d = isrBitDone_d | ctrlBitDone_q; - isrBitReady_d = isrBitReady_d | ctrlBitReady_q; - - // Force ISR bits low if not enabled. - isrBitDone_d = isrBitDone_d & ierBitDoneEn_q; - isrBitReady_d = isrBitReady_d & ierBitReadyEn_q; - -end - -// Implement sequential logic for all interrupt registers. -always @(posedge clk) -begin - if (srst) - begin - gieBitEnable_q <= 1'b0; - ierBitDoneEn_q <= 1'b0; - ierBitReadyEn_q <= 1'b0; - isrBitDone_q <= 1'b0; - isrBitReady_q <= 1'b0; - end - else - begin - gieBitEnable_q <= gieBitEnable_d; - ierBitDoneEn_q <= ierBitDoneEn_d; - ierBitReadyEn_q <= ierBitReadyEn_d; - isrBitDone_q <= isrBitDone_d; - isrBitReady_q <= isrBitReady_d; - end -end - -// Implement combinatorial read register. -always @(regReadReq_q, regWriteReq_q, regAddr_q, ctrlBitIdle_q, ctrlBitDone_q, - ctrlBitStart_q, ctrlBitReady_q, gieBitEnable_q, ierBitDoneEn_q, - ierBitReadyEn_q, isrBitDone_q, isrBitReady_q, zeros, regAddrTop) -begin - - // Implement the read mux. - if (regReadReq_q) - begin - if (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0]) - regRData_d = {zeros[31:4], ctrlBitReady_q, - ctrlBitIdle_q, ctrlBitDone_q, ctrlBitStart_q}; - else if (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0]) - regRData_d = {zeros[31:1], gieBitEnable_q}; - else if (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], ierBitReadyEn_q, ierBitDoneEn_q}; - else if (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], isrBitReady_q, isrBitDone_q}; - else - regRData_d = zeros[31:0]; - end - else - begin - regRData_d = zeros[31:0]; - end - - // Acknowledge all accesses to the reserved register set. - if (regAddr_q <= regAddrTop) - regAck_d = regReadReq_q | regWriteReq_q; - else - regAck_d = 1'b0; - -end - -// Implement sequential read register. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regRData_q <= zeros[31:0]; - end - else - begin - regAck_q <= regAck_d; - regRData_q <= regRData_d; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; -assign kernelIntr = gieBitEnable_q & (isrBitDone_q | isrBitReady_q); - -endmodule diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v deleted file mode 100644 index 67e6ac0..0000000 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v +++ /dev/null @@ -1,651 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control register selection unit. It -// maps the specified number of AXI slave interface registers at the start of -// the AXI address space to simple wrapper control registers and then maps the -// remaining locations to the AXI interface handler in the generated code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg_sel - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiWValid, sAxiWReady, sAxiWData, - sAxiWStrb, sAxiBValid, sAxiBReady, sAxiBResp, sAxiARValid, sAxiARReady, - sAxiARAddr, sAxiRValid, sAxiRReady, sAxiRData, sAxiRResp, mAxiAWValid, - mAxiAWReady, mAxiAWAddr, mAxiWValid, mAxiWReady, mAxiWData, mAxiWStrb, - mAxiBValid, mAxiBReady, mAxiBResp, mAxiARValid, mAxiARReady, mAxiARAddr, - mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, regReq, regAck, regWriteEn, - regAddr, regWData, regWStrb, regRData, clk, srst); - -// Specifies the width of the AXI address bus. -parameter AddrWidth = 16; - -// Specifies the width of the local register set address bus. -parameter RegAddrWidth = 8; - -// Specify the upper address location which is mapped to the local register set. -parameter RegAddrTop = 255; - -// Slave side AXI write address channel signals. -input sAxiAWValid; -output sAxiAWReady; -input [AddrWidth-1:0] sAxiAWAddr; - -// Slave side AXI write data channel signals. -input sAxiWValid; -output sAxiWReady; -input [31:0] sAxiWData; -input [3:0] sAxiWStrb; - -// Slave side AXI write acknowledgement channel signals. -output sAxiBValid; -input sAxiBReady; -output [1:0] sAxiBResp; - -// Slave side AXI read address channel signals. -input sAxiARValid; -output sAxiARReady; -input [AddrWidth-1:0] sAxiARAddr; - -// Slave side AXI read data channel signals. -output sAxiRValid; -input sAxiRReady; -output [31:0] sAxiRData; -output [1:0] sAxiRResp; - -// Master side AXI write address channel signals. -output mAxiAWValid; -input mAxiAWReady; -output [AddrWidth-1:0] mAxiAWAddr; - -// Master side AXI write data channel signals. -output mAxiWValid; -input mAxiWReady; -output [31:0] mAxiWData; -output [3:0] mAxiWStrb; - -// Master side AXI write acknowledgement channel signals. -input mAxiBValid; -output mAxiBReady; -input [1:0] mAxiBResp; - -// Master side AXI read address channel signals. -output mAxiARValid; -input mAxiARReady; -output [AddrWidth-1:0] mAxiARAddr; - -// Slave side AXI read data channel signals. -input mAxiRValid; -output mAxiRReady; -input [31:0] mAxiRData; -input [1:0] mAxiRResp; - -// Master side simple register interface signals. -output regReq; -input regAck; -output regWriteEn; -output [RegAddrWidth-1:0] regAddr; -output [31:0] regWData; -output [3:0] regWStrb; -input [31:0] regRData; - -// System level signals. -input clk; -input srst; - -// AXI write address channel register signals. -wire sAxiAWPending; -reg sAxiAWClear; -wire [AddrWidth-1:0] sAxiAWAddrReg; -reg mAxiAWPush; -wire mAxiAWBlocked; -wire [AddrWidth-1:0] mAxiAWAddrReg; - -// AXI write data channel register signals. -wire sAxiWPending; -reg sAxiWClear; -wire [31:0] sAxiWDataReg; -wire [3:0] sAxiWStrbReg; -reg mAxiWPush; -wire mAxiWBlocked; -wire [31:0] mAxiWDataReg; -wire [3:0] mAxiWStrbReg; - -// AXI read address channel register signals. -wire sAxiARPending; -reg sAxiARClear; -wire [AddrWidth-1:0] sAxiARAddrReg; -reg mAxiARPush; -wire mAxiARBlocked; -wire [AddrWidth-1:0] mAxiARAddrReg; - -// AXI write response channel register signals. -wire mAxiBPending; -reg mAxiBClear; -wire [1:0] mAxiBRespReg; -reg sAxiBPush; -wire sAxiBBlocked; -reg [1:0] sAxiBRespReg; - -// AXI read response channel register signals. -wire mAxiRPending; -reg mAxiRClear; -wire [31:0] mAxiRDataReg; -wire [1:0] mAxiRRespReg; -reg sAxiRPush; -wire sAxiRBlocked; -reg [31:0] sAxiRDataReg; -reg [1:0] sAxiRRespReg; - -// Specify the state space used to select the AXI transaction mode. -parameter [3:0] - Idle = 0, - RegReadStart = 1, - RegReadActive = 2, - RegWriteStart = 3, - RegWriteActive = 4, - AxiReadStart = 5, - AxiReadActive = 6, - AxiWriteStart = 7, - AxiWriteData = 8, - AxiWriteActive = 9; - -// Specify AXI state machine registers. -reg [3:0] axiState_d; -reg regReq_d; -reg regWriteEn_d; -reg [RegAddrWidth-1:0] regAddr_d; -reg [31:0] regWData_d; -reg [3:0] regWStrb_d; - -reg [3:0] axiState_q; -reg regReq_q; -reg regWriteEn_q; -reg [RegAddrWidth-1:0] regAddr_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; - -// Miscellaneous signals. -wire [AddrWidth-1:0] regAddrTop = RegAddrTop [AddrWidth-1:0]; -integer i; - -// Instantiate input registers for slave side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiAWReg_u - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiAWPending, sAxiAWClear, - sAxiAWAddrReg, clk, srst); - -// Instantiate input registers for slave side AXI data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 4) sAxiWReg_u - (sAxiWValid, sAxiWReady, sAxiWData, sAxiWStrb, sAxiWPending, - sAxiWClear, sAxiWDataReg, sAxiWStrbReg, clk, srst); - -// Instantiate input registers for slave side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiARReg_u - (sAxiARValid, sAxiARReady, sAxiARAddr, sAxiARPending, sAxiARClear, - sAxiARAddrReg, clk, srst); - -// Instantiate input register for master side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(2) mAxiBReg_u - (mAxiBValid, mAxiBReady, mAxiBResp, mAxiBPending, mAxiBClear, mAxiBRespReg, - clk, srst); - -// Instantiate input register for master side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 2) mAxiRReg_u - (mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, mAxiRPending, - mAxiRClear, mAxiRDataReg, mAxiRRespReg, clk, srst); - -// Instantate output register for master side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiAWReg_u - (mAxiAWPush, mAxiAWBlocked, mAxiAWAddrReg, mAxiAWValid, mAxiAWReady, - mAxiAWAddr, clk, srst); - -// Instantiate output register for master side AXI write data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 4) mAxiWReg_u - (mAxiWPush, mAxiWBlocked, mAxiWDataReg, mAxiWStrbReg, mAxiWValid, - mAxiWReady, mAxiWData, mAxiWStrb, clk, srst); - -// Instantiate output register for master side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiARReg_u - (mAxiARPush, mAxiARBlocked, mAxiARAddrReg, mAxiARValid, mAxiARReady, - mAxiARAddr, clk, srst); - -// Instantiate output register for slave side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(2) sAxiBReg_u - (sAxiBPush, sAxiBBlocked, sAxiBRespReg, sAxiBValid, sAxiBReady, sAxiBResp, - clk, srst); - -// Instantiate output register for slave side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 2) sAxiRReg_u - (sAxiRPush, sAxiRBlocked, sAxiRDataReg, sAxiRRespReg, sAxiRValid, - sAxiRReady, sAxiRData, sAxiRResp, clk, srst); - -// Pass through AXI signals where possible. -assign mAxiAWAddrReg = sAxiAWAddrReg; -assign mAxiWDataReg = sAxiWDataReg; -assign mAxiWStrbReg = sAxiWStrbReg; -assign mAxiARAddrReg = sAxiARAddrReg; - -// Implement combinatorial logic for selecting AXI transaction mode. -always @(axiState_q, regReq_q, regWriteEn_q, regAddr_q, regWData_q, regWStrb_q, - sAxiAWPending, sAxiAWAddrReg, sAxiWPending, sAxiWDataReg, sAxiWStrbReg, - sAxiBBlocked, sAxiARPending, sAxiARAddrReg, sAxiRBlocked, mAxiRPending, - mAxiRDataReg, mAxiRRespReg, mAxiAWBlocked, mAxiWBlocked, mAxiBPending, - mAxiARBlocked, mAxiBRespReg, regAck, regRData, regAddrTop) -begin - - // Preserve current state by default. - axiState_d = axiState_q; - regReq_d = regReq_q; - regWriteEn_d = regWriteEn_q; - regAddr_d = regAddr_q; - regWData_d = regWData_q; - regWStrb_d = regWStrb_q; - - // Set default read assignment to register inputs with AXI 'OKAY' response. - sAxiRPush = 1'b0; - sAxiRDataReg = regRData; - sAxiRRespReg = 2'b0; - - // Set default write status assigment to AXI 'OKAY' response. - sAxiBPush = 1'b0; - sAxiBRespReg = 2'b0; - - // Disable AXI register clear strobes by default. - sAxiAWClear = 1'b0; - sAxiWClear = 1'b0; - sAxiARClear = 1'b0; - mAxiBClear = 1'b0; - mAxiRClear = 1'b0; - - // Disable AXI master push strobes by default. - mAxiAWPush = 1'b0; - mAxiWPush = 1'b0; - mAxiARPush = 1'b0; - - // Implement state machine. - case (axiState_q) - - // In the idle state, wait until the AXI write or read address inputs are - // ready. Writes are prioritised over reads. - // verilator lint_off CMPCONST - Idle : - begin - if (sAxiAWPending) - begin - if (sAxiAWAddrReg <= regAddrTop) - axiState_d = RegWriteStart; - else - axiState_d = AxiWriteStart; - end - else if (sAxiARPending) - begin - if (sAxiARAddrReg <= regAddrTop) - axiState_d = RegReadStart; - else - axiState_d = AxiReadStart; - end - end - // verilator lint_on CMPCONST - - // Initiate read transactions on the local register interface. - RegReadStart : - begin - if (~sAxiRBlocked) - begin - axiState_d = RegReadActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b0; - regAddr_d = sAxiARAddrReg [RegAddrWidth-1:0]; - end - end - - // Process active read requests. - RegReadActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiRPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Initiate write transactions to the local register interface. - RegWriteStart : - begin - if (sAxiWPending & ~sAxiBBlocked) - begin - axiState_d = RegWriteActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b1; - regAddr_d = sAxiAWAddrReg [RegAddrWidth-1:0]; - regWData_d = sAxiWDataReg; - regWStrb_d = sAxiWStrbReg; - end - end - - // Process active write requests. - RegWriteActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiBPush = 1'b1; - sAxiAWClear = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Initiate read transaction on the AXI master side. - AxiReadStart : - begin - if (~mAxiARBlocked) - begin - axiState_d = AxiReadActive; - mAxiARPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Complete read transaction from the AXI master side. - AxiReadActive : - begin - sAxiRDataReg = mAxiRDataReg; - sAxiRRespReg = mAxiRRespReg; - if (mAxiRPending & ~sAxiRBlocked) - begin - axiState_d = Idle; - sAxiRPush = 1'b1; - mAxiRClear = 1'b1; - end - end - - // Initiate write transaction on the AXI master side. - AxiWriteStart : - begin - if (~mAxiAWBlocked) - begin - axiState_d = AxiWriteData; - mAxiAWPush = 1'b1; - sAxiAWClear = 1'b1; - end - end - - // Forward write data to the AXI master side. - AxiWriteData : - begin - if (sAxiWPending & ~mAxiWBlocked) - begin - axiState_d = AxiWriteActive; - mAxiWPush = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Complete write transaction from the AXI master side. - AxiWriteActive : - begin - sAxiBRespReg = mAxiBRespReg; - if (mAxiBPending & ~sAxiBBlocked) - begin - axiState_d = Idle; - sAxiBPush = 1'b1; - mAxiBClear = 1'b1; - end - end - - // Map unknown states to Idle. - default : - begin - axiState_d = Idle; - end - endcase -end - -// Implement sequential logic for AXI transaction state machine. -always @(posedge clk) -begin - if (srst) - begin - axiState_q <= Idle; - regReq_q <= 1'b0; - regWriteEn_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q [i] <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - end - else - begin - axiState_q <= axiState_d; - regReq_q <= regReq_d; - regWriteEn_q <= regWriteEn_d; - regAddr_q <= regAddr_d; - regWData_q <= regWData_d; - regWStrb_q <= regWStrb_d; - end -end - -assign regReq = regReq_q; -assign regWriteEn = regWriteEn_q; -assign regAddr = regAddr_q; -assign regWData = regWData_q; -assign regWStrb = regWStrb_q; - -endmodule - -// -// Provides common implementation of single AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x1 - (axiValid, axiReady, axiDataIn, dataPending, dataClear, dataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth-1:0] axiDataIn; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth-1:0] dataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataClear_q; -reg axiReady_q; -reg [DataWidth-1:0] axiDataIn_q; - -integer i; - -// Implements a single AXI input register. -always @(posedge clk) -begin - if (srst | dataClear) - begin - dataClear_q <= 1'b1; - axiReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - axiDataIn_q [i] <= 1'b0; - end - else if (dataClear_q) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b1; - end - else if (axiReady_q & axiValid) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b0; - axiDataIn_q <= axiDataIn; - end -end - -assign axiReady = axiReady_q; -assign dataPending = ~(dataClear_q | axiReady_q); -assign dataOut = axiDataIn_q; - -endmodule - -// -// Provides common implementation of dual AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x2 - (axiValid, axiReady, axiDataIn1, axiDataIn2, dataPending, dataClear, - dataOut1, dataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth1-1:0] axiDataIn1; -input [DataWidth2-1:0] axiDataIn2; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth1-1:0] dataOut1; -output [DataWidth2-1:0] dataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] dataOut; - -// Instantiate the single input register module. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (axiValid, axiReady, {axiDataIn2, axiDataIn1}, dataPending, dataClear, - dataOut, clk, srst); - -assign dataOut1 = dataOut [DataWidth1-1:0]; -assign dataOut2 = dataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - -// -// Provides common implementation of single AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x1 - (dataPush, dataBlocked, dataIn, axiValid, axiReady, axiDataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth-1:0] dataIn; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth-1:0] axiDataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataReady_q; -reg [DataWidth-1:0] dataReg_q; - -integer i; - -// Implements a single AXI output register. -always @(posedge clk) -begin - if (srst) - begin - dataReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - dataReg_q [i] <= 1'b0; - end - else if (dataReady_q & axiReady) - begin - dataReady_q <= 1'b0; - end - else if (dataPush) - begin - dataReady_q <= 1'b1; - dataReg_q <= dataIn; - end -end - -assign dataBlocked = dataReady_q; -assign axiValid = dataReady_q; -assign axiDataOut = dataReg_q; - -endmodule - -// -// Provides common implementation of dual AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x2 - (dataPush, dataBlocked, dataIn1, dataIn2, axiValid, axiReady, axiDataOut1, - axiDataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth1-1:0] dataIn1; -input [DataWidth2-1:0] dataIn2; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth1-1:0] axiDataOut1; -output [DataWidth2-1:0] axiDataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] axiDataOut; - -// Instantiate the single output register module. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (dataPush, dataBlocked, {dataIn2, dataIn1}, axiValid, axiReady, - axiDataOut, clk, srst); - -assign axiDataOut1 = axiDataOut [DataWidth1-1:0]; -assign axiDataOut2 = axiDataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v deleted file mode 100644 index 925d6d3..0000000 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v +++ /dev/null @@ -1,259 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel reset handler. It provides support for -// managing kernel resets under control of the external 'go' and 'done' control -// signals. -// - -`timescale 1ns/1ps - -module sda_kernel_reset_handler - (regGoValid, regGoHoldoff, regDoneValid, regDoneStop, kernelGoValid, - kernelGoHoldoff, kernelDoneValid, kernelDoneStop, sysRstReq, wrapperReset, - kernelReset, clk); - -// Specifies the reset counter size. The kernel reset line will be asserted for -// the time it takes the counter to wrap. -parameter ResetCountSize = 5; - -// Specifies the length of the reset pipeline, which allows the synthesis tools -// to build a reset tree if required by using register duplication. -parameter ResetPipeLength = 8; - -// Derives the reset counter limit. -parameter ResetCountLimit = (1 << ResetCountSize) - 1; - -// Specify the reset controller state space. -parameter [2:0] - ResetIdle = 0, - ResetTimeout = 1, - KernelStarting = 2, - KernelRunning = 3, - KernelExited = 4; - -// Upstream register interface signals. -input regGoValid; -output regGoHoldoff; -output regDoneValid; -input regDoneStop; - -// Kernel control go output signals. -output kernelGoValid; -input kernelGoHoldoff; -input kernelDoneValid; -output kernelDoneStop; - -// Specifies the system reset request signal and generated resets. -input sysRstReq; -output wrapperReset; -output kernelReset; - -// Specifies the clock input. There is no standard synchronous reset. -input clk; - -// Reset control state machine signals. -reg [2:0] resetState_d; -reg [ResetCountSize-1:0] resetCount_d; -reg kernelReset_d; -reg regGoHoldoff_d; -reg regDoneValid_d; -reg kernelGoValid_d; -reg kernelDoneStop_d; - -reg [2:0] resetState_q; -reg [ResetCountSize-1:0] resetCount_q; -reg kernelReset_q; -reg regGoHoldoff_q; -reg regDoneValid_q; -reg kernelGoValid_q; -reg kernelDoneStop_q; - -// Implements a register with an explicit initialisation value, which will have -// the effect of forcing a reset cycle immediately after loading the FPGA -// netlist. Only works with devices that support bitstream initalisation. -reg resetHandlerEnabled_q = 1'b0; -reg wrapperReset_q; - -// Specifies the reset pipeline signals. -reg [ResetPipeLength-1:0] wrapperResetPipe_q; -reg [ResetPipeLength-1:0] kernelResetPipe_q; - -// Miscellaneous signals. -integer i; - -// Initiate automatic reset on FPGA bitstream load. -always @(posedge clk) -begin - if (sysRstReq | ~resetHandlerEnabled_q) - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b1; - end - else - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b0; - end -end - -// Implement combinatorial logic for reset control state machine. -always @(resetState_q, resetCount_q, kernelReset_q, regGoHoldoff_q, regDoneValid_q, - kernelGoValid_q, kernelDoneStop_q, regGoValid, regDoneStop, kernelGoHoldoff, - kernelDoneValid) -begin - - // Hold current state by default. - resetState_d = resetState_q; - resetCount_d = resetCount_q; - kernelReset_d = kernelReset_q; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - - // Implement state machine. - case (resetState_q) - - // Hold the reset state for the required timeout. - ResetTimeout : - begin - if (resetCount_q == ResetCountLimit [ResetCountSize-1:0]) - begin - resetState_d = ResetIdle; - end - resetCount_d = resetCount_q + 1; - end - - // Wait for the kernel to accept the go signal. - KernelStarting : - begin - if (kernelGoValid_q & ~kernelGoHoldoff) - begin - resetState_d = KernelRunning; - end - else - begin - kernelGoValid_d = 1'b1; - end - end - - // In the kernel runnning state, wait for the 'done' response. - KernelRunning : - begin - if (kernelDoneValid & ~kernelDoneStop_q) - begin - resetState_d = KernelExited; - end - else - begin - kernelDoneStop_d = 1'b0; - end - end - - // In the kernel exited state, notify the control registers and place the - // kernel in reset until the next go request is received. - KernelExited : - begin - if (regDoneValid_q & ~regDoneStop) - begin - resetState_d = ResetTimeout; - kernelReset_d = 1'b1; - end - else - begin - regDoneValid_d = 1'b1; - end - end - - // In the reset idle state, wait for a go request from the register block - // before releasing the kernel reset. - ResetIdle : - begin - if (regGoValid & ~regGoHoldoff_q) - begin - resetState_d = KernelStarting; - kernelReset_d = 1'b0; - end - else - begin - regGoHoldoff_d = 1'b0; - end - end - - // Treat the unreachable default state as a hard reset. This prevents the - // Xilinx tools from generating dangling nets if the state encoding is - // automatically converted to one-hot. - default: - begin - resetState_d = ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_d [i] = 1'b0; - kernelReset_d = 1'b1; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - end - endcase - -end - -// Implement sequential logic for reset control state machine. -always @(posedge clk) -begin - if (wrapperReset_q) - begin - resetState_q <= ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_q [i] <= 1'b0; - kernelReset_q <= 1'b1; - regGoHoldoff_q <= 1'b1; - regDoneValid_q <= 1'b0; - kernelGoValid_q <= 1'b0; - kernelDoneStop_q <= 1'b1; - end - else - begin - resetState_q <= resetState_d; - resetCount_q <= resetCount_d; - kernelReset_q <= kernelReset_d; - regGoHoldoff_q <= regGoHoldoff_d; - regDoneValid_q <= regDoneValid_d; - kernelGoValid_q <= kernelGoValid_d; - kernelDoneStop_q <= kernelDoneStop_d; - end -end - -assign regGoHoldoff = regGoHoldoff_q; -assign regDoneValid = regDoneValid_q; -assign kernelGoValid = kernelGoValid_q; -assign kernelDoneStop = kernelDoneStop_q; - -// Implement reset output pipelines. -always @(posedge clk) -begin - if (wrapperReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - wrapperResetPipe_q [i] <= 1'b1; - else - wrapperResetPipe_q <= { 1'b0, wrapperResetPipe_q [ResetPipeLength-1:1] }; -end - -always @(posedge clk) -begin - if (kernelReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - kernelResetPipe_q [i] <= 1'b1; - else - kernelResetPipe_q <= { 1'b0, kernelResetPipe_q [ResetPipeLength-1:1] }; -end - -assign wrapperReset = wrapperResetPipe_q [0]; -assign kernelReset = kernelResetPipe_q [0]; - -endmodule diff --git a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v b/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v deleted file mode 100644 index 95054a0..0000000 --- a/histogram-array/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v +++ /dev/null @@ -1,390 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Provides the common wrapper code around an existing 'action' block so that it -// can be used in the context of an SDAccel 'kernel' block. This variant -// supports the complete set of control registers at AXI slave offset zero which -// are used to map the SDAccel run/status programming interface to the action -// block run/done SELF handshake lines. This wrapper implements a single AXI -// master interface which can access the shared global memory area on the FPGA -// card. -// - -`timescale 1ns/1ps - -// Can be redefined on the synthesis command line. -`ifndef AXI_SLAVE_ADDR_WIDTH -`define AXI_SLAVE_ADDR_WIDTH 16 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ADDR_WIDTH -`define AXI_MASTER_ADDR_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_DATA_WIDTH -`define AXI_MASTER_DATA_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ID_WIDTH -`define AXI_MASTER_ID_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_USER_WIDTH -`define AXI_MASTER_USER_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_CACHE_MASK -`define AXI_MASTER_CACHE_MASK 4'b0011 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_PARAM_MEM_ADDR_WIDTH -`define AXI_PARAM_MEM_ADDR_WIDTH 12 -`endif - -// Module name to be substituted in post-synthesis netlist. -module sda_kernel_wrapper_gmem - (s_axi_control_AWADDR, s_axi_control_AWVALID, s_axi_control_AWREADY, - s_axi_control_WDATA, s_axi_control_WSTRB, s_axi_control_WVALID, - s_axi_control_WREADY, s_axi_control_BRESP, s_axi_control_BVALID, - s_axi_control_BREADY, s_axi_control_ARADDR, s_axi_control_ARVALID, - s_axi_control_ARREADY, s_axi_control_RDATA, s_axi_control_RRESP, - s_axi_control_RVALID, s_axi_control_RREADY, m_axi_gmem_AWADDR, - m_axi_gmem_AWLEN, m_axi_gmem_AWSIZE, m_axi_gmem_AWBURST, m_axi_gmem_AWLOCK, - m_axi_gmem_AWREGION, m_axi_gmem_AWCACHE, m_axi_gmem_AWPROT, m_axi_gmem_AWQOS, - m_axi_gmem_AWID, m_axi_gmem_AWUSER, m_axi_gmem_AWVALID, m_axi_gmem_AWREADY, - m_axi_gmem_WDATA, m_axi_gmem_WSTRB, m_axi_gmem_WLAST, m_axi_gmem_WID, - m_axi_gmem_WUSER, m_axi_gmem_WVALID, m_axi_gmem_WREADY, m_axi_gmem_BRESP, - m_axi_gmem_BID, m_axi_gmem_BUSER, m_axi_gmem_BVALID, m_axi_gmem_BREADY, - m_axi_gmem_ARADDR, m_axi_gmem_ARLEN, m_axi_gmem_ARSIZE, m_axi_gmem_ARBURST, - m_axi_gmem_ARLOCK, m_axi_gmem_ARREGION, m_axi_gmem_ARCACHE, m_axi_gmem_ARPROT, - m_axi_gmem_ARQOS, m_axi_gmem_ARID, m_axi_gmem_ARUSER, m_axi_gmem_ARVALID, - m_axi_gmem_ARREADY, m_axi_gmem_RDATA, m_axi_gmem_RRESP, m_axi_gmem_RLAST, - m_axi_gmem_RID, m_axi_gmem_RUSER, m_axi_gmem_RVALID, m_axi_gmem_RREADY, - ap_clk, ap_rst_n, interrupt); - -// Specifies the AXI slave write address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_AWADDR; -input s_axi_control_AWVALID; -output s_axi_control_AWREADY; - -// Specifies the AXI slave write data signals. -input [31:0] s_axi_control_WDATA; -input [3:0] s_axi_control_WSTRB; -input s_axi_control_WVALID; -output s_axi_control_WREADY; - -// Specifies the AXI slave write response signals. -output [1:0] s_axi_control_BRESP; -output s_axi_control_BVALID; -input s_axi_control_BREADY; - -// Specifies the AXI slave read address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_ARADDR; -input s_axi_control_ARVALID; -output s_axi_control_ARREADY; - -// Specifies the AXI slave read data signals. -output [31:0] s_axi_control_RDATA; -output [1:0] s_axi_control_RRESP; -output s_axi_control_RVALID; -input s_axi_control_RREADY; - -// Specifies the AXI master write address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_AWADDR; -output [7:0] m_axi_gmem_AWLEN; -output [2:0] m_axi_gmem_AWSIZE; -output [1:0] m_axi_gmem_AWBURST; -output [1:0] m_axi_gmem_AWLOCK; -output [3:0] m_axi_gmem_AWCACHE; -output [2:0] m_axi_gmem_AWPROT; -output [3:0] m_axi_gmem_AWQOS; -output [3:0] m_axi_gmem_AWREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_AWID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_AWUSER; -output m_axi_gmem_AWVALID; -input m_axi_gmem_AWREADY; - -// Specifies the AXI master write data signals. -output [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_WDATA; -output [`AXI_MASTER_DATA_WIDTH/8-1:0] m_axi_gmem_WSTRB; -output m_axi_gmem_WLAST; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_WID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_WUSER; -output m_axi_gmem_WVALID; -input m_axi_gmem_WREADY; - -// Specifies the AXI master write response signals. -input [1:0] m_axi_gmem_BRESP; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_BID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_BUSER; -input m_axi_gmem_BVALID; -output m_axi_gmem_BREADY; - -// Specifies the AXI master read address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_ARADDR; -output [7:0] m_axi_gmem_ARLEN; -output [2:0] m_axi_gmem_ARSIZE; -output [1:0] m_axi_gmem_ARBURST; -output [1:0] m_axi_gmem_ARLOCK; -output [3:0] m_axi_gmem_ARCACHE; -output [2:0] m_axi_gmem_ARPROT; -output [3:0] m_axi_gmem_ARQOS; -output [3:0] m_axi_gmem_ARREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_ARID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_ARUSER; -output m_axi_gmem_ARVALID; -input m_axi_gmem_ARREADY; - -// Specifies the AXI master read data signals. -input [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_RDATA; -input [1:0] m_axi_gmem_RRESP; -input m_axi_gmem_RLAST; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_RID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_RUSER; -input m_axi_gmem_RVALID; -output m_axi_gmem_RREADY; - -// Specifies the system level I/O signals. -input ap_clk; -input ap_rst_n; - -// verilator lint_off SYMRSVDWORD -output interrupt; -// verilator lint_on SYMRSVDWORD - -// Reset management signals. -wire reg_go_valid; -wire reg_go_holdoff; -wire reg_done_valid; -wire reg_done_stop; -wire kernel_reset; -wire wrapper_reset; - -// AXI control interface master write address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_AWADDR; -wire [3:0] m_axi_control_AWCACHE; -wire [2:0] m_axi_control_AWPROT; -wire m_axi_control_AWVALID; -wire m_axi_control_AWREADY; - -// AXI control interface master write data signals. -wire [31:0] m_axi_control_WDATA; -wire [3:0] m_axi_control_WSTRB; -wire m_axi_control_WVALID; -wire m_axi_control_WREADY; - -// AXI control interface master write response signals. -wire [1:0] m_axi_control_BRESP; -wire m_axi_control_BVALID; -wire m_axi_control_BREADY; - -// AXI control interface master read address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_ARADDR; -wire [3:0] m_axi_control_ARCACHE; -wire [2:0] m_axi_control_ARPROT; -wire m_axi_control_ARVALID; -wire m_axi_control_ARREADY; - -// AXI control interface master read data signals. -wire [31:0] m_axi_control_RDATA; -wire [1:0] m_axi_control_RRESP; -wire m_axi_control_RVALID; -wire m_axi_control_RREADY; - -// AXI master interface intermediate signals. -wire [3:0] m_axi_gmem_local_ARCACHE; -wire [3:0] m_axi_gmem_local_AWCACHE; - -// Wrapper control register interface signals. -wire reg_req; -wire reg_ack; -wire reg_ack_0; -wire reg_ack_1; -wire reg_write_en; -wire [`AXI_PARAM_MEM_ADDR_WIDTH-1:0] reg_addr; -wire [31:0] reg_wdata; -wire [3:0] reg_wstrb; -wire [31:0] reg_rdata; -wire [31:0] reg_rdata_0; -wire [31:0] reg_rdata_1; - -// Kernel interface parameter access signals. -wire param_addr_valid; -wire [31:0] param_addr; -wire param_addr_stop; -wire param_data_valid; -wire [31:0] param_data; -wire param_data_stop; - -// Action control signals. -wire go_0Ready; -wire go_0Stop; -wire done_0Ready; -wire done_0Stop; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [31:0] m_axi_control_ext_AWADDR; -wire [31:0] m_axi_control_ext_ARADDR; - -// Tie off unused control interface signals. -assign m_axi_control_AWCACHE = 4'b0000; -assign m_axi_control_AWPROT = 3'b010; -assign m_axi_control_ARCACHE = 4'b0000; -assign m_axi_control_ARPROT = 3'b010; - -// Tie off upper bit of the lock signals for AXI3 backward compatibility. -assign m_axi_gmem_AWLOCK[1] = 1'b0; -assign m_axi_gmem_ARLOCK[1] = 1'b0; - -// Tie off unused WID signal -`ifndef AXI_MASTER_HAS_WID -assign m_axi_gmem_WID = `AXI_MASTER_ID_WIDTH'd0; -`endif - -// Apply cache mask to restrict memory access modes if required. The default -// is to restrict accesses to device mode only, as required by the AWS shell. -assign m_axi_gmem_ARCACHE = m_axi_gmem_local_ARCACHE & `AXI_MASTER_CACHE_MASK; -assign m_axi_gmem_AWCACHE = m_axi_gmem_local_AWCACHE & `AXI_MASTER_CACHE_MASK; - -// Instantiate the reset controller. -sda_kernel_reset_handler resetHandler_u - (reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, go_0Ready, - go_0Stop, done_0Ready, done_0Stop, ~ap_rst_n, wrapper_reset, kernel_reset, - ap_clk); - -// Instantiate the AXI slave register selection component. -sda_kernel_ctrl_reg_sel #(`AXI_SLAVE_ADDR_WIDTH, `AXI_PARAM_MEM_ADDR_WIDTH, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlRegSel_u - (s_axi_control_AWVALID, s_axi_control_AWREADY, s_axi_control_AWADDR, - s_axi_control_WVALID, s_axi_control_WREADY, s_axi_control_WDATA, - s_axi_control_WSTRB, s_axi_control_BVALID, s_axi_control_BREADY, - s_axi_control_BRESP, s_axi_control_ARVALID, s_axi_control_ARREADY, - s_axi_control_ARADDR, s_axi_control_RVALID, s_axi_control_RREADY, - s_axi_control_RDATA, s_axi_control_RRESP, m_axi_control_AWVALID, - m_axi_control_AWREADY, m_axi_control_AWADDR, m_axi_control_WVALID, - m_axi_control_WREADY, m_axi_control_WDATA, m_axi_control_WSTRB, - m_axi_control_BVALID, m_axi_control_BREADY, m_axi_control_BRESP, - m_axi_control_ARVALID, m_axi_control_ARREADY, m_axi_control_ARADDR, - m_axi_control_RVALID, m_axi_control_RREADY, m_axi_control_RDATA, - m_axi_control_RRESP, reg_req, reg_ack, reg_write_en, reg_addr, reg_wdata, - reg_wstrb, reg_rdata, ap_clk, wrapper_reset); - -// Instantiate the kernel control registers at slave address offset 0. -sda_kernel_ctrl_reg #(`AXI_PARAM_MEM_ADDR_WIDTH, 63) kernelCtrlReg_u - (reg_req, reg_ack_0, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_0, - reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, interrupt, ap_clk, - wrapper_reset); - -// Instantiate the kernel parameter memory. -sda_kernel_ctrl_param #(`AXI_PARAM_MEM_ADDR_WIDTH, 64, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlParam_u - (reg_req, reg_ack_1, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_1, - param_addr_valid, param_addr, param_addr_stop, param_data_valid, param_data, - param_data_stop, ap_clk, wrapper_reset); - -assign reg_ack = reg_ack_0 | reg_ack_1; -assign reg_rdata = reg_rdata_0 | reg_rdata_1 | zeros; - -// Extend the slave address bus widths to the standard 32 bit value for the -// action logic core. -assign m_axi_control_ext_AWADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_AWADDR}; -assign m_axi_control_ext_ARADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_ARADDR}; - -// Instantiate the simple generated action logic core. -teak__action__top__gmem kernelActionTop_u ( - .go_0Ready (go_0Ready), - .go_0Stop (go_0Stop), - .done_0Ready (done_0Ready), - .done_0Stop (done_0Stop), - .s_axi_araddr (m_axi_control_ext_ARADDR), - .s_axi_arcache (m_axi_control_ARCACHE), - .s_axi_arprot (m_axi_control_ARPROT), - .s_axi_arvalid (m_axi_control_ARVALID), - .s_axi_arready (m_axi_control_ARREADY), - .s_axi_rdata (m_axi_control_RDATA), - .s_axi_rresp (m_axi_control_RRESP), - .s_axi_rvalid (m_axi_control_RVALID), - .s_axi_rready (m_axi_control_RREADY), - .s_axi_awaddr (m_axi_control_ext_AWADDR), - .s_axi_awcache (m_axi_control_AWCACHE), - .s_axi_awprot (m_axi_control_AWPROT), - .s_axi_awvalid (m_axi_control_AWVALID), - .s_axi_awready (m_axi_control_AWREADY), - .s_axi_wdata (m_axi_control_WDATA), - .s_axi_wstrb (m_axi_control_WSTRB), - .s_axi_wvalid (m_axi_control_WVALID), - .s_axi_wready (m_axi_control_WREADY), - .s_axi_bresp (m_axi_control_BRESP), - .s_axi_bvalid (m_axi_control_BVALID), - .s_axi_bready (m_axi_control_BREADY), - .m_axi_gmem_awaddr (m_axi_gmem_AWADDR), - .m_axi_gmem_awlen (m_axi_gmem_AWLEN), - .m_axi_gmem_awsize (m_axi_gmem_AWSIZE), - .m_axi_gmem_awburst (m_axi_gmem_AWBURST), - .m_axi_gmem_awlock (m_axi_gmem_AWLOCK[0]), - .m_axi_gmem_awcache (m_axi_gmem_local_AWCACHE), - .m_axi_gmem_awprot (m_axi_gmem_AWPROT), - .m_axi_gmem_awqos (m_axi_gmem_AWQOS), - .m_axi_gmem_awregion (m_axi_gmem_AWREGION), - .m_axi_gmem_awid (m_axi_gmem_AWID), - .m_axi_gmem_awuser (m_axi_gmem_AWUSER), - .m_axi_gmem_awvalid (m_axi_gmem_AWVALID), - .m_axi_gmem_awready (m_axi_gmem_AWREADY), - .m_axi_gmem_wdata (m_axi_gmem_WDATA), - .m_axi_gmem_wstrb (m_axi_gmem_WSTRB), - .m_axi_gmem_wlast (m_axi_gmem_WLAST), -`ifdef AXI_MASTER_HAS_WID - .m_axi_gmem_wid (m_axi_gmem_WID), -`endif - .m_axi_gmem_wuser (m_axi_gmem_WUSER), - .m_axi_gmem_wvalid (m_axi_gmem_WVALID), - .m_axi_gmem_wready (m_axi_gmem_WREADY), - .m_axi_gmem_bresp (m_axi_gmem_BRESP), - .m_axi_gmem_bid (m_axi_gmem_BID), - .m_axi_gmem_buser (m_axi_gmem_BUSER), - .m_axi_gmem_bvalid (m_axi_gmem_BVALID), - .m_axi_gmem_bready (m_axi_gmem_BREADY), - .m_axi_gmem_araddr (m_axi_gmem_ARADDR), - .m_axi_gmem_arlen (m_axi_gmem_ARLEN), - .m_axi_gmem_arsize (m_axi_gmem_ARSIZE), - .m_axi_gmem_arburst (m_axi_gmem_ARBURST), - .m_axi_gmem_arlock (m_axi_gmem_ARLOCK[0]), - .m_axi_gmem_arcache (m_axi_gmem_local_ARCACHE), - .m_axi_gmem_arprot (m_axi_gmem_ARPROT), - .m_axi_gmem_arqos (m_axi_gmem_ARQOS), - .m_axi_gmem_arregion (m_axi_gmem_ARREGION), - .m_axi_gmem_arid (m_axi_gmem_ARID), - .m_axi_gmem_aruser (m_axi_gmem_ARUSER), - .m_axi_gmem_arvalid (m_axi_gmem_ARVALID), - .m_axi_gmem_arready (m_axi_gmem_ARREADY), - .m_axi_gmem_rdata (m_axi_gmem_RDATA), - .m_axi_gmem_rresp (m_axi_gmem_RRESP), - .m_axi_gmem_rlast (m_axi_gmem_RLAST), - .m_axi_gmem_rid (m_axi_gmem_RID), - .m_axi_gmem_ruser (m_axi_gmem_RUSER), - .m_axi_gmem_rvalid (m_axi_gmem_RVALID), - .m_axi_gmem_rready (m_axi_gmem_RREADY), - .paramaddr_0Ready (param_addr_valid), - .paramaddr_0Data (param_addr), - .paramaddr_0Stop (param_addr_stop), - .paramdata_0Ready (param_data_valid), - .paramdata_0Data (param_data), - .paramdata_0Stop (param_data_stop), - .clk (ap_clk), - .reset (kernel_reset) -); - -endmodule diff --git a/histogram-parallel/glide.lock b/histogram-parallel/glide.lock deleted file mode 100644 index cf75e36..0000000 --- a/histogram-parallel/glide.lock +++ /dev/null @@ -1,12 +0,0 @@ -hash: 8dae7d4b554c5dc4203a6aea5fcb855a3786d9b06d9a68dd567dee82c31071e3 -updated: 2018-08-27T21:50:34.393745+01:00 -imports: -- name: github.com/ReconfigureIO/sdaccel - version: 59bbcfa609e6dbc4af7ae0fbae373844f0a8ca3e - subpackages: - - axi/arbitrate - - axi/memory - - axi/protocol - - smi - - xcl -testImports: [] diff --git a/histogram-parallel/glide.yaml b/histogram-parallel/glide.yaml index a83597a..af4dac5 100644 --- a/histogram-parallel/glide.yaml +++ b/histogram-parallel/glide.yaml @@ -1,7 +1,7 @@ package: . import: - package: github.com/ReconfigureIO/sdaccel - version: ~0.18.0 + version: ~0.20.1 subpackages: - axi/arbitrate - axi/memory diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/framework.go b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/framework.go index abd3c23..ba4a82c 100644 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/framework.go +++ b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/framework.go @@ -1,10 +1,8 @@ +// +// TODO: This no longer does anything useful, so should be deleted once it is +// no longer referenced by example code. +// package sdaccel -// #include verilog/sda_kernel_reset_handler.v -// #include verilog/sda_kernel_ctrl_reg_sel.v -// #include verilog/sda_kernel_ctrl_reg.v -// #include verilog/sda_kernel_ctrl_param.v -// #include verilog/sda_kernel_wrapper_gmem.v - func init() { } diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go index 6d00f95..3d76a63 100644 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go +++ b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go @@ -68,24 +68,31 @@ type Flit64 struct { // TODO: Update once there is a fix for the channel size compiler limitation. // func ForwardFrame64( + forwardReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + forwardDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - go func() { - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } - }() + doForward := <-forwardReq + for doForward { + go func() { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } + }() - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + forwardDone <- true + doForward = <-forwardReq } } @@ -98,22 +105,29 @@ func ForwardFrame64( // TODO: Update once there is a fix for the channel size compiler limitation. // func AssembleFrame64( + assembleReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + assembleDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } + doAssemble := <-assembleReq + for doAssemble { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + assembleDone <- true + doAssemble = <-assembleReq } } @@ -1387,18 +1401,24 @@ func WriteBurstUInt64( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt64( + thisWriteOk := writeSingleBurstUInt64( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1427,18 +1447,24 @@ func WriteBurstUInt32( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt32( + thisWriteOk := writeSingleBurstUInt32( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1467,18 +1493,24 @@ func WriteBurstUInt16( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt16( + thisWriteOk := writeSingleBurstUInt16( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1505,18 +1537,24 @@ func WriteBurstUInt8( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt8( + thisWriteOk := writeSingleBurstUInt8( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -2026,18 +2064,24 @@ func ReadBurstUInt64( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt64( + thisReadOk := readSingleBurstUInt64( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2066,18 +2110,24 @@ func ReadBurstUInt32( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt32( + thisReadOk := readSingleBurstUInt32( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2106,18 +2156,24 @@ func ReadBurstUInt16( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt16( + thisReadOk := readSingleBurstUInt16( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2144,17 +2200,23 @@ func ReadBurstUInt8( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt8( + thisReadOk := readSingleBurstUInt8( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v deleted file mode 100644 index 406a034..0000000 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v +++ /dev/null @@ -1,303 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implements the parameter RAM block which is provided on the AXI control bus -// for assigning kernel parameters prior to running kernel code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_param - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, - paramAddrValid, paramAddr, paramAddrStop, paramDataValid, paramData, - paramDataStop, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 12; - -// Specifies the base address of the parameter block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter ParamAddrBase = 64; - -// Specifies the upper address of the parameter block. -parameter ParamAddrTop = 4095; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; - -// Kernel interface parameter access signals. -input paramAddrValid; -input [31:0] paramAddr; -output paramAddrStop; -output paramDataValid; -output [31:0] paramData; -input paramDataStop; - -// System level signals. -input clk; -input srst; - -// Inferred RAM. -reg [31:0] ramArray [(ParamAddrTop-ParamAddrBase+1)/4-1:0]; - -// Pipelined register interface input inputs. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; -reg [RegAddrWidth-3:0] regAddr_q; - -// Pipelined register interface output inputs. -reg regAck_q; -reg regReadDone_q; -reg regReadValid_q; -reg [31:0] regRData_q; -reg [31:0] regReadData_q; -reg [31:0] regPipeData_q; - -// Pipelined parameter RAM access signals. -reg paramAddrValid_q; -reg [31:0] paramAddr_q; -reg paramDataValid_q; -reg [31:0] paramData_q; - -// Parameter RAM access backpressure signals. -wire pmAddrStop; -wire pmReadStop; -wire pmPipeStop; - -// Parameter RAM access pipeline. -reg [RegAddrWidth-3:0] pmAddr_q; -reg [1:0] pmAddrAlign_q; -reg pmAddrValid_q; -reg [31:0] pmReadData_q; -reg [1:0] pmReadAlign_q; -reg pmReadValid_q; -reg [31:0] pmPipeData_q; -reg [1:0] pmPipeAlign_q; -reg pmPipeValid_q; -reg [31:0] pmDataAligned; - -// Miscellaneous signals. -wire [RegAddrWidth-1:0] regParamAddrBase = ParamAddrBase [RegAddrWidth-1:0]; -wire [RegAddrWidth-1:0] regParamAddrTop = ParamAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipelined register input signals. Assumes that there are no back -// to back transactions, so we can use rising edge detection on the request line. -// verilator lint_off CMPCONST -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regWData_q <= regWData; - regWStrb_q <= regWStrb; - if ((regAddr < regParamAddrBase) || (regAddr > regParamAddrTop)) - begin - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regAddr_q <= regAddr[RegAddrWidth-1:2] - (ParamAddrBase/4); - end - end -end -// verilator lint_on CMPCONST - -// Implement pipelined register output signals. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regReadDone_q <= 1'b0; - regReadValid_q <= 1'b0; - regRData_q <= 32'b0; - end - else - begin - regAck_q <= regReadValid_q | regWriteReq_q; - regReadDone_q <= regReadReq_q; - regReadValid_q <= regReadDone_q; - regRData_q <= regReadValid_q ? regPipeData_q : 32'b0; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; - -// Implement pipelined parameter address inputs. -always @(posedge clk) -begin - if (srst) - begin - paramAddrValid_q <= 1'b0; - paramAddr_q <= 32'b0; - end - else if (paramAddrValid_q) - begin - paramAddrValid_q <= pmAddrStop; - end - else - begin - paramAddrValid_q <= paramAddrValid; - paramAddr_q <= paramAddr; - end -end - -assign paramAddrStop = paramAddrValid_q; - -// Implement the parameter data RAM access backpressure signals. -assign pmAddrStop = pmReadStop & pmAddrValid_q; -assign pmReadStop = pmPipeStop & pmReadValid_q; -assign pmPipeStop = paramDataValid_q & pmPipeValid_q; - -// Implement parameter access input pipeline. -always @(posedge clk) -begin - if (srst) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrValid_q <= 1'b0; - pmReadValid_q <= 1'b0; - pmPipeValid_q <= 1'b0; - end - else - begin - if (~pmAddrStop) - begin - pmAddrValid_q <= paramAddrValid_q; - if ((paramAddr_q < ParamAddrBase) || (paramAddr_q > ParamAddrTop)) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrAlign_q <= 2'b0; - end - else - begin - pmAddr_q <= paramAddr_q[RegAddrWidth-1:2] - (ParamAddrBase/4); - pmAddrAlign_q <= paramAddr_q[1:0]; - end - end - if (~pmReadStop) - begin - pmReadValid_q <= pmAddrValid_q; - pmReadAlign_q <= pmAddrAlign_q; - end - if (~pmPipeStop) - begin - pmPipeValid_q <= pmReadValid_q; - pmPipeAlign_q <= pmReadAlign_q; - end - end -end - -// Perform data alignment on read data. Uses the least significant bits of the -// parameter address to rotate the addressed byte into the LSB position. When -// combined with a suitable type cast in the kernel code, this allows byte and -// half word parameter values to be addressed on byte and half word boundaries. -always @(pmPipeAlign_q, pmPipeData_q) -begin - case (pmPipeAlign_q) - 2'b11 : pmDataAligned = {pmPipeData_q [23:0], pmPipeData_q [31:24]}; - 2'b10 : pmDataAligned = {pmPipeData_q [15:0], pmPipeData_q [31:16]}; - 2'b01 : pmDataAligned = {pmPipeData_q [7:0], pmPipeData_q [31:8]}; - default: pmDataAligned = pmPipeData_q; - endcase -end - -// Provide output pipeline register for read data. -always @(posedge clk) -begin - if (srst) - begin - paramDataValid_q <= 1'b0; - paramData_q <= 32'b0; - end - else if (paramDataValid_q) - begin - paramDataValid_q <= paramDataStop; - end - else - begin - paramDataValid_q <= pmPipeValid_q; - paramData_q <= pmDataAligned; - end -end - -assign paramDataValid = paramDataValid_q; -assign paramData = paramData_q; - -// Implement parameter RAM. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmReadStop) - begin - pmReadData_q <= ramArray [pmAddr_q]; - end - - // Register read pipeline is a single cycle delay. - regReadData_q <= ramArray [regAddr_q]; - - // Apply write enable strobes. - if (regWriteReq_q) - begin - if (regWStrb_q[0]) - ramArray [regAddr_q][7:0] <= regWData_q [7:0]; - if (regWStrb_q[1]) - ramArray [regAddr_q][15:8] <= regWData_q [15:8]; - if (regWStrb_q[2]) - ramArray [regAddr_q][23:16] <= regWData_q [23:16]; - if (regWStrb_q[3]) - ramArray [regAddr_q][31:24] <= regWData_q [31:24]; - end -end - -// Pipeline read data for improved timing. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmPipeStop) - begin - pmPipeData_q <= pmReadData_q; - end - - // Register read pipeline is a single cycle delay. - regPipeData_q <= regReadData_q; - -end - -endmodule diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v deleted file mode 100644 index e25deb8..0000000 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v +++ /dev/null @@ -1,357 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control registers. This is a set of -// four registers which are located at address offset 0 in the SDAccel kernel -// control register space. -// -// The control unit uses the standard register layout for the SDAccel control -// register. For the basic control register this is as follows: -// Bit 0: start signal (R/W) - Start processing data when this bit is set. -// The state of bit 0 will be cleared on start of processing. -// Bit 1: done signal (RO) - Asserted when the processing is done. -// The state of bit 1 will be cleared on reads. -// Bit 2: idle signal (RO) - Asserted when not processing any data. -// The state of bit 2 will be cleared on starting a new processing cycle. -// Bit 3: ready signal (RO) - Asserted when ready to start processing. -// The state of bit 3 will be cleared on starting a new processing cycle. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, goValid, - goHoldoff, doneValid, doneStop, kernelIntr, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 8; - -// Specifies the upper address of the reserved address block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter RegAddrTop = 63; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. The full register interface is implemented -// even though some of the register write bus is not used. -// verilator lint_off UNUSED -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; -// verilator lint_on UNUSED - -// Specify action go SELF control handshake signals. -output goValid; -input goHoldoff; - -// Specify action done SELF control handshake signals. -input doneValid; -output doneStop; - -// System level signals. -output kernelIntr; -input clk; -input srst; - -// Specify the register layout using byte offsets. Note that valid accesses -// must be aligned to 32-bit word boundaries. -parameter [31:0] - REG_ADDR_CTRL = 'h00, - REG_ADDR_GIE = 'h04, - REG_ADDR_IER = 'h08, - REG_ADDR_ISR = 'h0C; - -// Pipeline the register interface input signals. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg regWData0_q; -reg regWData1_q; -reg regWStrb0_q; -reg [RegAddrWidth-1:0] regAddr_q; - -// Specify the control register bit signals. -reg ctrlBitStart_d; -reg ctrlBitDone_d; -reg ctrlBitIdle_d; -reg ctrlBitReady_d; -reg goValid_d; - -reg ctrlBitStart_q; -reg ctrlBitDone_q; -reg ctrlBitIdle_q; -reg ctrlBitReady_q; -reg goValid_q; - -// Specify the interrupt enable register bit signals. -reg gieBitEnable_d; -reg ierBitDoneEn_d; -reg ierBitReadyEn_d; - -reg gieBitEnable_q; -reg ierBitDoneEn_q; -reg ierBitReadyEn_q; - -// Specify the interrupt status register bit signals. -reg isrBitDone_d; -reg isrBitReady_d; - -reg isrBitDone_q; -reg isrBitReady_q; - -// Specify the read pipeline signals. -reg regAck_d; -reg [31:0] regRData_d; - -reg regAck_q; -reg [31:0] regRData_q; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [RegAddrWidth-1:0] regAddrTop = RegAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipeined register read interface signals. Assumes that there are -// no back to back transactions, so we can use rising edge detection on the -// request line. -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData0_q <= 1'b0; - regWData1_q <= 1'b0; - regWStrb0_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regWData0_q <= regWData[0]; - regWData1_q <= regWData[1]; - regWStrb0_q <= regWStrb[0]; - regAddr_q <= regAddr; - end -end - -// Implement combinatorial logic for controlling register bit state. -always @(ctrlBitStart_q, ctrlBitDone_q, ctrlBitIdle_q, ctrlBitReady_q, - goValid_q, regReadReq_q, regWriteReq_q, regAddr_q, regWData0_q, regWStrb0_q, - goHoldoff, doneValid) -begin - - // Hold current state by default. - ctrlBitStart_d = ctrlBitStart_q; - ctrlBitDone_d = ctrlBitDone_q; - ctrlBitIdle_d = ctrlBitIdle_q; - ctrlBitReady_d = ctrlBitIdle_q & ~goHoldoff; - goValid_d = goValid_q; - - // Clear the 'done' bit on reads. - if (regReadReq_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitDone_d = 1'b0; - end - - // Assert the 'start' bit on register write requests. - if (regWriteReq_q & regWStrb0_q & regWData0_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitStart_d = 1'b1; - end - - // Attempt to initiate the SDAccel kernel operation. - if (ctrlBitStart_q & ctrlBitReady_q) - begin - if (goValid_q & ~goHoldoff) - begin - ctrlBitStart_d = 1'b0; - ctrlBitIdle_d = 1'b0; - ctrlBitReady_d = 1'b0; - goValid_d = 1'b0; - end - else - begin - goValid_d = 1'b1; - end - end - - // Detect completion of the SDAccel kernel operation. - if (~ctrlBitIdle_q & doneValid) - begin - ctrlBitDone_d = 1'b1; - ctrlBitIdle_d = 1'b1; - end - -end - -// Implement sequential logic for register bit values. -always @(posedge clk) -begin - if (srst) - begin - ctrlBitStart_q <= 1'b0; - ctrlBitDone_q <= 1'b0; - ctrlBitIdle_q <= 1'b1; - ctrlBitReady_q <= 1'b0; - goValid_q <= 1'b0; - end - else - begin - ctrlBitStart_q <= ctrlBitStart_d; - ctrlBitDone_q <= ctrlBitDone_d; - ctrlBitIdle_q <= ctrlBitIdle_d; - ctrlBitReady_q <= ctrlBitReady_d; - goValid_q <= goValid_d; - end -end - -assign goValid = goValid_q; -assign doneStop = ctrlBitIdle_q; - -// Implement combinatorial logic for interrupt enable registers. -always @(gieBitEnable_q, ierBitDoneEn_q, ierBitReadyEn_q, regWriteReq_q, - regAddr_q, regWData0_q, regWData1_q, regWStrb0_q) -begin - - // Hold current state by default. - gieBitEnable_d = gieBitEnable_q; - ierBitDoneEn_d = ierBitDoneEn_q; - ierBitReadyEn_d = ierBitReadyEn_q; - - // Set the global interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0])) - begin - gieBitEnable_d = regWData0_q; - end - - // Set the IP core interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0])) - begin - ierBitDoneEn_d = regWData0_q; - ierBitReadyEn_d = regWData1_q; - end -end - -// Implement combinatorial logic for interrupt status register. This is a bit -// unconventional in that it allows the software to set interrupt status bits -// by toggling them. However this matches the Xilinx implementation since it -// may be a requirement for their closed source OpenCL software. -always @(isrBitDone_q, isrBitReady_q, ierBitDoneEn_q, ierBitReadyEn_q, - regWriteReq_q, regAddr_q, regWData0_q, regWData1_q, regWStrb0_q, - ctrlBitDone_q, ctrlBitReady_q) -begin - - // Hold current state by default. - isrBitDone_d = isrBitDone_q; - isrBitReady_d = isrBitReady_q; - - // Toggle the ISR bits under software control. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0])) - begin - isrBitDone_d = isrBitDone_d ^ regWData0_q; - isrBitReady_d = isrBitReady_d ^ regWData1_q; - end - - // Assert the ISR bits on the 'done' and 'ready' signals. - isrBitDone_d = isrBitDone_d | ctrlBitDone_q; - isrBitReady_d = isrBitReady_d | ctrlBitReady_q; - - // Force ISR bits low if not enabled. - isrBitDone_d = isrBitDone_d & ierBitDoneEn_q; - isrBitReady_d = isrBitReady_d & ierBitReadyEn_q; - -end - -// Implement sequential logic for all interrupt registers. -always @(posedge clk) -begin - if (srst) - begin - gieBitEnable_q <= 1'b0; - ierBitDoneEn_q <= 1'b0; - ierBitReadyEn_q <= 1'b0; - isrBitDone_q <= 1'b0; - isrBitReady_q <= 1'b0; - end - else - begin - gieBitEnable_q <= gieBitEnable_d; - ierBitDoneEn_q <= ierBitDoneEn_d; - ierBitReadyEn_q <= ierBitReadyEn_d; - isrBitDone_q <= isrBitDone_d; - isrBitReady_q <= isrBitReady_d; - end -end - -// Implement combinatorial read register. -always @(regReadReq_q, regWriteReq_q, regAddr_q, ctrlBitIdle_q, ctrlBitDone_q, - ctrlBitStart_q, ctrlBitReady_q, gieBitEnable_q, ierBitDoneEn_q, - ierBitReadyEn_q, isrBitDone_q, isrBitReady_q, zeros, regAddrTop) -begin - - // Implement the read mux. - if (regReadReq_q) - begin - if (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0]) - regRData_d = {zeros[31:4], ctrlBitReady_q, - ctrlBitIdle_q, ctrlBitDone_q, ctrlBitStart_q}; - else if (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0]) - regRData_d = {zeros[31:1], gieBitEnable_q}; - else if (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], ierBitReadyEn_q, ierBitDoneEn_q}; - else if (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], isrBitReady_q, isrBitDone_q}; - else - regRData_d = zeros[31:0]; - end - else - begin - regRData_d = zeros[31:0]; - end - - // Acknowledge all accesses to the reserved register set. - if (regAddr_q <= regAddrTop) - regAck_d = regReadReq_q | regWriteReq_q; - else - regAck_d = 1'b0; - -end - -// Implement sequential read register. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regRData_q <= zeros[31:0]; - end - else - begin - regAck_q <= regAck_d; - regRData_q <= regRData_d; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; -assign kernelIntr = gieBitEnable_q & (isrBitDone_q | isrBitReady_q); - -endmodule diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v deleted file mode 100644 index 67e6ac0..0000000 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v +++ /dev/null @@ -1,651 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control register selection unit. It -// maps the specified number of AXI slave interface registers at the start of -// the AXI address space to simple wrapper control registers and then maps the -// remaining locations to the AXI interface handler in the generated code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg_sel - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiWValid, sAxiWReady, sAxiWData, - sAxiWStrb, sAxiBValid, sAxiBReady, sAxiBResp, sAxiARValid, sAxiARReady, - sAxiARAddr, sAxiRValid, sAxiRReady, sAxiRData, sAxiRResp, mAxiAWValid, - mAxiAWReady, mAxiAWAddr, mAxiWValid, mAxiWReady, mAxiWData, mAxiWStrb, - mAxiBValid, mAxiBReady, mAxiBResp, mAxiARValid, mAxiARReady, mAxiARAddr, - mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, regReq, regAck, regWriteEn, - regAddr, regWData, regWStrb, regRData, clk, srst); - -// Specifies the width of the AXI address bus. -parameter AddrWidth = 16; - -// Specifies the width of the local register set address bus. -parameter RegAddrWidth = 8; - -// Specify the upper address location which is mapped to the local register set. -parameter RegAddrTop = 255; - -// Slave side AXI write address channel signals. -input sAxiAWValid; -output sAxiAWReady; -input [AddrWidth-1:0] sAxiAWAddr; - -// Slave side AXI write data channel signals. -input sAxiWValid; -output sAxiWReady; -input [31:0] sAxiWData; -input [3:0] sAxiWStrb; - -// Slave side AXI write acknowledgement channel signals. -output sAxiBValid; -input sAxiBReady; -output [1:0] sAxiBResp; - -// Slave side AXI read address channel signals. -input sAxiARValid; -output sAxiARReady; -input [AddrWidth-1:0] sAxiARAddr; - -// Slave side AXI read data channel signals. -output sAxiRValid; -input sAxiRReady; -output [31:0] sAxiRData; -output [1:0] sAxiRResp; - -// Master side AXI write address channel signals. -output mAxiAWValid; -input mAxiAWReady; -output [AddrWidth-1:0] mAxiAWAddr; - -// Master side AXI write data channel signals. -output mAxiWValid; -input mAxiWReady; -output [31:0] mAxiWData; -output [3:0] mAxiWStrb; - -// Master side AXI write acknowledgement channel signals. -input mAxiBValid; -output mAxiBReady; -input [1:0] mAxiBResp; - -// Master side AXI read address channel signals. -output mAxiARValid; -input mAxiARReady; -output [AddrWidth-1:0] mAxiARAddr; - -// Slave side AXI read data channel signals. -input mAxiRValid; -output mAxiRReady; -input [31:0] mAxiRData; -input [1:0] mAxiRResp; - -// Master side simple register interface signals. -output regReq; -input regAck; -output regWriteEn; -output [RegAddrWidth-1:0] regAddr; -output [31:0] regWData; -output [3:0] regWStrb; -input [31:0] regRData; - -// System level signals. -input clk; -input srst; - -// AXI write address channel register signals. -wire sAxiAWPending; -reg sAxiAWClear; -wire [AddrWidth-1:0] sAxiAWAddrReg; -reg mAxiAWPush; -wire mAxiAWBlocked; -wire [AddrWidth-1:0] mAxiAWAddrReg; - -// AXI write data channel register signals. -wire sAxiWPending; -reg sAxiWClear; -wire [31:0] sAxiWDataReg; -wire [3:0] sAxiWStrbReg; -reg mAxiWPush; -wire mAxiWBlocked; -wire [31:0] mAxiWDataReg; -wire [3:0] mAxiWStrbReg; - -// AXI read address channel register signals. -wire sAxiARPending; -reg sAxiARClear; -wire [AddrWidth-1:0] sAxiARAddrReg; -reg mAxiARPush; -wire mAxiARBlocked; -wire [AddrWidth-1:0] mAxiARAddrReg; - -// AXI write response channel register signals. -wire mAxiBPending; -reg mAxiBClear; -wire [1:0] mAxiBRespReg; -reg sAxiBPush; -wire sAxiBBlocked; -reg [1:0] sAxiBRespReg; - -// AXI read response channel register signals. -wire mAxiRPending; -reg mAxiRClear; -wire [31:0] mAxiRDataReg; -wire [1:0] mAxiRRespReg; -reg sAxiRPush; -wire sAxiRBlocked; -reg [31:0] sAxiRDataReg; -reg [1:0] sAxiRRespReg; - -// Specify the state space used to select the AXI transaction mode. -parameter [3:0] - Idle = 0, - RegReadStart = 1, - RegReadActive = 2, - RegWriteStart = 3, - RegWriteActive = 4, - AxiReadStart = 5, - AxiReadActive = 6, - AxiWriteStart = 7, - AxiWriteData = 8, - AxiWriteActive = 9; - -// Specify AXI state machine registers. -reg [3:0] axiState_d; -reg regReq_d; -reg regWriteEn_d; -reg [RegAddrWidth-1:0] regAddr_d; -reg [31:0] regWData_d; -reg [3:0] regWStrb_d; - -reg [3:0] axiState_q; -reg regReq_q; -reg regWriteEn_q; -reg [RegAddrWidth-1:0] regAddr_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; - -// Miscellaneous signals. -wire [AddrWidth-1:0] regAddrTop = RegAddrTop [AddrWidth-1:0]; -integer i; - -// Instantiate input registers for slave side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiAWReg_u - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiAWPending, sAxiAWClear, - sAxiAWAddrReg, clk, srst); - -// Instantiate input registers for slave side AXI data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 4) sAxiWReg_u - (sAxiWValid, sAxiWReady, sAxiWData, sAxiWStrb, sAxiWPending, - sAxiWClear, sAxiWDataReg, sAxiWStrbReg, clk, srst); - -// Instantiate input registers for slave side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiARReg_u - (sAxiARValid, sAxiARReady, sAxiARAddr, sAxiARPending, sAxiARClear, - sAxiARAddrReg, clk, srst); - -// Instantiate input register for master side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(2) mAxiBReg_u - (mAxiBValid, mAxiBReady, mAxiBResp, mAxiBPending, mAxiBClear, mAxiBRespReg, - clk, srst); - -// Instantiate input register for master side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 2) mAxiRReg_u - (mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, mAxiRPending, - mAxiRClear, mAxiRDataReg, mAxiRRespReg, clk, srst); - -// Instantate output register for master side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiAWReg_u - (mAxiAWPush, mAxiAWBlocked, mAxiAWAddrReg, mAxiAWValid, mAxiAWReady, - mAxiAWAddr, clk, srst); - -// Instantiate output register for master side AXI write data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 4) mAxiWReg_u - (mAxiWPush, mAxiWBlocked, mAxiWDataReg, mAxiWStrbReg, mAxiWValid, - mAxiWReady, mAxiWData, mAxiWStrb, clk, srst); - -// Instantiate output register for master side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiARReg_u - (mAxiARPush, mAxiARBlocked, mAxiARAddrReg, mAxiARValid, mAxiARReady, - mAxiARAddr, clk, srst); - -// Instantiate output register for slave side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(2) sAxiBReg_u - (sAxiBPush, sAxiBBlocked, sAxiBRespReg, sAxiBValid, sAxiBReady, sAxiBResp, - clk, srst); - -// Instantiate output register for slave side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 2) sAxiRReg_u - (sAxiRPush, sAxiRBlocked, sAxiRDataReg, sAxiRRespReg, sAxiRValid, - sAxiRReady, sAxiRData, sAxiRResp, clk, srst); - -// Pass through AXI signals where possible. -assign mAxiAWAddrReg = sAxiAWAddrReg; -assign mAxiWDataReg = sAxiWDataReg; -assign mAxiWStrbReg = sAxiWStrbReg; -assign mAxiARAddrReg = sAxiARAddrReg; - -// Implement combinatorial logic for selecting AXI transaction mode. -always @(axiState_q, regReq_q, regWriteEn_q, regAddr_q, regWData_q, regWStrb_q, - sAxiAWPending, sAxiAWAddrReg, sAxiWPending, sAxiWDataReg, sAxiWStrbReg, - sAxiBBlocked, sAxiARPending, sAxiARAddrReg, sAxiRBlocked, mAxiRPending, - mAxiRDataReg, mAxiRRespReg, mAxiAWBlocked, mAxiWBlocked, mAxiBPending, - mAxiARBlocked, mAxiBRespReg, regAck, regRData, regAddrTop) -begin - - // Preserve current state by default. - axiState_d = axiState_q; - regReq_d = regReq_q; - regWriteEn_d = regWriteEn_q; - regAddr_d = regAddr_q; - regWData_d = regWData_q; - regWStrb_d = regWStrb_q; - - // Set default read assignment to register inputs with AXI 'OKAY' response. - sAxiRPush = 1'b0; - sAxiRDataReg = regRData; - sAxiRRespReg = 2'b0; - - // Set default write status assigment to AXI 'OKAY' response. - sAxiBPush = 1'b0; - sAxiBRespReg = 2'b0; - - // Disable AXI register clear strobes by default. - sAxiAWClear = 1'b0; - sAxiWClear = 1'b0; - sAxiARClear = 1'b0; - mAxiBClear = 1'b0; - mAxiRClear = 1'b0; - - // Disable AXI master push strobes by default. - mAxiAWPush = 1'b0; - mAxiWPush = 1'b0; - mAxiARPush = 1'b0; - - // Implement state machine. - case (axiState_q) - - // In the idle state, wait until the AXI write or read address inputs are - // ready. Writes are prioritised over reads. - // verilator lint_off CMPCONST - Idle : - begin - if (sAxiAWPending) - begin - if (sAxiAWAddrReg <= regAddrTop) - axiState_d = RegWriteStart; - else - axiState_d = AxiWriteStart; - end - else if (sAxiARPending) - begin - if (sAxiARAddrReg <= regAddrTop) - axiState_d = RegReadStart; - else - axiState_d = AxiReadStart; - end - end - // verilator lint_on CMPCONST - - // Initiate read transactions on the local register interface. - RegReadStart : - begin - if (~sAxiRBlocked) - begin - axiState_d = RegReadActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b0; - regAddr_d = sAxiARAddrReg [RegAddrWidth-1:0]; - end - end - - // Process active read requests. - RegReadActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiRPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Initiate write transactions to the local register interface. - RegWriteStart : - begin - if (sAxiWPending & ~sAxiBBlocked) - begin - axiState_d = RegWriteActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b1; - regAddr_d = sAxiAWAddrReg [RegAddrWidth-1:0]; - regWData_d = sAxiWDataReg; - regWStrb_d = sAxiWStrbReg; - end - end - - // Process active write requests. - RegWriteActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiBPush = 1'b1; - sAxiAWClear = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Initiate read transaction on the AXI master side. - AxiReadStart : - begin - if (~mAxiARBlocked) - begin - axiState_d = AxiReadActive; - mAxiARPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Complete read transaction from the AXI master side. - AxiReadActive : - begin - sAxiRDataReg = mAxiRDataReg; - sAxiRRespReg = mAxiRRespReg; - if (mAxiRPending & ~sAxiRBlocked) - begin - axiState_d = Idle; - sAxiRPush = 1'b1; - mAxiRClear = 1'b1; - end - end - - // Initiate write transaction on the AXI master side. - AxiWriteStart : - begin - if (~mAxiAWBlocked) - begin - axiState_d = AxiWriteData; - mAxiAWPush = 1'b1; - sAxiAWClear = 1'b1; - end - end - - // Forward write data to the AXI master side. - AxiWriteData : - begin - if (sAxiWPending & ~mAxiWBlocked) - begin - axiState_d = AxiWriteActive; - mAxiWPush = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Complete write transaction from the AXI master side. - AxiWriteActive : - begin - sAxiBRespReg = mAxiBRespReg; - if (mAxiBPending & ~sAxiBBlocked) - begin - axiState_d = Idle; - sAxiBPush = 1'b1; - mAxiBClear = 1'b1; - end - end - - // Map unknown states to Idle. - default : - begin - axiState_d = Idle; - end - endcase -end - -// Implement sequential logic for AXI transaction state machine. -always @(posedge clk) -begin - if (srst) - begin - axiState_q <= Idle; - regReq_q <= 1'b0; - regWriteEn_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q [i] <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - end - else - begin - axiState_q <= axiState_d; - regReq_q <= regReq_d; - regWriteEn_q <= regWriteEn_d; - regAddr_q <= regAddr_d; - regWData_q <= regWData_d; - regWStrb_q <= regWStrb_d; - end -end - -assign regReq = regReq_q; -assign regWriteEn = regWriteEn_q; -assign regAddr = regAddr_q; -assign regWData = regWData_q; -assign regWStrb = regWStrb_q; - -endmodule - -// -// Provides common implementation of single AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x1 - (axiValid, axiReady, axiDataIn, dataPending, dataClear, dataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth-1:0] axiDataIn; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth-1:0] dataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataClear_q; -reg axiReady_q; -reg [DataWidth-1:0] axiDataIn_q; - -integer i; - -// Implements a single AXI input register. -always @(posedge clk) -begin - if (srst | dataClear) - begin - dataClear_q <= 1'b1; - axiReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - axiDataIn_q [i] <= 1'b0; - end - else if (dataClear_q) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b1; - end - else if (axiReady_q & axiValid) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b0; - axiDataIn_q <= axiDataIn; - end -end - -assign axiReady = axiReady_q; -assign dataPending = ~(dataClear_q | axiReady_q); -assign dataOut = axiDataIn_q; - -endmodule - -// -// Provides common implementation of dual AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x2 - (axiValid, axiReady, axiDataIn1, axiDataIn2, dataPending, dataClear, - dataOut1, dataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth1-1:0] axiDataIn1; -input [DataWidth2-1:0] axiDataIn2; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth1-1:0] dataOut1; -output [DataWidth2-1:0] dataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] dataOut; - -// Instantiate the single input register module. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (axiValid, axiReady, {axiDataIn2, axiDataIn1}, dataPending, dataClear, - dataOut, clk, srst); - -assign dataOut1 = dataOut [DataWidth1-1:0]; -assign dataOut2 = dataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - -// -// Provides common implementation of single AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x1 - (dataPush, dataBlocked, dataIn, axiValid, axiReady, axiDataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth-1:0] dataIn; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth-1:0] axiDataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataReady_q; -reg [DataWidth-1:0] dataReg_q; - -integer i; - -// Implements a single AXI output register. -always @(posedge clk) -begin - if (srst) - begin - dataReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - dataReg_q [i] <= 1'b0; - end - else if (dataReady_q & axiReady) - begin - dataReady_q <= 1'b0; - end - else if (dataPush) - begin - dataReady_q <= 1'b1; - dataReg_q <= dataIn; - end -end - -assign dataBlocked = dataReady_q; -assign axiValid = dataReady_q; -assign axiDataOut = dataReg_q; - -endmodule - -// -// Provides common implementation of dual AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x2 - (dataPush, dataBlocked, dataIn1, dataIn2, axiValid, axiReady, axiDataOut1, - axiDataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth1-1:0] dataIn1; -input [DataWidth2-1:0] dataIn2; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth1-1:0] axiDataOut1; -output [DataWidth2-1:0] axiDataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] axiDataOut; - -// Instantiate the single output register module. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (dataPush, dataBlocked, {dataIn2, dataIn1}, axiValid, axiReady, - axiDataOut, clk, srst); - -assign axiDataOut1 = axiDataOut [DataWidth1-1:0]; -assign axiDataOut2 = axiDataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v deleted file mode 100644 index 925d6d3..0000000 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v +++ /dev/null @@ -1,259 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel reset handler. It provides support for -// managing kernel resets under control of the external 'go' and 'done' control -// signals. -// - -`timescale 1ns/1ps - -module sda_kernel_reset_handler - (regGoValid, regGoHoldoff, regDoneValid, regDoneStop, kernelGoValid, - kernelGoHoldoff, kernelDoneValid, kernelDoneStop, sysRstReq, wrapperReset, - kernelReset, clk); - -// Specifies the reset counter size. The kernel reset line will be asserted for -// the time it takes the counter to wrap. -parameter ResetCountSize = 5; - -// Specifies the length of the reset pipeline, which allows the synthesis tools -// to build a reset tree if required by using register duplication. -parameter ResetPipeLength = 8; - -// Derives the reset counter limit. -parameter ResetCountLimit = (1 << ResetCountSize) - 1; - -// Specify the reset controller state space. -parameter [2:0] - ResetIdle = 0, - ResetTimeout = 1, - KernelStarting = 2, - KernelRunning = 3, - KernelExited = 4; - -// Upstream register interface signals. -input regGoValid; -output regGoHoldoff; -output regDoneValid; -input regDoneStop; - -// Kernel control go output signals. -output kernelGoValid; -input kernelGoHoldoff; -input kernelDoneValid; -output kernelDoneStop; - -// Specifies the system reset request signal and generated resets. -input sysRstReq; -output wrapperReset; -output kernelReset; - -// Specifies the clock input. There is no standard synchronous reset. -input clk; - -// Reset control state machine signals. -reg [2:0] resetState_d; -reg [ResetCountSize-1:0] resetCount_d; -reg kernelReset_d; -reg regGoHoldoff_d; -reg regDoneValid_d; -reg kernelGoValid_d; -reg kernelDoneStop_d; - -reg [2:0] resetState_q; -reg [ResetCountSize-1:0] resetCount_q; -reg kernelReset_q; -reg regGoHoldoff_q; -reg regDoneValid_q; -reg kernelGoValid_q; -reg kernelDoneStop_q; - -// Implements a register with an explicit initialisation value, which will have -// the effect of forcing a reset cycle immediately after loading the FPGA -// netlist. Only works with devices that support bitstream initalisation. -reg resetHandlerEnabled_q = 1'b0; -reg wrapperReset_q; - -// Specifies the reset pipeline signals. -reg [ResetPipeLength-1:0] wrapperResetPipe_q; -reg [ResetPipeLength-1:0] kernelResetPipe_q; - -// Miscellaneous signals. -integer i; - -// Initiate automatic reset on FPGA bitstream load. -always @(posedge clk) -begin - if (sysRstReq | ~resetHandlerEnabled_q) - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b1; - end - else - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b0; - end -end - -// Implement combinatorial logic for reset control state machine. -always @(resetState_q, resetCount_q, kernelReset_q, regGoHoldoff_q, regDoneValid_q, - kernelGoValid_q, kernelDoneStop_q, regGoValid, regDoneStop, kernelGoHoldoff, - kernelDoneValid) -begin - - // Hold current state by default. - resetState_d = resetState_q; - resetCount_d = resetCount_q; - kernelReset_d = kernelReset_q; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - - // Implement state machine. - case (resetState_q) - - // Hold the reset state for the required timeout. - ResetTimeout : - begin - if (resetCount_q == ResetCountLimit [ResetCountSize-1:0]) - begin - resetState_d = ResetIdle; - end - resetCount_d = resetCount_q + 1; - end - - // Wait for the kernel to accept the go signal. - KernelStarting : - begin - if (kernelGoValid_q & ~kernelGoHoldoff) - begin - resetState_d = KernelRunning; - end - else - begin - kernelGoValid_d = 1'b1; - end - end - - // In the kernel runnning state, wait for the 'done' response. - KernelRunning : - begin - if (kernelDoneValid & ~kernelDoneStop_q) - begin - resetState_d = KernelExited; - end - else - begin - kernelDoneStop_d = 1'b0; - end - end - - // In the kernel exited state, notify the control registers and place the - // kernel in reset until the next go request is received. - KernelExited : - begin - if (regDoneValid_q & ~regDoneStop) - begin - resetState_d = ResetTimeout; - kernelReset_d = 1'b1; - end - else - begin - regDoneValid_d = 1'b1; - end - end - - // In the reset idle state, wait for a go request from the register block - // before releasing the kernel reset. - ResetIdle : - begin - if (regGoValid & ~regGoHoldoff_q) - begin - resetState_d = KernelStarting; - kernelReset_d = 1'b0; - end - else - begin - regGoHoldoff_d = 1'b0; - end - end - - // Treat the unreachable default state as a hard reset. This prevents the - // Xilinx tools from generating dangling nets if the state encoding is - // automatically converted to one-hot. - default: - begin - resetState_d = ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_d [i] = 1'b0; - kernelReset_d = 1'b1; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - end - endcase - -end - -// Implement sequential logic for reset control state machine. -always @(posedge clk) -begin - if (wrapperReset_q) - begin - resetState_q <= ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_q [i] <= 1'b0; - kernelReset_q <= 1'b1; - regGoHoldoff_q <= 1'b1; - regDoneValid_q <= 1'b0; - kernelGoValid_q <= 1'b0; - kernelDoneStop_q <= 1'b1; - end - else - begin - resetState_q <= resetState_d; - resetCount_q <= resetCount_d; - kernelReset_q <= kernelReset_d; - regGoHoldoff_q <= regGoHoldoff_d; - regDoneValid_q <= regDoneValid_d; - kernelGoValid_q <= kernelGoValid_d; - kernelDoneStop_q <= kernelDoneStop_d; - end -end - -assign regGoHoldoff = regGoHoldoff_q; -assign regDoneValid = regDoneValid_q; -assign kernelGoValid = kernelGoValid_q; -assign kernelDoneStop = kernelDoneStop_q; - -// Implement reset output pipelines. -always @(posedge clk) -begin - if (wrapperReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - wrapperResetPipe_q [i] <= 1'b1; - else - wrapperResetPipe_q <= { 1'b0, wrapperResetPipe_q [ResetPipeLength-1:1] }; -end - -always @(posedge clk) -begin - if (kernelReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - kernelResetPipe_q [i] <= 1'b1; - else - kernelResetPipe_q <= { 1'b0, kernelResetPipe_q [ResetPipeLength-1:1] }; -end - -assign wrapperReset = wrapperResetPipe_q [0]; -assign kernelReset = kernelResetPipe_q [0]; - -endmodule diff --git a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v b/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v deleted file mode 100644 index 95054a0..0000000 --- a/histogram-parallel/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v +++ /dev/null @@ -1,390 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Provides the common wrapper code around an existing 'action' block so that it -// can be used in the context of an SDAccel 'kernel' block. This variant -// supports the complete set of control registers at AXI slave offset zero which -// are used to map the SDAccel run/status programming interface to the action -// block run/done SELF handshake lines. This wrapper implements a single AXI -// master interface which can access the shared global memory area on the FPGA -// card. -// - -`timescale 1ns/1ps - -// Can be redefined on the synthesis command line. -`ifndef AXI_SLAVE_ADDR_WIDTH -`define AXI_SLAVE_ADDR_WIDTH 16 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ADDR_WIDTH -`define AXI_MASTER_ADDR_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_DATA_WIDTH -`define AXI_MASTER_DATA_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ID_WIDTH -`define AXI_MASTER_ID_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_USER_WIDTH -`define AXI_MASTER_USER_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_CACHE_MASK -`define AXI_MASTER_CACHE_MASK 4'b0011 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_PARAM_MEM_ADDR_WIDTH -`define AXI_PARAM_MEM_ADDR_WIDTH 12 -`endif - -// Module name to be substituted in post-synthesis netlist. -module sda_kernel_wrapper_gmem - (s_axi_control_AWADDR, s_axi_control_AWVALID, s_axi_control_AWREADY, - s_axi_control_WDATA, s_axi_control_WSTRB, s_axi_control_WVALID, - s_axi_control_WREADY, s_axi_control_BRESP, s_axi_control_BVALID, - s_axi_control_BREADY, s_axi_control_ARADDR, s_axi_control_ARVALID, - s_axi_control_ARREADY, s_axi_control_RDATA, s_axi_control_RRESP, - s_axi_control_RVALID, s_axi_control_RREADY, m_axi_gmem_AWADDR, - m_axi_gmem_AWLEN, m_axi_gmem_AWSIZE, m_axi_gmem_AWBURST, m_axi_gmem_AWLOCK, - m_axi_gmem_AWREGION, m_axi_gmem_AWCACHE, m_axi_gmem_AWPROT, m_axi_gmem_AWQOS, - m_axi_gmem_AWID, m_axi_gmem_AWUSER, m_axi_gmem_AWVALID, m_axi_gmem_AWREADY, - m_axi_gmem_WDATA, m_axi_gmem_WSTRB, m_axi_gmem_WLAST, m_axi_gmem_WID, - m_axi_gmem_WUSER, m_axi_gmem_WVALID, m_axi_gmem_WREADY, m_axi_gmem_BRESP, - m_axi_gmem_BID, m_axi_gmem_BUSER, m_axi_gmem_BVALID, m_axi_gmem_BREADY, - m_axi_gmem_ARADDR, m_axi_gmem_ARLEN, m_axi_gmem_ARSIZE, m_axi_gmem_ARBURST, - m_axi_gmem_ARLOCK, m_axi_gmem_ARREGION, m_axi_gmem_ARCACHE, m_axi_gmem_ARPROT, - m_axi_gmem_ARQOS, m_axi_gmem_ARID, m_axi_gmem_ARUSER, m_axi_gmem_ARVALID, - m_axi_gmem_ARREADY, m_axi_gmem_RDATA, m_axi_gmem_RRESP, m_axi_gmem_RLAST, - m_axi_gmem_RID, m_axi_gmem_RUSER, m_axi_gmem_RVALID, m_axi_gmem_RREADY, - ap_clk, ap_rst_n, interrupt); - -// Specifies the AXI slave write address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_AWADDR; -input s_axi_control_AWVALID; -output s_axi_control_AWREADY; - -// Specifies the AXI slave write data signals. -input [31:0] s_axi_control_WDATA; -input [3:0] s_axi_control_WSTRB; -input s_axi_control_WVALID; -output s_axi_control_WREADY; - -// Specifies the AXI slave write response signals. -output [1:0] s_axi_control_BRESP; -output s_axi_control_BVALID; -input s_axi_control_BREADY; - -// Specifies the AXI slave read address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_ARADDR; -input s_axi_control_ARVALID; -output s_axi_control_ARREADY; - -// Specifies the AXI slave read data signals. -output [31:0] s_axi_control_RDATA; -output [1:0] s_axi_control_RRESP; -output s_axi_control_RVALID; -input s_axi_control_RREADY; - -// Specifies the AXI master write address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_AWADDR; -output [7:0] m_axi_gmem_AWLEN; -output [2:0] m_axi_gmem_AWSIZE; -output [1:0] m_axi_gmem_AWBURST; -output [1:0] m_axi_gmem_AWLOCK; -output [3:0] m_axi_gmem_AWCACHE; -output [2:0] m_axi_gmem_AWPROT; -output [3:0] m_axi_gmem_AWQOS; -output [3:0] m_axi_gmem_AWREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_AWID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_AWUSER; -output m_axi_gmem_AWVALID; -input m_axi_gmem_AWREADY; - -// Specifies the AXI master write data signals. -output [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_WDATA; -output [`AXI_MASTER_DATA_WIDTH/8-1:0] m_axi_gmem_WSTRB; -output m_axi_gmem_WLAST; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_WID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_WUSER; -output m_axi_gmem_WVALID; -input m_axi_gmem_WREADY; - -// Specifies the AXI master write response signals. -input [1:0] m_axi_gmem_BRESP; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_BID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_BUSER; -input m_axi_gmem_BVALID; -output m_axi_gmem_BREADY; - -// Specifies the AXI master read address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_ARADDR; -output [7:0] m_axi_gmem_ARLEN; -output [2:0] m_axi_gmem_ARSIZE; -output [1:0] m_axi_gmem_ARBURST; -output [1:0] m_axi_gmem_ARLOCK; -output [3:0] m_axi_gmem_ARCACHE; -output [2:0] m_axi_gmem_ARPROT; -output [3:0] m_axi_gmem_ARQOS; -output [3:0] m_axi_gmem_ARREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_ARID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_ARUSER; -output m_axi_gmem_ARVALID; -input m_axi_gmem_ARREADY; - -// Specifies the AXI master read data signals. -input [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_RDATA; -input [1:0] m_axi_gmem_RRESP; -input m_axi_gmem_RLAST; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_RID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_RUSER; -input m_axi_gmem_RVALID; -output m_axi_gmem_RREADY; - -// Specifies the system level I/O signals. -input ap_clk; -input ap_rst_n; - -// verilator lint_off SYMRSVDWORD -output interrupt; -// verilator lint_on SYMRSVDWORD - -// Reset management signals. -wire reg_go_valid; -wire reg_go_holdoff; -wire reg_done_valid; -wire reg_done_stop; -wire kernel_reset; -wire wrapper_reset; - -// AXI control interface master write address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_AWADDR; -wire [3:0] m_axi_control_AWCACHE; -wire [2:0] m_axi_control_AWPROT; -wire m_axi_control_AWVALID; -wire m_axi_control_AWREADY; - -// AXI control interface master write data signals. -wire [31:0] m_axi_control_WDATA; -wire [3:0] m_axi_control_WSTRB; -wire m_axi_control_WVALID; -wire m_axi_control_WREADY; - -// AXI control interface master write response signals. -wire [1:0] m_axi_control_BRESP; -wire m_axi_control_BVALID; -wire m_axi_control_BREADY; - -// AXI control interface master read address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_ARADDR; -wire [3:0] m_axi_control_ARCACHE; -wire [2:0] m_axi_control_ARPROT; -wire m_axi_control_ARVALID; -wire m_axi_control_ARREADY; - -// AXI control interface master read data signals. -wire [31:0] m_axi_control_RDATA; -wire [1:0] m_axi_control_RRESP; -wire m_axi_control_RVALID; -wire m_axi_control_RREADY; - -// AXI master interface intermediate signals. -wire [3:0] m_axi_gmem_local_ARCACHE; -wire [3:0] m_axi_gmem_local_AWCACHE; - -// Wrapper control register interface signals. -wire reg_req; -wire reg_ack; -wire reg_ack_0; -wire reg_ack_1; -wire reg_write_en; -wire [`AXI_PARAM_MEM_ADDR_WIDTH-1:0] reg_addr; -wire [31:0] reg_wdata; -wire [3:0] reg_wstrb; -wire [31:0] reg_rdata; -wire [31:0] reg_rdata_0; -wire [31:0] reg_rdata_1; - -// Kernel interface parameter access signals. -wire param_addr_valid; -wire [31:0] param_addr; -wire param_addr_stop; -wire param_data_valid; -wire [31:0] param_data; -wire param_data_stop; - -// Action control signals. -wire go_0Ready; -wire go_0Stop; -wire done_0Ready; -wire done_0Stop; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [31:0] m_axi_control_ext_AWADDR; -wire [31:0] m_axi_control_ext_ARADDR; - -// Tie off unused control interface signals. -assign m_axi_control_AWCACHE = 4'b0000; -assign m_axi_control_AWPROT = 3'b010; -assign m_axi_control_ARCACHE = 4'b0000; -assign m_axi_control_ARPROT = 3'b010; - -// Tie off upper bit of the lock signals for AXI3 backward compatibility. -assign m_axi_gmem_AWLOCK[1] = 1'b0; -assign m_axi_gmem_ARLOCK[1] = 1'b0; - -// Tie off unused WID signal -`ifndef AXI_MASTER_HAS_WID -assign m_axi_gmem_WID = `AXI_MASTER_ID_WIDTH'd0; -`endif - -// Apply cache mask to restrict memory access modes if required. The default -// is to restrict accesses to device mode only, as required by the AWS shell. -assign m_axi_gmem_ARCACHE = m_axi_gmem_local_ARCACHE & `AXI_MASTER_CACHE_MASK; -assign m_axi_gmem_AWCACHE = m_axi_gmem_local_AWCACHE & `AXI_MASTER_CACHE_MASK; - -// Instantiate the reset controller. -sda_kernel_reset_handler resetHandler_u - (reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, go_0Ready, - go_0Stop, done_0Ready, done_0Stop, ~ap_rst_n, wrapper_reset, kernel_reset, - ap_clk); - -// Instantiate the AXI slave register selection component. -sda_kernel_ctrl_reg_sel #(`AXI_SLAVE_ADDR_WIDTH, `AXI_PARAM_MEM_ADDR_WIDTH, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlRegSel_u - (s_axi_control_AWVALID, s_axi_control_AWREADY, s_axi_control_AWADDR, - s_axi_control_WVALID, s_axi_control_WREADY, s_axi_control_WDATA, - s_axi_control_WSTRB, s_axi_control_BVALID, s_axi_control_BREADY, - s_axi_control_BRESP, s_axi_control_ARVALID, s_axi_control_ARREADY, - s_axi_control_ARADDR, s_axi_control_RVALID, s_axi_control_RREADY, - s_axi_control_RDATA, s_axi_control_RRESP, m_axi_control_AWVALID, - m_axi_control_AWREADY, m_axi_control_AWADDR, m_axi_control_WVALID, - m_axi_control_WREADY, m_axi_control_WDATA, m_axi_control_WSTRB, - m_axi_control_BVALID, m_axi_control_BREADY, m_axi_control_BRESP, - m_axi_control_ARVALID, m_axi_control_ARREADY, m_axi_control_ARADDR, - m_axi_control_RVALID, m_axi_control_RREADY, m_axi_control_RDATA, - m_axi_control_RRESP, reg_req, reg_ack, reg_write_en, reg_addr, reg_wdata, - reg_wstrb, reg_rdata, ap_clk, wrapper_reset); - -// Instantiate the kernel control registers at slave address offset 0. -sda_kernel_ctrl_reg #(`AXI_PARAM_MEM_ADDR_WIDTH, 63) kernelCtrlReg_u - (reg_req, reg_ack_0, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_0, - reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, interrupt, ap_clk, - wrapper_reset); - -// Instantiate the kernel parameter memory. -sda_kernel_ctrl_param #(`AXI_PARAM_MEM_ADDR_WIDTH, 64, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlParam_u - (reg_req, reg_ack_1, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_1, - param_addr_valid, param_addr, param_addr_stop, param_data_valid, param_data, - param_data_stop, ap_clk, wrapper_reset); - -assign reg_ack = reg_ack_0 | reg_ack_1; -assign reg_rdata = reg_rdata_0 | reg_rdata_1 | zeros; - -// Extend the slave address bus widths to the standard 32 bit value for the -// action logic core. -assign m_axi_control_ext_AWADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_AWADDR}; -assign m_axi_control_ext_ARADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_ARADDR}; - -// Instantiate the simple generated action logic core. -teak__action__top__gmem kernelActionTop_u ( - .go_0Ready (go_0Ready), - .go_0Stop (go_0Stop), - .done_0Ready (done_0Ready), - .done_0Stop (done_0Stop), - .s_axi_araddr (m_axi_control_ext_ARADDR), - .s_axi_arcache (m_axi_control_ARCACHE), - .s_axi_arprot (m_axi_control_ARPROT), - .s_axi_arvalid (m_axi_control_ARVALID), - .s_axi_arready (m_axi_control_ARREADY), - .s_axi_rdata (m_axi_control_RDATA), - .s_axi_rresp (m_axi_control_RRESP), - .s_axi_rvalid (m_axi_control_RVALID), - .s_axi_rready (m_axi_control_RREADY), - .s_axi_awaddr (m_axi_control_ext_AWADDR), - .s_axi_awcache (m_axi_control_AWCACHE), - .s_axi_awprot (m_axi_control_AWPROT), - .s_axi_awvalid (m_axi_control_AWVALID), - .s_axi_awready (m_axi_control_AWREADY), - .s_axi_wdata (m_axi_control_WDATA), - .s_axi_wstrb (m_axi_control_WSTRB), - .s_axi_wvalid (m_axi_control_WVALID), - .s_axi_wready (m_axi_control_WREADY), - .s_axi_bresp (m_axi_control_BRESP), - .s_axi_bvalid (m_axi_control_BVALID), - .s_axi_bready (m_axi_control_BREADY), - .m_axi_gmem_awaddr (m_axi_gmem_AWADDR), - .m_axi_gmem_awlen (m_axi_gmem_AWLEN), - .m_axi_gmem_awsize (m_axi_gmem_AWSIZE), - .m_axi_gmem_awburst (m_axi_gmem_AWBURST), - .m_axi_gmem_awlock (m_axi_gmem_AWLOCK[0]), - .m_axi_gmem_awcache (m_axi_gmem_local_AWCACHE), - .m_axi_gmem_awprot (m_axi_gmem_AWPROT), - .m_axi_gmem_awqos (m_axi_gmem_AWQOS), - .m_axi_gmem_awregion (m_axi_gmem_AWREGION), - .m_axi_gmem_awid (m_axi_gmem_AWID), - .m_axi_gmem_awuser (m_axi_gmem_AWUSER), - .m_axi_gmem_awvalid (m_axi_gmem_AWVALID), - .m_axi_gmem_awready (m_axi_gmem_AWREADY), - .m_axi_gmem_wdata (m_axi_gmem_WDATA), - .m_axi_gmem_wstrb (m_axi_gmem_WSTRB), - .m_axi_gmem_wlast (m_axi_gmem_WLAST), -`ifdef AXI_MASTER_HAS_WID - .m_axi_gmem_wid (m_axi_gmem_WID), -`endif - .m_axi_gmem_wuser (m_axi_gmem_WUSER), - .m_axi_gmem_wvalid (m_axi_gmem_WVALID), - .m_axi_gmem_wready (m_axi_gmem_WREADY), - .m_axi_gmem_bresp (m_axi_gmem_BRESP), - .m_axi_gmem_bid (m_axi_gmem_BID), - .m_axi_gmem_buser (m_axi_gmem_BUSER), - .m_axi_gmem_bvalid (m_axi_gmem_BVALID), - .m_axi_gmem_bready (m_axi_gmem_BREADY), - .m_axi_gmem_araddr (m_axi_gmem_ARADDR), - .m_axi_gmem_arlen (m_axi_gmem_ARLEN), - .m_axi_gmem_arsize (m_axi_gmem_ARSIZE), - .m_axi_gmem_arburst (m_axi_gmem_ARBURST), - .m_axi_gmem_arlock (m_axi_gmem_ARLOCK[0]), - .m_axi_gmem_arcache (m_axi_gmem_local_ARCACHE), - .m_axi_gmem_arprot (m_axi_gmem_ARPROT), - .m_axi_gmem_arqos (m_axi_gmem_ARQOS), - .m_axi_gmem_arregion (m_axi_gmem_ARREGION), - .m_axi_gmem_arid (m_axi_gmem_ARID), - .m_axi_gmem_aruser (m_axi_gmem_ARUSER), - .m_axi_gmem_arvalid (m_axi_gmem_ARVALID), - .m_axi_gmem_arready (m_axi_gmem_ARREADY), - .m_axi_gmem_rdata (m_axi_gmem_RDATA), - .m_axi_gmem_rresp (m_axi_gmem_RRESP), - .m_axi_gmem_rlast (m_axi_gmem_RLAST), - .m_axi_gmem_rid (m_axi_gmem_RID), - .m_axi_gmem_ruser (m_axi_gmem_RUSER), - .m_axi_gmem_rvalid (m_axi_gmem_RVALID), - .m_axi_gmem_rready (m_axi_gmem_RREADY), - .paramaddr_0Ready (param_addr_valid), - .paramaddr_0Data (param_addr), - .paramaddr_0Stop (param_addr_stop), - .paramdata_0Ready (param_data_valid), - .paramdata_0Data (param_data), - .paramdata_0Stop (param_data_stop), - .clk (ap_clk), - .reset (kernel_reset) -); - -endmodule diff --git a/memcopy/glide.lock b/memcopy/glide.lock deleted file mode 100644 index 9782a27..0000000 --- a/memcopy/glide.lock +++ /dev/null @@ -1,12 +0,0 @@ -hash: 8dae7d4b554c5dc4203a6aea5fcb855a3786d9b06d9a68dd567dee82c31071e3 -updated: 2018-08-27T21:51:10.978049+01:00 -imports: -- name: github.com/ReconfigureIO/sdaccel - version: 59bbcfa609e6dbc4af7ae0fbae373844f0a8ca3e - subpackages: - - axi/arbitrate - - axi/memory - - axi/protocol - - smi - - xcl -testImports: [] diff --git a/memcopy/glide.yaml b/memcopy/glide.yaml index a83597a..af4dac5 100644 --- a/memcopy/glide.yaml +++ b/memcopy/glide.yaml @@ -1,7 +1,7 @@ package: . import: - package: github.com/ReconfigureIO/sdaccel - version: ~0.18.0 + version: ~0.20.1 subpackages: - axi/arbitrate - axi/memory diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/framework.go b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/framework.go index abd3c23..ba4a82c 100644 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/framework.go +++ b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/framework.go @@ -1,10 +1,8 @@ +// +// TODO: This no longer does anything useful, so should be deleted once it is +// no longer referenced by example code. +// package sdaccel -// #include verilog/sda_kernel_reset_handler.v -// #include verilog/sda_kernel_ctrl_reg_sel.v -// #include verilog/sda_kernel_ctrl_reg.v -// #include verilog/sda_kernel_ctrl_param.v -// #include verilog/sda_kernel_wrapper_gmem.v - func init() { } diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go index 6d00f95..3d76a63 100644 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go +++ b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/smi/protocol.go @@ -68,24 +68,31 @@ type Flit64 struct { // TODO: Update once there is a fix for the channel size compiler limitation. // func ForwardFrame64( + forwardReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + forwardDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - go func() { - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } - }() + doForward := <-forwardReq + for doForward { + go func() { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } + }() - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + forwardDone <- true + doForward = <-forwardReq } } @@ -98,22 +105,29 @@ func ForwardFrame64( // TODO: Update once there is a fix for the channel size compiler limitation. // func AssembleFrame64( + assembleReq <-chan bool, smiInput <-chan Flit64, - smiOutput chan<- Flit64) { + smiOutput chan<- Flit64, + assembleDone chan<- bool) { smiBuffer := make(chan Flit64, 34 /* SmiMemFrame64Size */) - hasNextInputFlit := true - for hasNextInputFlit { - inputFlitData := <-smiInput - smiBuffer <- inputFlitData - hasNextInputFlit = inputFlitData.Eofc == uint8(0) - } + doAssemble := <-assembleReq + for doAssemble { + hasNextInputFlit := true + for hasNextInputFlit { + inputFlitData := <-smiInput + smiBuffer <- inputFlitData + hasNextInputFlit = inputFlitData.Eofc == uint8(0) + } - hasNextOutputFlit := true - for hasNextOutputFlit { - outputFlitData := <-smiBuffer - smiOutput <- outputFlitData - hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + hasNextOutputFlit := true + for hasNextOutputFlit { + outputFlitData := <-smiBuffer + smiOutput <- outputFlitData + hasNextOutputFlit = outputFlitData.Eofc == uint8(0) + } + assembleDone <- true + doAssemble = <-assembleReq } } @@ -1387,18 +1401,24 @@ func WriteBurstUInt64( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt64( + thisWriteOk := writeSingleBurstUInt64( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1427,18 +1447,24 @@ func WriteBurstUInt32( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt32( + thisWriteOk := writeSingleBurstUInt32( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1467,18 +1493,24 @@ func WriteBurstUInt16( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt16( + thisWriteOk := writeSingleBurstUInt16( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -1505,18 +1537,24 @@ func WriteBurstUInt8( burstOffset := uint16(writeAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiWriteChan := make(chan Flit64, 1) + asmReqChan := make(chan bool, 1) + asmDoneChan := make(chan bool, 1) + go AssembleFrame64(asmReqChan, smiWriteChan, smiRequest, asmDoneChan) for writeLength != 0 { - go AssembleFrame64(smiWriteChan, smiRequest) + asmReqChan <- true if writeLength < uint32(burstSize) { burstSize = uint16(writeLength) } - writeOk = writeOk && writeSingleBurstUInt8( + thisWriteOk := writeSingleBurstUInt8( smiWriteChan, smiResponse, writeAddr, writeOptions, burstSize, writeDataChan) + writeOk = writeOk && thisWriteOk writeAddr += uintptr(burstSize) writeLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-asmDoneChan } + asmReqChan <- false return writeOk } @@ -2026,18 +2064,24 @@ func ReadBurstUInt64( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt64( + thisReadOk := readSingleBurstUInt64( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2066,18 +2110,24 @@ func ReadBurstUInt32( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt32( + thisReadOk := readSingleBurstUInt32( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2106,18 +2156,24 @@ func ReadBurstUInt16( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt16( + thisReadOk := readSingleBurstUInt16( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } @@ -2144,17 +2200,23 @@ func ReadBurstUInt8( burstOffset := uint16(readAddr) & uint16(SmiMemBurstSize-1) burstSize := uint16(SmiMemBurstSize) - burstOffset smiReadChan := make(chan Flit64, 1) + fwdReqChan := make(chan bool, 1) + fwdDoneChan := make(chan bool, 1) + go ForwardFrame64(fwdReqChan, smiResponse, smiReadChan, fwdDoneChan) for readLength != 0 { - go ForwardFrame64(smiResponse, smiReadChan) + fwdReqChan <- true if readLength < uint32(burstSize) { burstSize = uint16(readLength) } - readOk = readOk && readSingleBurstUInt8( + thisReadOk := readSingleBurstUInt8( smiRequest, smiReadChan, readAddr, readOptions, burstSize, readDataChan) + readOk = readOk && thisReadOk readAddr += uintptr(burstSize) readLength -= uint32(burstSize) burstSize = uint16(SmiMemBurstSize) + <-fwdDoneChan } + fwdReqChan <- false return readOk } diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v deleted file mode 100644 index 406a034..0000000 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_param.v +++ /dev/null @@ -1,303 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implements the parameter RAM block which is provided on the AXI control bus -// for assigning kernel parameters prior to running kernel code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_param - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, - paramAddrValid, paramAddr, paramAddrStop, paramDataValid, paramData, - paramDataStop, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 12; - -// Specifies the base address of the parameter block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter ParamAddrBase = 64; - -// Specifies the upper address of the parameter block. -parameter ParamAddrTop = 4095; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; - -// Kernel interface parameter access signals. -input paramAddrValid; -input [31:0] paramAddr; -output paramAddrStop; -output paramDataValid; -output [31:0] paramData; -input paramDataStop; - -// System level signals. -input clk; -input srst; - -// Inferred RAM. -reg [31:0] ramArray [(ParamAddrTop-ParamAddrBase+1)/4-1:0]; - -// Pipelined register interface input inputs. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; -reg [RegAddrWidth-3:0] regAddr_q; - -// Pipelined register interface output inputs. -reg regAck_q; -reg regReadDone_q; -reg regReadValid_q; -reg [31:0] regRData_q; -reg [31:0] regReadData_q; -reg [31:0] regPipeData_q; - -// Pipelined parameter RAM access signals. -reg paramAddrValid_q; -reg [31:0] paramAddr_q; -reg paramDataValid_q; -reg [31:0] paramData_q; - -// Parameter RAM access backpressure signals. -wire pmAddrStop; -wire pmReadStop; -wire pmPipeStop; - -// Parameter RAM access pipeline. -reg [RegAddrWidth-3:0] pmAddr_q; -reg [1:0] pmAddrAlign_q; -reg pmAddrValid_q; -reg [31:0] pmReadData_q; -reg [1:0] pmReadAlign_q; -reg pmReadValid_q; -reg [31:0] pmPipeData_q; -reg [1:0] pmPipeAlign_q; -reg pmPipeValid_q; -reg [31:0] pmDataAligned; - -// Miscellaneous signals. -wire [RegAddrWidth-1:0] regParamAddrBase = ParamAddrBase [RegAddrWidth-1:0]; -wire [RegAddrWidth-1:0] regParamAddrTop = ParamAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipelined register input signals. Assumes that there are no back -// to back transactions, so we can use rising edge detection on the request line. -// verilator lint_off CMPCONST -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regWData_q <= regWData; - regWStrb_q <= regWStrb; - if ((regAddr < regParamAddrBase) || (regAddr > regParamAddrTop)) - begin - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - for (i = 0; i < RegAddrWidth-2; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regAddr_q <= regAddr[RegAddrWidth-1:2] - (ParamAddrBase/4); - end - end -end -// verilator lint_on CMPCONST - -// Implement pipelined register output signals. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regReadDone_q <= 1'b0; - regReadValid_q <= 1'b0; - regRData_q <= 32'b0; - end - else - begin - regAck_q <= regReadValid_q | regWriteReq_q; - regReadDone_q <= regReadReq_q; - regReadValid_q <= regReadDone_q; - regRData_q <= regReadValid_q ? regPipeData_q : 32'b0; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; - -// Implement pipelined parameter address inputs. -always @(posedge clk) -begin - if (srst) - begin - paramAddrValid_q <= 1'b0; - paramAddr_q <= 32'b0; - end - else if (paramAddrValid_q) - begin - paramAddrValid_q <= pmAddrStop; - end - else - begin - paramAddrValid_q <= paramAddrValid; - paramAddr_q <= paramAddr; - end -end - -assign paramAddrStop = paramAddrValid_q; - -// Implement the parameter data RAM access backpressure signals. -assign pmAddrStop = pmReadStop & pmAddrValid_q; -assign pmReadStop = pmPipeStop & pmReadValid_q; -assign pmPipeStop = paramDataValid_q & pmPipeValid_q; - -// Implement parameter access input pipeline. -always @(posedge clk) -begin - if (srst) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrValid_q <= 1'b0; - pmReadValid_q <= 1'b0; - pmPipeValid_q <= 1'b0; - end - else - begin - if (~pmAddrStop) - begin - pmAddrValid_q <= paramAddrValid_q; - if ((paramAddr_q < ParamAddrBase) || (paramAddr_q > ParamAddrTop)) - begin - for (i = 0; i < RegAddrWidth-2; i = i + 1) - pmAddr_q[i] <= 1'b0; - pmAddrAlign_q <= 2'b0; - end - else - begin - pmAddr_q <= paramAddr_q[RegAddrWidth-1:2] - (ParamAddrBase/4); - pmAddrAlign_q <= paramAddr_q[1:0]; - end - end - if (~pmReadStop) - begin - pmReadValid_q <= pmAddrValid_q; - pmReadAlign_q <= pmAddrAlign_q; - end - if (~pmPipeStop) - begin - pmPipeValid_q <= pmReadValid_q; - pmPipeAlign_q <= pmReadAlign_q; - end - end -end - -// Perform data alignment on read data. Uses the least significant bits of the -// parameter address to rotate the addressed byte into the LSB position. When -// combined with a suitable type cast in the kernel code, this allows byte and -// half word parameter values to be addressed on byte and half word boundaries. -always @(pmPipeAlign_q, pmPipeData_q) -begin - case (pmPipeAlign_q) - 2'b11 : pmDataAligned = {pmPipeData_q [23:0], pmPipeData_q [31:24]}; - 2'b10 : pmDataAligned = {pmPipeData_q [15:0], pmPipeData_q [31:16]}; - 2'b01 : pmDataAligned = {pmPipeData_q [7:0], pmPipeData_q [31:8]}; - default: pmDataAligned = pmPipeData_q; - endcase -end - -// Provide output pipeline register for read data. -always @(posedge clk) -begin - if (srst) - begin - paramDataValid_q <= 1'b0; - paramData_q <= 32'b0; - end - else if (paramDataValid_q) - begin - paramDataValid_q <= paramDataStop; - end - else - begin - paramDataValid_q <= pmPipeValid_q; - paramData_q <= pmDataAligned; - end -end - -assign paramDataValid = paramDataValid_q; -assign paramData = paramData_q; - -// Implement parameter RAM. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmReadStop) - begin - pmReadData_q <= ramArray [pmAddr_q]; - end - - // Register read pipeline is a single cycle delay. - regReadData_q <= ramArray [regAddr_q]; - - // Apply write enable strobes. - if (regWriteReq_q) - begin - if (regWStrb_q[0]) - ramArray [regAddr_q][7:0] <= regWData_q [7:0]; - if (regWStrb_q[1]) - ramArray [regAddr_q][15:8] <= regWData_q [15:8]; - if (regWStrb_q[2]) - ramArray [regAddr_q][23:16] <= regWData_q [23:16]; - if (regWStrb_q[3]) - ramArray [regAddr_q][31:24] <= regWData_q [31:24]; - end -end - -// Pipeline read data for improved timing. -always @(posedge clk) -begin - - // SELF parameter pipeline is gated for backpressure. - if (~pmPipeStop) - begin - pmPipeData_q <= pmReadData_q; - end - - // Register read pipeline is a single cycle delay. - regPipeData_q <= regReadData_q; - -end - -endmodule diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v deleted file mode 100644 index e25deb8..0000000 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg.v +++ /dev/null @@ -1,357 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control registers. This is a set of -// four registers which are located at address offset 0 in the SDAccel kernel -// control register space. -// -// The control unit uses the standard register layout for the SDAccel control -// register. For the basic control register this is as follows: -// Bit 0: start signal (R/W) - Start processing data when this bit is set. -// The state of bit 0 will be cleared on start of processing. -// Bit 1: done signal (RO) - Asserted when the processing is done. -// The state of bit 1 will be cleared on reads. -// Bit 2: idle signal (RO) - Asserted when not processing any data. -// The state of bit 2 will be cleared on starting a new processing cycle. -// Bit 3: ready signal (RO) - Asserted when ready to start processing. -// The state of bit 3 will be cleared on starting a new processing cycle. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg - (regReq, regAck, regWriteEn, regAddr, regWData, regWStrb, regRData, goValid, - goHoldoff, doneValid, doneStop, kernelIntr, clk, srst); - -// Specifies the width of the register address bus. -parameter RegAddrWidth = 8; - -// Specifies the upper address of the reserved address block. -// The default is to reserve space for 16 32-bit Verilog wrapper registers. -parameter RegAddrTop = 63; - -// Slave side simple register interface signals. Note that all outputs are -// driven low when inactive so that they can be ORed together with other -// register block implementations. The full register interface is implemented -// even though some of the register write bus is not used. -// verilator lint_off UNUSED -input regReq; -output regAck; -input regWriteEn; -input [RegAddrWidth-1:0] regAddr; -input [31:0] regWData; -input [3:0] regWStrb; -output [31:0] regRData; -// verilator lint_on UNUSED - -// Specify action go SELF control handshake signals. -output goValid; -input goHoldoff; - -// Specify action done SELF control handshake signals. -input doneValid; -output doneStop; - -// System level signals. -output kernelIntr; -input clk; -input srst; - -// Specify the register layout using byte offsets. Note that valid accesses -// must be aligned to 32-bit word boundaries. -parameter [31:0] - REG_ADDR_CTRL = 'h00, - REG_ADDR_GIE = 'h04, - REG_ADDR_IER = 'h08, - REG_ADDR_ISR = 'h0C; - -// Pipeline the register interface input signals. -reg regReq_q; -reg regReadReq_q; -reg regWriteReq_q; -reg regWData0_q; -reg regWData1_q; -reg regWStrb0_q; -reg [RegAddrWidth-1:0] regAddr_q; - -// Specify the control register bit signals. -reg ctrlBitStart_d; -reg ctrlBitDone_d; -reg ctrlBitIdle_d; -reg ctrlBitReady_d; -reg goValid_d; - -reg ctrlBitStart_q; -reg ctrlBitDone_q; -reg ctrlBitIdle_q; -reg ctrlBitReady_q; -reg goValid_q; - -// Specify the interrupt enable register bit signals. -reg gieBitEnable_d; -reg ierBitDoneEn_d; -reg ierBitReadyEn_d; - -reg gieBitEnable_q; -reg ierBitDoneEn_q; -reg ierBitReadyEn_q; - -// Specify the interrupt status register bit signals. -reg isrBitDone_d; -reg isrBitReady_d; - -reg isrBitDone_q; -reg isrBitReady_q; - -// Specify the read pipeline signals. -reg regAck_d; -reg [31:0] regRData_d; - -reg regAck_q; -reg [31:0] regRData_q; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [RegAddrWidth-1:0] regAddrTop = RegAddrTop [RegAddrWidth-1:0]; -integer i; - -// Implement pipeined register read interface signals. Assumes that there are -// no back to back transactions, so we can use rising edge detection on the -// request line. -always @(posedge clk) -begin - if (srst) - begin - regReq_q <= 1'b0; - regReadReq_q <= 1'b0; - regWriteReq_q <= 1'b0; - regWData0_q <= 1'b0; - regWData1_q <= 1'b0; - regWStrb0_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q[i] <= 1'b0; - end - else - begin - regReq_q <= regReq; - regReadReq_q <= regReq & ~regReq_q & ~regWriteEn; - regWriteReq_q <= regReq & ~regReq_q & regWriteEn; - regWData0_q <= regWData[0]; - regWData1_q <= regWData[1]; - regWStrb0_q <= regWStrb[0]; - regAddr_q <= regAddr; - end -end - -// Implement combinatorial logic for controlling register bit state. -always @(ctrlBitStart_q, ctrlBitDone_q, ctrlBitIdle_q, ctrlBitReady_q, - goValid_q, regReadReq_q, regWriteReq_q, regAddr_q, regWData0_q, regWStrb0_q, - goHoldoff, doneValid) -begin - - // Hold current state by default. - ctrlBitStart_d = ctrlBitStart_q; - ctrlBitDone_d = ctrlBitDone_q; - ctrlBitIdle_d = ctrlBitIdle_q; - ctrlBitReady_d = ctrlBitIdle_q & ~goHoldoff; - goValid_d = goValid_q; - - // Clear the 'done' bit on reads. - if (regReadReq_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitDone_d = 1'b0; - end - - // Assert the 'start' bit on register write requests. - if (regWriteReq_q & regWStrb0_q & regWData0_q & - (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0])) - begin - ctrlBitStart_d = 1'b1; - end - - // Attempt to initiate the SDAccel kernel operation. - if (ctrlBitStart_q & ctrlBitReady_q) - begin - if (goValid_q & ~goHoldoff) - begin - ctrlBitStart_d = 1'b0; - ctrlBitIdle_d = 1'b0; - ctrlBitReady_d = 1'b0; - goValid_d = 1'b0; - end - else - begin - goValid_d = 1'b1; - end - end - - // Detect completion of the SDAccel kernel operation. - if (~ctrlBitIdle_q & doneValid) - begin - ctrlBitDone_d = 1'b1; - ctrlBitIdle_d = 1'b1; - end - -end - -// Implement sequential logic for register bit values. -always @(posedge clk) -begin - if (srst) - begin - ctrlBitStart_q <= 1'b0; - ctrlBitDone_q <= 1'b0; - ctrlBitIdle_q <= 1'b1; - ctrlBitReady_q <= 1'b0; - goValid_q <= 1'b0; - end - else - begin - ctrlBitStart_q <= ctrlBitStart_d; - ctrlBitDone_q <= ctrlBitDone_d; - ctrlBitIdle_q <= ctrlBitIdle_d; - ctrlBitReady_q <= ctrlBitReady_d; - goValid_q <= goValid_d; - end -end - -assign goValid = goValid_q; -assign doneStop = ctrlBitIdle_q; - -// Implement combinatorial logic for interrupt enable registers. -always @(gieBitEnable_q, ierBitDoneEn_q, ierBitReadyEn_q, regWriteReq_q, - regAddr_q, regWData0_q, regWData1_q, regWStrb0_q) -begin - - // Hold current state by default. - gieBitEnable_d = gieBitEnable_q; - ierBitDoneEn_d = ierBitDoneEn_q; - ierBitReadyEn_d = ierBitReadyEn_q; - - // Set the global interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0])) - begin - gieBitEnable_d = regWData0_q; - end - - // Set the IP core interrupt enable register. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0])) - begin - ierBitDoneEn_d = regWData0_q; - ierBitReadyEn_d = regWData1_q; - end -end - -// Implement combinatorial logic for interrupt status register. This is a bit -// unconventional in that it allows the software to set interrupt status bits -// by toggling them. However this matches the Xilinx implementation since it -// may be a requirement for their closed source OpenCL software. -always @(isrBitDone_q, isrBitReady_q, ierBitDoneEn_q, ierBitReadyEn_q, - regWriteReq_q, regAddr_q, regWData0_q, regWData1_q, regWStrb0_q, - ctrlBitDone_q, ctrlBitReady_q) -begin - - // Hold current state by default. - isrBitDone_d = isrBitDone_q; - isrBitReady_d = isrBitReady_q; - - // Toggle the ISR bits under software control. - if (regWriteReq_q & regWStrb0_q & - (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0])) - begin - isrBitDone_d = isrBitDone_d ^ regWData0_q; - isrBitReady_d = isrBitReady_d ^ regWData1_q; - end - - // Assert the ISR bits on the 'done' and 'ready' signals. - isrBitDone_d = isrBitDone_d | ctrlBitDone_q; - isrBitReady_d = isrBitReady_d | ctrlBitReady_q; - - // Force ISR bits low if not enabled. - isrBitDone_d = isrBitDone_d & ierBitDoneEn_q; - isrBitReady_d = isrBitReady_d & ierBitReadyEn_q; - -end - -// Implement sequential logic for all interrupt registers. -always @(posedge clk) -begin - if (srst) - begin - gieBitEnable_q <= 1'b0; - ierBitDoneEn_q <= 1'b0; - ierBitReadyEn_q <= 1'b0; - isrBitDone_q <= 1'b0; - isrBitReady_q <= 1'b0; - end - else - begin - gieBitEnable_q <= gieBitEnable_d; - ierBitDoneEn_q <= ierBitDoneEn_d; - ierBitReadyEn_q <= ierBitReadyEn_d; - isrBitDone_q <= isrBitDone_d; - isrBitReady_q <= isrBitReady_d; - end -end - -// Implement combinatorial read register. -always @(regReadReq_q, regWriteReq_q, regAddr_q, ctrlBitIdle_q, ctrlBitDone_q, - ctrlBitStart_q, ctrlBitReady_q, gieBitEnable_q, ierBitDoneEn_q, - ierBitReadyEn_q, isrBitDone_q, isrBitReady_q, zeros, regAddrTop) -begin - - // Implement the read mux. - if (regReadReq_q) - begin - if (regAddr_q == REG_ADDR_CTRL[RegAddrWidth-1:0]) - regRData_d = {zeros[31:4], ctrlBitReady_q, - ctrlBitIdle_q, ctrlBitDone_q, ctrlBitStart_q}; - else if (regAddr_q == REG_ADDR_GIE[RegAddrWidth-1:0]) - regRData_d = {zeros[31:1], gieBitEnable_q}; - else if (regAddr_q == REG_ADDR_IER[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], ierBitReadyEn_q, ierBitDoneEn_q}; - else if (regAddr_q == REG_ADDR_ISR[RegAddrWidth-1:0]) - regRData_d = {zeros[31:2], isrBitReady_q, isrBitDone_q}; - else - regRData_d = zeros[31:0]; - end - else - begin - regRData_d = zeros[31:0]; - end - - // Acknowledge all accesses to the reserved register set. - if (regAddr_q <= regAddrTop) - regAck_d = regReadReq_q | regWriteReq_q; - else - regAck_d = 1'b0; - -end - -// Implement sequential read register. -always @(posedge clk) -begin - if (srst) - begin - regAck_q <= 1'b0; - regRData_q <= zeros[31:0]; - end - else - begin - regAck_q <= regAck_d; - regRData_q <= regRData_d; - end -end - -assign regAck = regAck_q; -assign regRData = regRData_q; -assign kernelIntr = gieBitEnable_q & (isrBitDone_q | isrBitReady_q); - -endmodule diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v deleted file mode 100644 index 67e6ac0..0000000 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_ctrl_reg_sel.v +++ /dev/null @@ -1,651 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel entity control register selection unit. It -// maps the specified number of AXI slave interface registers at the start of -// the AXI address space to simple wrapper control registers and then maps the -// remaining locations to the AXI interface handler in the generated code. -// - -`timescale 1ns/1ps - -module sda_kernel_ctrl_reg_sel - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiWValid, sAxiWReady, sAxiWData, - sAxiWStrb, sAxiBValid, sAxiBReady, sAxiBResp, sAxiARValid, sAxiARReady, - sAxiARAddr, sAxiRValid, sAxiRReady, sAxiRData, sAxiRResp, mAxiAWValid, - mAxiAWReady, mAxiAWAddr, mAxiWValid, mAxiWReady, mAxiWData, mAxiWStrb, - mAxiBValid, mAxiBReady, mAxiBResp, mAxiARValid, mAxiARReady, mAxiARAddr, - mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, regReq, regAck, regWriteEn, - regAddr, regWData, regWStrb, regRData, clk, srst); - -// Specifies the width of the AXI address bus. -parameter AddrWidth = 16; - -// Specifies the width of the local register set address bus. -parameter RegAddrWidth = 8; - -// Specify the upper address location which is mapped to the local register set. -parameter RegAddrTop = 255; - -// Slave side AXI write address channel signals. -input sAxiAWValid; -output sAxiAWReady; -input [AddrWidth-1:0] sAxiAWAddr; - -// Slave side AXI write data channel signals. -input sAxiWValid; -output sAxiWReady; -input [31:0] sAxiWData; -input [3:0] sAxiWStrb; - -// Slave side AXI write acknowledgement channel signals. -output sAxiBValid; -input sAxiBReady; -output [1:0] sAxiBResp; - -// Slave side AXI read address channel signals. -input sAxiARValid; -output sAxiARReady; -input [AddrWidth-1:0] sAxiARAddr; - -// Slave side AXI read data channel signals. -output sAxiRValid; -input sAxiRReady; -output [31:0] sAxiRData; -output [1:0] sAxiRResp; - -// Master side AXI write address channel signals. -output mAxiAWValid; -input mAxiAWReady; -output [AddrWidth-1:0] mAxiAWAddr; - -// Master side AXI write data channel signals. -output mAxiWValid; -input mAxiWReady; -output [31:0] mAxiWData; -output [3:0] mAxiWStrb; - -// Master side AXI write acknowledgement channel signals. -input mAxiBValid; -output mAxiBReady; -input [1:0] mAxiBResp; - -// Master side AXI read address channel signals. -output mAxiARValid; -input mAxiARReady; -output [AddrWidth-1:0] mAxiARAddr; - -// Slave side AXI read data channel signals. -input mAxiRValid; -output mAxiRReady; -input [31:0] mAxiRData; -input [1:0] mAxiRResp; - -// Master side simple register interface signals. -output regReq; -input regAck; -output regWriteEn; -output [RegAddrWidth-1:0] regAddr; -output [31:0] regWData; -output [3:0] regWStrb; -input [31:0] regRData; - -// System level signals. -input clk; -input srst; - -// AXI write address channel register signals. -wire sAxiAWPending; -reg sAxiAWClear; -wire [AddrWidth-1:0] sAxiAWAddrReg; -reg mAxiAWPush; -wire mAxiAWBlocked; -wire [AddrWidth-1:0] mAxiAWAddrReg; - -// AXI write data channel register signals. -wire sAxiWPending; -reg sAxiWClear; -wire [31:0] sAxiWDataReg; -wire [3:0] sAxiWStrbReg; -reg mAxiWPush; -wire mAxiWBlocked; -wire [31:0] mAxiWDataReg; -wire [3:0] mAxiWStrbReg; - -// AXI read address channel register signals. -wire sAxiARPending; -reg sAxiARClear; -wire [AddrWidth-1:0] sAxiARAddrReg; -reg mAxiARPush; -wire mAxiARBlocked; -wire [AddrWidth-1:0] mAxiARAddrReg; - -// AXI write response channel register signals. -wire mAxiBPending; -reg mAxiBClear; -wire [1:0] mAxiBRespReg; -reg sAxiBPush; -wire sAxiBBlocked; -reg [1:0] sAxiBRespReg; - -// AXI read response channel register signals. -wire mAxiRPending; -reg mAxiRClear; -wire [31:0] mAxiRDataReg; -wire [1:0] mAxiRRespReg; -reg sAxiRPush; -wire sAxiRBlocked; -reg [31:0] sAxiRDataReg; -reg [1:0] sAxiRRespReg; - -// Specify the state space used to select the AXI transaction mode. -parameter [3:0] - Idle = 0, - RegReadStart = 1, - RegReadActive = 2, - RegWriteStart = 3, - RegWriteActive = 4, - AxiReadStart = 5, - AxiReadActive = 6, - AxiWriteStart = 7, - AxiWriteData = 8, - AxiWriteActive = 9; - -// Specify AXI state machine registers. -reg [3:0] axiState_d; -reg regReq_d; -reg regWriteEn_d; -reg [RegAddrWidth-1:0] regAddr_d; -reg [31:0] regWData_d; -reg [3:0] regWStrb_d; - -reg [3:0] axiState_q; -reg regReq_q; -reg regWriteEn_q; -reg [RegAddrWidth-1:0] regAddr_q; -reg [31:0] regWData_q; -reg [3:0] regWStrb_q; - -// Miscellaneous signals. -wire [AddrWidth-1:0] regAddrTop = RegAddrTop [AddrWidth-1:0]; -integer i; - -// Instantiate input registers for slave side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiAWReg_u - (sAxiAWValid, sAxiAWReady, sAxiAWAddr, sAxiAWPending, sAxiAWClear, - sAxiAWAddrReg, clk, srst); - -// Instantiate input registers for slave side AXI data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 4) sAxiWReg_u - (sAxiWValid, sAxiWReady, sAxiWData, sAxiWStrb, sAxiWPending, - sAxiWClear, sAxiWDataReg, sAxiWStrbReg, clk, srst); - -// Instantiate input registers for slave side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(AddrWidth) sAxiARReg_u - (sAxiARValid, sAxiARReady, sAxiARAddr, sAxiARPending, sAxiARClear, - sAxiARAddrReg, clk, srst); - -// Instantiate input register for master side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(2) mAxiBReg_u - (mAxiBValid, mAxiBReady, mAxiBResp, mAxiBPending, mAxiBClear, mAxiBRespReg, - clk, srst); - -// Instantiate input register for master side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_inreg_x2 #(32, 2) mAxiRReg_u - (mAxiRValid, mAxiRReady, mAxiRData, mAxiRResp, mAxiRPending, - mAxiRClear, mAxiRDataReg, mAxiRRespReg, clk, srst); - -// Instantate output register for master side AXI write address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiAWReg_u - (mAxiAWPush, mAxiAWBlocked, mAxiAWAddrReg, mAxiAWValid, mAxiAWReady, - mAxiAWAddr, clk, srst); - -// Instantiate output register for master side AXI write data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 4) mAxiWReg_u - (mAxiWPush, mAxiWBlocked, mAxiWDataReg, mAxiWStrbReg, mAxiWValid, - mAxiWReady, mAxiWData, mAxiWStrb, clk, srst); - -// Instantiate output register for master side AXI read address channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(AddrWidth) mAxiARReg_u - (mAxiARPush, mAxiARBlocked, mAxiARAddrReg, mAxiARValid, mAxiARReady, - mAxiARAddr, clk, srst); - -// Instantiate output register for slave side AXI write acknowledgement. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(2) sAxiBReg_u - (sAxiBPush, sAxiBBlocked, sAxiBRespReg, sAxiBValid, sAxiBReady, sAxiBResp, - clk, srst); - -// Instantiate output register for slave side AXI read data channel. -sda_kernel_ctrl_reg_sel_axi_outreg_x2 #(32, 2) sAxiRReg_u - (sAxiRPush, sAxiRBlocked, sAxiRDataReg, sAxiRRespReg, sAxiRValid, - sAxiRReady, sAxiRData, sAxiRResp, clk, srst); - -// Pass through AXI signals where possible. -assign mAxiAWAddrReg = sAxiAWAddrReg; -assign mAxiWDataReg = sAxiWDataReg; -assign mAxiWStrbReg = sAxiWStrbReg; -assign mAxiARAddrReg = sAxiARAddrReg; - -// Implement combinatorial logic for selecting AXI transaction mode. -always @(axiState_q, regReq_q, regWriteEn_q, regAddr_q, regWData_q, regWStrb_q, - sAxiAWPending, sAxiAWAddrReg, sAxiWPending, sAxiWDataReg, sAxiWStrbReg, - sAxiBBlocked, sAxiARPending, sAxiARAddrReg, sAxiRBlocked, mAxiRPending, - mAxiRDataReg, mAxiRRespReg, mAxiAWBlocked, mAxiWBlocked, mAxiBPending, - mAxiARBlocked, mAxiBRespReg, regAck, regRData, regAddrTop) -begin - - // Preserve current state by default. - axiState_d = axiState_q; - regReq_d = regReq_q; - regWriteEn_d = regWriteEn_q; - regAddr_d = regAddr_q; - regWData_d = regWData_q; - regWStrb_d = regWStrb_q; - - // Set default read assignment to register inputs with AXI 'OKAY' response. - sAxiRPush = 1'b0; - sAxiRDataReg = regRData; - sAxiRRespReg = 2'b0; - - // Set default write status assigment to AXI 'OKAY' response. - sAxiBPush = 1'b0; - sAxiBRespReg = 2'b0; - - // Disable AXI register clear strobes by default. - sAxiAWClear = 1'b0; - sAxiWClear = 1'b0; - sAxiARClear = 1'b0; - mAxiBClear = 1'b0; - mAxiRClear = 1'b0; - - // Disable AXI master push strobes by default. - mAxiAWPush = 1'b0; - mAxiWPush = 1'b0; - mAxiARPush = 1'b0; - - // Implement state machine. - case (axiState_q) - - // In the idle state, wait until the AXI write or read address inputs are - // ready. Writes are prioritised over reads. - // verilator lint_off CMPCONST - Idle : - begin - if (sAxiAWPending) - begin - if (sAxiAWAddrReg <= regAddrTop) - axiState_d = RegWriteStart; - else - axiState_d = AxiWriteStart; - end - else if (sAxiARPending) - begin - if (sAxiARAddrReg <= regAddrTop) - axiState_d = RegReadStart; - else - axiState_d = AxiReadStart; - end - end - // verilator lint_on CMPCONST - - // Initiate read transactions on the local register interface. - RegReadStart : - begin - if (~sAxiRBlocked) - begin - axiState_d = RegReadActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b0; - regAddr_d = sAxiARAddrReg [RegAddrWidth-1:0]; - end - end - - // Process active read requests. - RegReadActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiRPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Initiate write transactions to the local register interface. - RegWriteStart : - begin - if (sAxiWPending & ~sAxiBBlocked) - begin - axiState_d = RegWriteActive; - regReq_d = 1'b1; - regWriteEn_d = 1'b1; - regAddr_d = sAxiAWAddrReg [RegAddrWidth-1:0]; - regWData_d = sAxiWDataReg; - regWStrb_d = sAxiWStrbReg; - end - end - - // Process active write requests. - RegWriteActive : - begin - if (regAck) - begin - axiState_d = Idle; - regReq_d = 1'b0; - regWriteEn_d = 1'b0; - sAxiBPush = 1'b1; - sAxiAWClear = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Initiate read transaction on the AXI master side. - AxiReadStart : - begin - if (~mAxiARBlocked) - begin - axiState_d = AxiReadActive; - mAxiARPush = 1'b1; - sAxiARClear = 1'b1; - end - end - - // Complete read transaction from the AXI master side. - AxiReadActive : - begin - sAxiRDataReg = mAxiRDataReg; - sAxiRRespReg = mAxiRRespReg; - if (mAxiRPending & ~sAxiRBlocked) - begin - axiState_d = Idle; - sAxiRPush = 1'b1; - mAxiRClear = 1'b1; - end - end - - // Initiate write transaction on the AXI master side. - AxiWriteStart : - begin - if (~mAxiAWBlocked) - begin - axiState_d = AxiWriteData; - mAxiAWPush = 1'b1; - sAxiAWClear = 1'b1; - end - end - - // Forward write data to the AXI master side. - AxiWriteData : - begin - if (sAxiWPending & ~mAxiWBlocked) - begin - axiState_d = AxiWriteActive; - mAxiWPush = 1'b1; - sAxiWClear = 1'b1; - end - end - - // Complete write transaction from the AXI master side. - AxiWriteActive : - begin - sAxiBRespReg = mAxiBRespReg; - if (mAxiBPending & ~sAxiBBlocked) - begin - axiState_d = Idle; - sAxiBPush = 1'b1; - mAxiBClear = 1'b1; - end - end - - // Map unknown states to Idle. - default : - begin - axiState_d = Idle; - end - endcase -end - -// Implement sequential logic for AXI transaction state machine. -always @(posedge clk) -begin - if (srst) - begin - axiState_q <= Idle; - regReq_q <= 1'b0; - regWriteEn_q <= 1'b0; - for (i = 0; i < RegAddrWidth; i = i + 1) - regAddr_q [i] <= 1'b0; - regWData_q <= 32'b0; - regWStrb_q <= 4'b0; - end - else - begin - axiState_q <= axiState_d; - regReq_q <= regReq_d; - regWriteEn_q <= regWriteEn_d; - regAddr_q <= regAddr_d; - regWData_q <= regWData_d; - regWStrb_q <= regWStrb_d; - end -end - -assign regReq = regReq_q; -assign regWriteEn = regWriteEn_q; -assign regAddr = regAddr_q; -assign regWData = regWData_q; -assign regWStrb = regWStrb_q; - -endmodule - -// -// Provides common implementation of single AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x1 - (axiValid, axiReady, axiDataIn, dataPending, dataClear, dataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth-1:0] axiDataIn; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth-1:0] dataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataClear_q; -reg axiReady_q; -reg [DataWidth-1:0] axiDataIn_q; - -integer i; - -// Implements a single AXI input register. -always @(posedge clk) -begin - if (srst | dataClear) - begin - dataClear_q <= 1'b1; - axiReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - axiDataIn_q [i] <= 1'b0; - end - else if (dataClear_q) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b1; - end - else if (axiReady_q & axiValid) - begin - dataClear_q <= 1'b0; - axiReady_q <= 1'b0; - axiDataIn_q <= axiDataIn; - end -end - -assign axiReady = axiReady_q; -assign dataPending = ~(dataClear_q | axiReady_q); -assign dataOut = axiDataIn_q; - -endmodule - -// -// Provides common implementation of dual AXI data input register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_inreg_x2 - (axiValid, axiReady, axiDataIn1, axiDataIn2, dataPending, dataClear, - dataOut1, dataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the AXI bus input signals. -input axiValid; -output axiReady; -input [DataWidth1-1:0] axiDataIn1; -input [DataWidth2-1:0] axiDataIn2; - -// Specifies the data register output signals. -output dataPending; -input dataClear; -output [DataWidth1-1:0] dataOut1; -output [DataWidth2-1:0] dataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] dataOut; - -// Instantiate the single input register module. -sda_kernel_ctrl_reg_sel_axi_inreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (axiValid, axiReady, {axiDataIn2, axiDataIn1}, dataPending, dataClear, - dataOut, clk, srst); - -assign dataOut1 = dataOut [DataWidth1-1:0]; -assign dataOut2 = dataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - -// -// Provides common implementation of single AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x1 - (dataPush, dataBlocked, dataIn, axiValid, axiReady, axiDataOut, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the register data width. -parameter DataWidth = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth-1:0] dataIn; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth-1:0] axiDataOut; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies internal registers. -reg dataReady_q; -reg [DataWidth-1:0] dataReg_q; - -integer i; - -// Implements a single AXI output register. -always @(posedge clk) -begin - if (srst) - begin - dataReady_q <= 1'b0; - for (i = 0; i < DataWidth; i = i + 1) - dataReg_q [i] <= 1'b0; - end - else if (dataReady_q & axiReady) - begin - dataReady_q <= 1'b0; - end - else if (dataPush) - begin - dataReady_q <= 1'b1; - dataReg_q <= dataIn; - end -end - -assign dataBlocked = dataReady_q; -assign axiValid = dataReady_q; -assign axiDataOut = dataReg_q; - -endmodule - -// -// Provides common implementation of dual AXI data output register. -// -// verilator lint_off DECLFILENAME -module sda_kernel_ctrl_reg_sel_axi_outreg_x2 - (dataPush, dataBlocked, dataIn1, dataIn2, axiValid, axiReady, axiDataOut1, - axiDataOut2, clk, srst); -// verilator lint_on DECLFILENAME - -// Specify the first register data width. -parameter DataWidth1 = 16; - -// Specify the second register data width. -parameter DataWidth2 = 16; - -// Specifies the data register interface signals. -input dataPush; -output dataBlocked; -input [DataWidth1-1:0] dataIn1; -input [DataWidth2-1:0] dataIn2; - -// Specifies the AXI bus output signals. -output axiValid; -input axiReady; -output [DataWidth1-1:0] axiDataOut1; -output [DataWidth2-1:0] axiDataOut2; - -// Specifies the system level signals. -input clk; -input srst; - -// Specifies the concatenated data vectors. -wire [DataWidth1+DataWidth2-1:0] axiDataOut; - -// Instantiate the single output register module. -sda_kernel_ctrl_reg_sel_axi_outreg_x1 #(DataWidth1+DataWidth2) axiDataReg_u - (dataPush, dataBlocked, {dataIn2, dataIn1}, axiValid, axiReady, - axiDataOut, clk, srst); - -assign axiDataOut1 = axiDataOut [DataWidth1-1:0]; -assign axiDataOut2 = axiDataOut [DataWidth1+DataWidth2-1:DataWidth1]; - -endmodule - diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v deleted file mode 100644 index 925d6d3..0000000 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_reset_handler.v +++ /dev/null @@ -1,259 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Implementation of SDAccel kernel reset handler. It provides support for -// managing kernel resets under control of the external 'go' and 'done' control -// signals. -// - -`timescale 1ns/1ps - -module sda_kernel_reset_handler - (regGoValid, regGoHoldoff, regDoneValid, regDoneStop, kernelGoValid, - kernelGoHoldoff, kernelDoneValid, kernelDoneStop, sysRstReq, wrapperReset, - kernelReset, clk); - -// Specifies the reset counter size. The kernel reset line will be asserted for -// the time it takes the counter to wrap. -parameter ResetCountSize = 5; - -// Specifies the length of the reset pipeline, which allows the synthesis tools -// to build a reset tree if required by using register duplication. -parameter ResetPipeLength = 8; - -// Derives the reset counter limit. -parameter ResetCountLimit = (1 << ResetCountSize) - 1; - -// Specify the reset controller state space. -parameter [2:0] - ResetIdle = 0, - ResetTimeout = 1, - KernelStarting = 2, - KernelRunning = 3, - KernelExited = 4; - -// Upstream register interface signals. -input regGoValid; -output regGoHoldoff; -output regDoneValid; -input regDoneStop; - -// Kernel control go output signals. -output kernelGoValid; -input kernelGoHoldoff; -input kernelDoneValid; -output kernelDoneStop; - -// Specifies the system reset request signal and generated resets. -input sysRstReq; -output wrapperReset; -output kernelReset; - -// Specifies the clock input. There is no standard synchronous reset. -input clk; - -// Reset control state machine signals. -reg [2:0] resetState_d; -reg [ResetCountSize-1:0] resetCount_d; -reg kernelReset_d; -reg regGoHoldoff_d; -reg regDoneValid_d; -reg kernelGoValid_d; -reg kernelDoneStop_d; - -reg [2:0] resetState_q; -reg [ResetCountSize-1:0] resetCount_q; -reg kernelReset_q; -reg regGoHoldoff_q; -reg regDoneValid_q; -reg kernelGoValid_q; -reg kernelDoneStop_q; - -// Implements a register with an explicit initialisation value, which will have -// the effect of forcing a reset cycle immediately after loading the FPGA -// netlist. Only works with devices that support bitstream initalisation. -reg resetHandlerEnabled_q = 1'b0; -reg wrapperReset_q; - -// Specifies the reset pipeline signals. -reg [ResetPipeLength-1:0] wrapperResetPipe_q; -reg [ResetPipeLength-1:0] kernelResetPipe_q; - -// Miscellaneous signals. -integer i; - -// Initiate automatic reset on FPGA bitstream load. -always @(posedge clk) -begin - if (sysRstReq | ~resetHandlerEnabled_q) - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b1; - end - else - begin - resetHandlerEnabled_q <= 1'b1; - wrapperReset_q <= 1'b0; - end -end - -// Implement combinatorial logic for reset control state machine. -always @(resetState_q, resetCount_q, kernelReset_q, regGoHoldoff_q, regDoneValid_q, - kernelGoValid_q, kernelDoneStop_q, regGoValid, regDoneStop, kernelGoHoldoff, - kernelDoneValid) -begin - - // Hold current state by default. - resetState_d = resetState_q; - resetCount_d = resetCount_q; - kernelReset_d = kernelReset_q; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - - // Implement state machine. - case (resetState_q) - - // Hold the reset state for the required timeout. - ResetTimeout : - begin - if (resetCount_q == ResetCountLimit [ResetCountSize-1:0]) - begin - resetState_d = ResetIdle; - end - resetCount_d = resetCount_q + 1; - end - - // Wait for the kernel to accept the go signal. - KernelStarting : - begin - if (kernelGoValid_q & ~kernelGoHoldoff) - begin - resetState_d = KernelRunning; - end - else - begin - kernelGoValid_d = 1'b1; - end - end - - // In the kernel runnning state, wait for the 'done' response. - KernelRunning : - begin - if (kernelDoneValid & ~kernelDoneStop_q) - begin - resetState_d = KernelExited; - end - else - begin - kernelDoneStop_d = 1'b0; - end - end - - // In the kernel exited state, notify the control registers and place the - // kernel in reset until the next go request is received. - KernelExited : - begin - if (regDoneValid_q & ~regDoneStop) - begin - resetState_d = ResetTimeout; - kernelReset_d = 1'b1; - end - else - begin - regDoneValid_d = 1'b1; - end - end - - // In the reset idle state, wait for a go request from the register block - // before releasing the kernel reset. - ResetIdle : - begin - if (regGoValid & ~regGoHoldoff_q) - begin - resetState_d = KernelStarting; - kernelReset_d = 1'b0; - end - else - begin - regGoHoldoff_d = 1'b0; - end - end - - // Treat the unreachable default state as a hard reset. This prevents the - // Xilinx tools from generating dangling nets if the state encoding is - // automatically converted to one-hot. - default: - begin - resetState_d = ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_d [i] = 1'b0; - kernelReset_d = 1'b1; - regGoHoldoff_d = 1'b1; - regDoneValid_d = 1'b0; - kernelGoValid_d = 1'b0; - kernelDoneStop_d = 1'b1; - end - endcase - -end - -// Implement sequential logic for reset control state machine. -always @(posedge clk) -begin - if (wrapperReset_q) - begin - resetState_q <= ResetTimeout; - for (i = 0; i < ResetCountSize; i = i + 1) - resetCount_q [i] <= 1'b0; - kernelReset_q <= 1'b1; - regGoHoldoff_q <= 1'b1; - regDoneValid_q <= 1'b0; - kernelGoValid_q <= 1'b0; - kernelDoneStop_q <= 1'b1; - end - else - begin - resetState_q <= resetState_d; - resetCount_q <= resetCount_d; - kernelReset_q <= kernelReset_d; - regGoHoldoff_q <= regGoHoldoff_d; - regDoneValid_q <= regDoneValid_d; - kernelGoValid_q <= kernelGoValid_d; - kernelDoneStop_q <= kernelDoneStop_d; - end -end - -assign regGoHoldoff = regGoHoldoff_q; -assign regDoneValid = regDoneValid_q; -assign kernelGoValid = kernelGoValid_q; -assign kernelDoneStop = kernelDoneStop_q; - -// Implement reset output pipelines. -always @(posedge clk) -begin - if (wrapperReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - wrapperResetPipe_q [i] <= 1'b1; - else - wrapperResetPipe_q <= { 1'b0, wrapperResetPipe_q [ResetPipeLength-1:1] }; -end - -always @(posedge clk) -begin - if (kernelReset_q) - for (i = 0; i < ResetPipeLength; i = i + 1) - kernelResetPipe_q [i] <= 1'b1; - else - kernelResetPipe_q <= { 1'b0, kernelResetPipe_q [ResetPipeLength-1:1] }; -end - -assign wrapperReset = wrapperResetPipe_q [0]; -assign kernelReset = kernelResetPipe_q [0]; - -endmodule diff --git a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v b/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v deleted file mode 100644 index 95054a0..0000000 --- a/memcopy/vendor/github.com/ReconfigureIO/sdaccel/verilog/sda_kernel_wrapper_gmem.v +++ /dev/null @@ -1,390 +0,0 @@ -// -// (c) 2017 ReconfigureIO -// -// -// - -// -// Provides the common wrapper code around an existing 'action' block so that it -// can be used in the context of an SDAccel 'kernel' block. This variant -// supports the complete set of control registers at AXI slave offset zero which -// are used to map the SDAccel run/status programming interface to the action -// block run/done SELF handshake lines. This wrapper implements a single AXI -// master interface which can access the shared global memory area on the FPGA -// card. -// - -`timescale 1ns/1ps - -// Can be redefined on the synthesis command line. -`ifndef AXI_SLAVE_ADDR_WIDTH -`define AXI_SLAVE_ADDR_WIDTH 16 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ADDR_WIDTH -`define AXI_MASTER_ADDR_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_DATA_WIDTH -`define AXI_MASTER_DATA_WIDTH 64 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_ID_WIDTH -`define AXI_MASTER_ID_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_USER_WIDTH -`define AXI_MASTER_USER_WIDTH 1 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_MASTER_CACHE_MASK -`define AXI_MASTER_CACHE_MASK 4'b0011 -`endif - -// Can be redefined on the synthesis command line. -`ifndef AXI_PARAM_MEM_ADDR_WIDTH -`define AXI_PARAM_MEM_ADDR_WIDTH 12 -`endif - -// Module name to be substituted in post-synthesis netlist. -module sda_kernel_wrapper_gmem - (s_axi_control_AWADDR, s_axi_control_AWVALID, s_axi_control_AWREADY, - s_axi_control_WDATA, s_axi_control_WSTRB, s_axi_control_WVALID, - s_axi_control_WREADY, s_axi_control_BRESP, s_axi_control_BVALID, - s_axi_control_BREADY, s_axi_control_ARADDR, s_axi_control_ARVALID, - s_axi_control_ARREADY, s_axi_control_RDATA, s_axi_control_RRESP, - s_axi_control_RVALID, s_axi_control_RREADY, m_axi_gmem_AWADDR, - m_axi_gmem_AWLEN, m_axi_gmem_AWSIZE, m_axi_gmem_AWBURST, m_axi_gmem_AWLOCK, - m_axi_gmem_AWREGION, m_axi_gmem_AWCACHE, m_axi_gmem_AWPROT, m_axi_gmem_AWQOS, - m_axi_gmem_AWID, m_axi_gmem_AWUSER, m_axi_gmem_AWVALID, m_axi_gmem_AWREADY, - m_axi_gmem_WDATA, m_axi_gmem_WSTRB, m_axi_gmem_WLAST, m_axi_gmem_WID, - m_axi_gmem_WUSER, m_axi_gmem_WVALID, m_axi_gmem_WREADY, m_axi_gmem_BRESP, - m_axi_gmem_BID, m_axi_gmem_BUSER, m_axi_gmem_BVALID, m_axi_gmem_BREADY, - m_axi_gmem_ARADDR, m_axi_gmem_ARLEN, m_axi_gmem_ARSIZE, m_axi_gmem_ARBURST, - m_axi_gmem_ARLOCK, m_axi_gmem_ARREGION, m_axi_gmem_ARCACHE, m_axi_gmem_ARPROT, - m_axi_gmem_ARQOS, m_axi_gmem_ARID, m_axi_gmem_ARUSER, m_axi_gmem_ARVALID, - m_axi_gmem_ARREADY, m_axi_gmem_RDATA, m_axi_gmem_RRESP, m_axi_gmem_RLAST, - m_axi_gmem_RID, m_axi_gmem_RUSER, m_axi_gmem_RVALID, m_axi_gmem_RREADY, - ap_clk, ap_rst_n, interrupt); - -// Specifies the AXI slave write address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_AWADDR; -input s_axi_control_AWVALID; -output s_axi_control_AWREADY; - -// Specifies the AXI slave write data signals. -input [31:0] s_axi_control_WDATA; -input [3:0] s_axi_control_WSTRB; -input s_axi_control_WVALID; -output s_axi_control_WREADY; - -// Specifies the AXI slave write response signals. -output [1:0] s_axi_control_BRESP; -output s_axi_control_BVALID; -input s_axi_control_BREADY; - -// Specifies the AXI slave read address signals. -input [`AXI_SLAVE_ADDR_WIDTH-1:0] s_axi_control_ARADDR; -input s_axi_control_ARVALID; -output s_axi_control_ARREADY; - -// Specifies the AXI slave read data signals. -output [31:0] s_axi_control_RDATA; -output [1:0] s_axi_control_RRESP; -output s_axi_control_RVALID; -input s_axi_control_RREADY; - -// Specifies the AXI master write address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_AWADDR; -output [7:0] m_axi_gmem_AWLEN; -output [2:0] m_axi_gmem_AWSIZE; -output [1:0] m_axi_gmem_AWBURST; -output [1:0] m_axi_gmem_AWLOCK; -output [3:0] m_axi_gmem_AWCACHE; -output [2:0] m_axi_gmem_AWPROT; -output [3:0] m_axi_gmem_AWQOS; -output [3:0] m_axi_gmem_AWREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_AWID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_AWUSER; -output m_axi_gmem_AWVALID; -input m_axi_gmem_AWREADY; - -// Specifies the AXI master write data signals. -output [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_WDATA; -output [`AXI_MASTER_DATA_WIDTH/8-1:0] m_axi_gmem_WSTRB; -output m_axi_gmem_WLAST; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_WID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_WUSER; -output m_axi_gmem_WVALID; -input m_axi_gmem_WREADY; - -// Specifies the AXI master write response signals. -input [1:0] m_axi_gmem_BRESP; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_BID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_BUSER; -input m_axi_gmem_BVALID; -output m_axi_gmem_BREADY; - -// Specifies the AXI master read address signals. -output [`AXI_MASTER_ADDR_WIDTH-1:0] m_axi_gmem_ARADDR; -output [7:0] m_axi_gmem_ARLEN; -output [2:0] m_axi_gmem_ARSIZE; -output [1:0] m_axi_gmem_ARBURST; -output [1:0] m_axi_gmem_ARLOCK; -output [3:0] m_axi_gmem_ARCACHE; -output [2:0] m_axi_gmem_ARPROT; -output [3:0] m_axi_gmem_ARQOS; -output [3:0] m_axi_gmem_ARREGION; -output [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_ARID; -output [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_ARUSER; -output m_axi_gmem_ARVALID; -input m_axi_gmem_ARREADY; - -// Specifies the AXI master read data signals. -input [`AXI_MASTER_DATA_WIDTH-1:0] m_axi_gmem_RDATA; -input [1:0] m_axi_gmem_RRESP; -input m_axi_gmem_RLAST; -input [`AXI_MASTER_ID_WIDTH-1:0] m_axi_gmem_RID; -input [`AXI_MASTER_USER_WIDTH-1:0] m_axi_gmem_RUSER; -input m_axi_gmem_RVALID; -output m_axi_gmem_RREADY; - -// Specifies the system level I/O signals. -input ap_clk; -input ap_rst_n; - -// verilator lint_off SYMRSVDWORD -output interrupt; -// verilator lint_on SYMRSVDWORD - -// Reset management signals. -wire reg_go_valid; -wire reg_go_holdoff; -wire reg_done_valid; -wire reg_done_stop; -wire kernel_reset; -wire wrapper_reset; - -// AXI control interface master write address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_AWADDR; -wire [3:0] m_axi_control_AWCACHE; -wire [2:0] m_axi_control_AWPROT; -wire m_axi_control_AWVALID; -wire m_axi_control_AWREADY; - -// AXI control interface master write data signals. -wire [31:0] m_axi_control_WDATA; -wire [3:0] m_axi_control_WSTRB; -wire m_axi_control_WVALID; -wire m_axi_control_WREADY; - -// AXI control interface master write response signals. -wire [1:0] m_axi_control_BRESP; -wire m_axi_control_BVALID; -wire m_axi_control_BREADY; - -// AXI control interface master read address signals. -wire [`AXI_SLAVE_ADDR_WIDTH-1:0] m_axi_control_ARADDR; -wire [3:0] m_axi_control_ARCACHE; -wire [2:0] m_axi_control_ARPROT; -wire m_axi_control_ARVALID; -wire m_axi_control_ARREADY; - -// AXI control interface master read data signals. -wire [31:0] m_axi_control_RDATA; -wire [1:0] m_axi_control_RRESP; -wire m_axi_control_RVALID; -wire m_axi_control_RREADY; - -// AXI master interface intermediate signals. -wire [3:0] m_axi_gmem_local_ARCACHE; -wire [3:0] m_axi_gmem_local_AWCACHE; - -// Wrapper control register interface signals. -wire reg_req; -wire reg_ack; -wire reg_ack_0; -wire reg_ack_1; -wire reg_write_en; -wire [`AXI_PARAM_MEM_ADDR_WIDTH-1:0] reg_addr; -wire [31:0] reg_wdata; -wire [3:0] reg_wstrb; -wire [31:0] reg_rdata; -wire [31:0] reg_rdata_0; -wire [31:0] reg_rdata_1; - -// Kernel interface parameter access signals. -wire param_addr_valid; -wire [31:0] param_addr; -wire param_addr_stop; -wire param_data_valid; -wire [31:0] param_data; -wire param_data_stop; - -// Action control signals. -wire go_0Ready; -wire go_0Stop; -wire done_0Ready; -wire done_0Stop; - -// Miscellaneous signals. -wire [31:0] zeros = 32'b0; -wire [31:0] m_axi_control_ext_AWADDR; -wire [31:0] m_axi_control_ext_ARADDR; - -// Tie off unused control interface signals. -assign m_axi_control_AWCACHE = 4'b0000; -assign m_axi_control_AWPROT = 3'b010; -assign m_axi_control_ARCACHE = 4'b0000; -assign m_axi_control_ARPROT = 3'b010; - -// Tie off upper bit of the lock signals for AXI3 backward compatibility. -assign m_axi_gmem_AWLOCK[1] = 1'b0; -assign m_axi_gmem_ARLOCK[1] = 1'b0; - -// Tie off unused WID signal -`ifndef AXI_MASTER_HAS_WID -assign m_axi_gmem_WID = `AXI_MASTER_ID_WIDTH'd0; -`endif - -// Apply cache mask to restrict memory access modes if required. The default -// is to restrict accesses to device mode only, as required by the AWS shell. -assign m_axi_gmem_ARCACHE = m_axi_gmem_local_ARCACHE & `AXI_MASTER_CACHE_MASK; -assign m_axi_gmem_AWCACHE = m_axi_gmem_local_AWCACHE & `AXI_MASTER_CACHE_MASK; - -// Instantiate the reset controller. -sda_kernel_reset_handler resetHandler_u - (reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, go_0Ready, - go_0Stop, done_0Ready, done_0Stop, ~ap_rst_n, wrapper_reset, kernel_reset, - ap_clk); - -// Instantiate the AXI slave register selection component. -sda_kernel_ctrl_reg_sel #(`AXI_SLAVE_ADDR_WIDTH, `AXI_PARAM_MEM_ADDR_WIDTH, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlRegSel_u - (s_axi_control_AWVALID, s_axi_control_AWREADY, s_axi_control_AWADDR, - s_axi_control_WVALID, s_axi_control_WREADY, s_axi_control_WDATA, - s_axi_control_WSTRB, s_axi_control_BVALID, s_axi_control_BREADY, - s_axi_control_BRESP, s_axi_control_ARVALID, s_axi_control_ARREADY, - s_axi_control_ARADDR, s_axi_control_RVALID, s_axi_control_RREADY, - s_axi_control_RDATA, s_axi_control_RRESP, m_axi_control_AWVALID, - m_axi_control_AWREADY, m_axi_control_AWADDR, m_axi_control_WVALID, - m_axi_control_WREADY, m_axi_control_WDATA, m_axi_control_WSTRB, - m_axi_control_BVALID, m_axi_control_BREADY, m_axi_control_BRESP, - m_axi_control_ARVALID, m_axi_control_ARREADY, m_axi_control_ARADDR, - m_axi_control_RVALID, m_axi_control_RREADY, m_axi_control_RDATA, - m_axi_control_RRESP, reg_req, reg_ack, reg_write_en, reg_addr, reg_wdata, - reg_wstrb, reg_rdata, ap_clk, wrapper_reset); - -// Instantiate the kernel control registers at slave address offset 0. -sda_kernel_ctrl_reg #(`AXI_PARAM_MEM_ADDR_WIDTH, 63) kernelCtrlReg_u - (reg_req, reg_ack_0, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_0, - reg_go_valid, reg_go_holdoff, reg_done_valid, reg_done_stop, interrupt, ap_clk, - wrapper_reset); - -// Instantiate the kernel parameter memory. -sda_kernel_ctrl_param #(`AXI_PARAM_MEM_ADDR_WIDTH, 64, - (1 << `AXI_PARAM_MEM_ADDR_WIDTH)-1) kernelCtrlParam_u - (reg_req, reg_ack_1, reg_write_en, reg_addr, reg_wdata, reg_wstrb, reg_rdata_1, - param_addr_valid, param_addr, param_addr_stop, param_data_valid, param_data, - param_data_stop, ap_clk, wrapper_reset); - -assign reg_ack = reg_ack_0 | reg_ack_1; -assign reg_rdata = reg_rdata_0 | reg_rdata_1 | zeros; - -// Extend the slave address bus widths to the standard 32 bit value for the -// action logic core. -assign m_axi_control_ext_AWADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_AWADDR}; -assign m_axi_control_ext_ARADDR = - {zeros [31:`AXI_SLAVE_ADDR_WIDTH], m_axi_control_ARADDR}; - -// Instantiate the simple generated action logic core. -teak__action__top__gmem kernelActionTop_u ( - .go_0Ready (go_0Ready), - .go_0Stop (go_0Stop), - .done_0Ready (done_0Ready), - .done_0Stop (done_0Stop), - .s_axi_araddr (m_axi_control_ext_ARADDR), - .s_axi_arcache (m_axi_control_ARCACHE), - .s_axi_arprot (m_axi_control_ARPROT), - .s_axi_arvalid (m_axi_control_ARVALID), - .s_axi_arready (m_axi_control_ARREADY), - .s_axi_rdata (m_axi_control_RDATA), - .s_axi_rresp (m_axi_control_RRESP), - .s_axi_rvalid (m_axi_control_RVALID), - .s_axi_rready (m_axi_control_RREADY), - .s_axi_awaddr (m_axi_control_ext_AWADDR), - .s_axi_awcache (m_axi_control_AWCACHE), - .s_axi_awprot (m_axi_control_AWPROT), - .s_axi_awvalid (m_axi_control_AWVALID), - .s_axi_awready (m_axi_control_AWREADY), - .s_axi_wdata (m_axi_control_WDATA), - .s_axi_wstrb (m_axi_control_WSTRB), - .s_axi_wvalid (m_axi_control_WVALID), - .s_axi_wready (m_axi_control_WREADY), - .s_axi_bresp (m_axi_control_BRESP), - .s_axi_bvalid (m_axi_control_BVALID), - .s_axi_bready (m_axi_control_BREADY), - .m_axi_gmem_awaddr (m_axi_gmem_AWADDR), - .m_axi_gmem_awlen (m_axi_gmem_AWLEN), - .m_axi_gmem_awsize (m_axi_gmem_AWSIZE), - .m_axi_gmem_awburst (m_axi_gmem_AWBURST), - .m_axi_gmem_awlock (m_axi_gmem_AWLOCK[0]), - .m_axi_gmem_awcache (m_axi_gmem_local_AWCACHE), - .m_axi_gmem_awprot (m_axi_gmem_AWPROT), - .m_axi_gmem_awqos (m_axi_gmem_AWQOS), - .m_axi_gmem_awregion (m_axi_gmem_AWREGION), - .m_axi_gmem_awid (m_axi_gmem_AWID), - .m_axi_gmem_awuser (m_axi_gmem_AWUSER), - .m_axi_gmem_awvalid (m_axi_gmem_AWVALID), - .m_axi_gmem_awready (m_axi_gmem_AWREADY), - .m_axi_gmem_wdata (m_axi_gmem_WDATA), - .m_axi_gmem_wstrb (m_axi_gmem_WSTRB), - .m_axi_gmem_wlast (m_axi_gmem_WLAST), -`ifdef AXI_MASTER_HAS_WID - .m_axi_gmem_wid (m_axi_gmem_WID), -`endif - .m_axi_gmem_wuser (m_axi_gmem_WUSER), - .m_axi_gmem_wvalid (m_axi_gmem_WVALID), - .m_axi_gmem_wready (m_axi_gmem_WREADY), - .m_axi_gmem_bresp (m_axi_gmem_BRESP), - .m_axi_gmem_bid (m_axi_gmem_BID), - .m_axi_gmem_buser (m_axi_gmem_BUSER), - .m_axi_gmem_bvalid (m_axi_gmem_BVALID), - .m_axi_gmem_bready (m_axi_gmem_BREADY), - .m_axi_gmem_araddr (m_axi_gmem_ARADDR), - .m_axi_gmem_arlen (m_axi_gmem_ARLEN), - .m_axi_gmem_arsize (m_axi_gmem_ARSIZE), - .m_axi_gmem_arburst (m_axi_gmem_ARBURST), - .m_axi_gmem_arlock (m_axi_gmem_ARLOCK[0]), - .m_axi_gmem_arcache (m_axi_gmem_local_ARCACHE), - .m_axi_gmem_arprot (m_axi_gmem_ARPROT), - .m_axi_gmem_arqos (m_axi_gmem_ARQOS), - .m_axi_gmem_arregion (m_axi_gmem_ARREGION), - .m_axi_gmem_arid (m_axi_gmem_ARID), - .m_axi_gmem_aruser (m_axi_gmem_ARUSER), - .m_axi_gmem_arvalid (m_axi_gmem_ARVALID), - .m_axi_gmem_arready (m_axi_gmem_ARREADY), - .m_axi_gmem_rdata (m_axi_gmem_RDATA), - .m_axi_gmem_rresp (m_axi_gmem_RRESP), - .m_axi_gmem_rlast (m_axi_gmem_RLAST), - .m_axi_gmem_rid (m_axi_gmem_RID), - .m_axi_gmem_ruser (m_axi_gmem_RUSER), - .m_axi_gmem_rvalid (m_axi_gmem_RVALID), - .m_axi_gmem_rready (m_axi_gmem_RREADY), - .paramaddr_0Ready (param_addr_valid), - .paramaddr_0Data (param_addr), - .paramaddr_0Stop (param_addr_stop), - .paramdata_0Ready (param_data_valid), - .paramdata_0Data (param_data), - .paramdata_0Stop (param_data_stop), - .clk (ap_clk), - .reset (kernel_reset) -); - -endmodule diff --git a/scripts/files/glide.lock b/scripts/files/glide.lock deleted file mode 100644 index 3058cab..0000000 --- a/scripts/files/glide.lock +++ /dev/null @@ -1,11 +0,0 @@ -hash: 8ad028198587ad691804c667772b773def3ca9fdfbae1fd132c5aaa5aa81ae2e -updated: 2018-02-12T11:48:34.247532906Z -imports: -- name: github.com/ReconfigureIO/sdaccel - version: e93e5713d49cc1354dcd1d35cfaef85ba151e0a3 - subpackages: - - axi/arbitrate - - axi/memory - - axi/protocol - - xcl -testImports: [] diff --git a/scripts/files/glide.yaml b/scripts/files/glide.yaml index d1ad514..bbdf15c 100644 --- a/scripts/files/glide.yaml +++ b/scripts/files/glide.yaml @@ -1,7 +1,7 @@ package: . import: - package: github.com/ReconfigureIO/sdaccel - version: v0.17.0 + version: ~v0.20.1 subpackages: - axi/arbitrate - axi/memory diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.gitignore b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.gitignore new file mode 100644 index 0000000..5be488b --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.gitignore @@ -0,0 +1,16 @@ +# Binaries for programs and plugins +*.exe +*.dll +*.so +*.dylib + +# Test binary, build with `go test -c` +*.test + +# Output of the go coverage tool, specifically when used with LiteIDE +*.out + +# Project-local glide cache, RE: https://github.com/Masterminds/glide/issues/736 +.glide/ + +dist/ \ No newline at end of file diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.travis.yml b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.travis.yml new file mode 100644 index 0000000..d7c3544 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/.travis.yml @@ -0,0 +1,36 @@ +language: go +go_import_path: github.com/ReconfigureIO/sdaccel + +go: + - 1.9 + +script: + - make test + - make all + +deploy: + provider: releases + api_key: + secure: "F3sXhpMX7iX2ubqi/Z42o1jmUozYjQdtOWDwJhWi00wDFIBXD8cmCC5+Cry+R2dOINkMTh69PbP7vYEkZvDEcBNUbVZpkieSXC46RGSzDFDH8wI2ACp24APWYprUBx4YPJsfNNmFnhdFgEQFBWIfUq1arI5w11oVlcNivnHnj0xAgVEBWFyRSy3h2uLqeVogem3EmRPAFdLJCplGzIZfiL7Bcnu5+yIUsSFGQJqWpDb0OWxfyZWqPQdt5kV3R8akhXHXuVkoAHgr3rtopoSG2wpxn/LJpenkmApNV0XpU7+DIm5x30XETjnSP9iZyrVnCxFF/gNDCTtnX73VF0mkIdlgnIlWEqZpr37MJtlaEFfrzbTICrkwDTqnf5TBzYE/AlCFOdO6vRnCtQ8oFBdUetAAFCpTLpQLTGThO/NijWZtn0EiVTsH+vP7kxnQrdgAD+m5lNKIdJuDWGnGsuKYUncTFE8akZErpe39XF5aqk5ikYCBhVVXFXiX8oAtNG060XkGdDXPb0mgpPJusodgm4Zp36O7PfElIcS1Z4mpMFoUqekJNoHM/oRP53MpQJY4xgakejFTpxgjejXkhUWNcOZbE3C9/lEF0d4VMVA0ip4Mb3q90vwqMgutq6GSgbkFlwf4Ck8Xf8Bcl4BLq2T7rhmJDRJKnnCs0UKWyT3cBBM=" + file: dist/fix + on: + repo: ReconfigureIO/sdaccel + # don't delete the artifacts from previous phases + skip_cleanup: true + # deploy when a new tag is pushed + on: + tags: true + +branches: + only: + # Pushes and PR to the master branch + - master + # IMPORTANT Ruby regex to match tags. Required, or travis won't trigger deploys when a new tag + # is pushed. This regex matches semantic versions like v1.2.3-rc4+2016.02.22 + - /^v\d+\.\d+\.\d+.*$/ + +notifications: + email: + on_success: never + slack: + secure: UJ5HojrImmU6s8HKe0iGJr4QZLCwAdZfttQMZvk2MpQH+riFV+garnxcC20XDWbnjPzWUXWjO61Jbm7nqpbY2ZuNQZgpff6fZuWA78nifUFCbXolN4ntXY1cAepeYGSr+nTm3uNolOfmWhHcxxcEvfdgKlqp09Ni0ORuVinMEqk3nWS4npyo8J2keqk7IzKUlyQP+KsvVsEFRR7BNmfciH+JzhOIWujlLQzETtpYBayls1p+hhpTs5qbJCNfJNMLGLMsq/Ah/JN6XYqA78fXcmuyn6lSXeqKaOGzCTAiFmC5F0rvJC/6KJDVRiGFGLomwEduD00KktCUElBJoD4lgbNuC8cgkFsI8duzj0qiDnlUBIY27LhbIONp6F2lHojMrarD72CK0bTV0Fvire03A25NnvGi2uCOXJ5SVQbSM0eTbdTwQScnbD6GGQlHXzvLXF+CZIIeWjljwrsppaSyoSfngHM0Bxe3IT/mrlBGz+85Sc6yBhVyANWBI0JF8fBjGqUQ+CoAkWk0JqP5S5i3zc+mO8qWS8vVHpkTY3gDtu9+t1bQVWxZNHzY2v2ykpWUqnnTQtc4cMwmQnjzoZjiQjqyphy6x+26NcD+O35stnw3F40GLeW4pCVImDIRQ49cbJ2ow2VNkqa1NBOKgWai98yi1h6eesTvKJTLgytI6Lg= diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/CODE_OF_CONDUCT.md b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..a9279ee --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/CODE_OF_CONDUCT.md @@ -0,0 +1,46 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as contributors and maintainers pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level of experience, nationality, personal appearance, race, religion, or sexual identity and orientation. + +## Our Standards + +Examples of behavior that contributes to creating a positive environment include: + +* Using welcoming and inclusive language +* Being respectful of differing viewpoints and experiences +* Gracefully accepting constructive criticism +* Focusing on what is best for the community +* Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +* The use of sexualized language or imagery and unwelcome sexual attention or advances +* Trolling, insulting/derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or electronic address, without explicit permission +* Other conduct which could reasonably be considered inappropriate in a professional setting + +## Our Responsibilities + +Project maintainers are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. + +Project maintainers have the right and responsibility to remove, edit, or reject comments, commits, code, wiki edits, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any contributor for other behaviors that they deem inappropriate, threatening, offensive, or harmful. + +## Scope + +This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. Examples of representing a project or community include using an official project e-mail address, posting via an official social media account, or acting as an appointed representative at an online or offline event. Representation of a project may be further defined and clarified by project maintainers. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at josh.bohde@reconfigure.io. The project team will review and investigate all complaints, and will respond in a way that it deems appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, available at [http://contributor-covenant.org/version/1/4][version] + +[homepage]: http://contributor-covenant.org +[version]: http://contributor-covenant.org/version/1/4/ diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/LICENSE b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/LICENSE new file mode 100644 index 0000000..7cd5d5a --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2017, Reconfigure.io +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/Makefile b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/Makefile new file mode 100644 index 0000000..9370dac --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/Makefile @@ -0,0 +1,28 @@ +# variable definitions +NAME := sdaccel +VERSION := $(shell git describe --tags --always --dirty) +GOVERSION := $(shell go version) +BUILDTIME := $(shell date -u +"%Y-%m-%dT%H:%M:%SZ") +BUILDDATE := $(shell date -u +"%B %d, %Y") +BUILDER := $(shell echo "`git config user.name` <`git config user.email`>") +PKG_RELEASE ?= 1 +PROJECT_URL := "https://github.com/ReconfigureIO/$(NAME)" + +.PHONY: test all clean + +CMD_SOURCES := $(shell go list ./... | grep /cmd/) +TARGETS := $(patsubst github.com/ReconfigureIO/sdaccel/cmd/%,dist/%,$(CMD_SOURCES)) + +all: ${TARGETS} + +test: + go test -v $$(go list ./... | grep -v /vendor/ | grep -v /cmd/) + +dist: + mkdir -p dist + +dist/%: cmd/% | dist + go build -ldflags "$(LDFLAGS)" -o $@ github.com/ReconfigureIO/sdaccel/$< + +clean: + rm -rf dist diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/README.md b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/README.md new file mode 100644 index 0000000..baf6807 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/README.md @@ -0,0 +1,43 @@ +sdaccel +======= + +[![Build Status](https://travis-ci.org/ReconfigureIO/sdaccel.svg?branch=master)](https://travis-ci.org/ReconfigureIO/sdaccel) +[![Documentation](https://godoc.org/github.com/ReconfigureIO/sdaccel?status.svg)](http://godoc.org/github.com/ReconfigureIO/sdaccel) + +A library for interacting with SDAccel from Go + +Using in your kernels +--------------------- + +Reconfigure.io supports including vendor packages in your kernels. You can use your favorite Go dependency manager to add it to your kernel. We use [glide](https://github.com/Masterminds/glide) for our code. + +``` +$ glide create --non-interactive +[INFO] Generating a YAML configuration file and guessing the dependencies +[INFO] Attempting to import from other package managers (use --skip-import to skip) +[INFO] Scanning code to look for dependencies +[INFO] Writing configuration file (glide.yaml) +[INFO] You can now edit the glide.yaml file. Consider: +[INFO] --> Using versions and ranges. See https://glide.sh/docs/versions/ +[INFO] --> Adding additional metadata. See https://glide.sh/docs/glide.yaml/ +[INFO] --> Running the config-wizard command to improve the versions in your configuration +$ glide get github.com/ReconfigureIO/sdaccel +[INFO] Preparing to install 1 package. +[INFO] Attempting to get package github.com/ReconfigureIO/sdaccel +[INFO] --> Gathering release information for github.com/ReconfigureIO/sdaccel +[INFO] --> Adding github.com/ReconfigureIO/sdaccel to your configuration +[INFO] Downloading dependencies. Please wait... +[INFO] --> Fetching updates for github.com/ReconfigureIO/sdaccel +[INFO] Resolving imports +[INFO] Downloading dependencies. Please wait... +[INFO] Exporting resolved dependencies... +[INFO] --> Exporting github.com/ReconfigureIO/sdaccel +[INFO] Replacing existing vendor dependencies +``` + +Contributing +------------ + +Pull requests & issues are enthusiastically accepted! + +By participating in this project you agree to follow our [Code of Conduct](CODE_OF_CONDUCT.md). diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/arbitrate/axiarbitrate.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/arbitrate/axiarbitrate.go new file mode 100644 index 0000000..49319e0 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/arbitrate/axiarbitrate.go @@ -0,0 +1,428 @@ +// +// (c) 2017 ReconfigureIO +// +// +// + +// +// AXI protocol bus arbitration between multiple 'upstream' ports. This package +// specifies a set of goroutines which may be used to arbitrate between multiple +// upstream AXI 'server' ports and a single downstream 'client' port. The +// current implementation supports arbitration between 2, 3 or 4 upstream ports. +// TODO: Support arbitrary number of upstream ports on demand using the Go +// generate capability. +// + +/* +Package arbitrate provides reusable arbitrators for AXI transations. +*/ +package arbitrate + +import ( + "github.com/ReconfigureIO/sdaccel/axi/protocol" +) + +// +// Goroutine which implements AXI arbitration between two AXI write interfaces. +// +func WriteArbitrateX2( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + serverAddr0 <-chan protocol.Addr, + serverData0 <-chan protocol.WriteData, + serverResp0 chan<- protocol.WriteResp, + serverAddr1 <-chan protocol.Addr, + serverData1 <-chan protocol.WriteData, + serverResp1 chan<- protocol.WriteResp) { + + // Specify the input selection channels. + dataChanSelect := make(chan byte) + respChanSelect := make(chan byte) + + // Run write data channel handler. + go func() { + for { + var writeData protocol.WriteData + chanSelect := <-dataChanSelect + + // Terminate transfers on write data channel 'last' flag. + isLast := false + for !isLast { + switch chanSelect { + case 0: + writeData = <-serverData0 + default: + writeData = <-serverData1 + } + clientData <- writeData + isLast = writeData.Last + } + } + }() + + // Run response channel handler. + go func() { + for { + chanSelect := <-respChanSelect + writeResp := <-clientResp + switch chanSelect { + case 0: + serverResp0 <- writeResp + default: + serverResp1 <- writeResp + } + } + }() + + // Use intermediate variables for efficient implementation. + var writeAddr protocol.Addr + var dataChanId byte + for { + select { + case writeAddr = <-serverAddr0: + dataChanId = 0 + case writeAddr = <-serverAddr1: + dataChanId = 1 + } + clientAddr <- writeAddr + dataChanSelect <- dataChanId + respChanSelect <- dataChanId + } +} + +// +// Goroutine which implements AXI arbitration between three AXI write interfaces. +// +func WriteArbitrateX3( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + serverAddr0 <-chan protocol.Addr, + serverData0 <-chan protocol.WriteData, + serverResp0 chan<- protocol.WriteResp, + serverAddr1 <-chan protocol.Addr, + serverData1 <-chan protocol.WriteData, + serverResp1 chan<- protocol.WriteResp, + serverAddr2 <-chan protocol.Addr, + serverData2 <-chan protocol.WriteData, + serverResp2 chan<- protocol.WriteResp) { + + // Specify the input selection channels. + dataChanSelect := make(chan byte) + respChanSelect := make(chan byte) + + // Run write data channel handler. + go func() { + for { + var writeData protocol.WriteData + chanSelect := <-dataChanSelect + + // Terminate transfers on write data channel 'last' flag. + isLast := false + for !isLast { + switch chanSelect { + case 0: + writeData = <-serverData0 + case 1: + writeData = <-serverData1 + default: + writeData = <-serverData2 + } + clientData <- writeData + isLast = writeData.Last + } + } + }() + + // Run response channel handler. + go func() { + for { + chanSelect := <-respChanSelect + writeResp := <-clientResp + switch chanSelect { + case 0: + serverResp0 <- writeResp + case 1: + serverResp1 <- writeResp + default: + serverResp2 <- writeResp + } + } + }() + + // Use intermediate variables for efficient implementation. + var writeAddr protocol.Addr + var dataChanId byte + for { + select { + case writeAddr = <-serverAddr0: + dataChanId = 0 + case writeAddr = <-serverAddr1: + dataChanId = 1 + case writeAddr = <-serverAddr2: + dataChanId = 2 + } + clientAddr <- writeAddr + dataChanSelect <- dataChanId + respChanSelect <- dataChanId + } +} + +// +// Goroutine which implements AXI arbitration between four AXI write interfaces. +// +func WriteArbitrateX4( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + serverAddr0 <-chan protocol.Addr, + serverData0 <-chan protocol.WriteData, + serverResp0 chan<- protocol.WriteResp, + serverAddr1 <-chan protocol.Addr, + serverData1 <-chan protocol.WriteData, + serverResp1 chan<- protocol.WriteResp, + serverAddr2 <-chan protocol.Addr, + serverData2 <-chan protocol.WriteData, + serverResp2 chan<- protocol.WriteResp, + serverAddr3 <-chan protocol.Addr, + serverData3 <-chan protocol.WriteData, + serverResp3 chan<- protocol.WriteResp) { + + // Specify the input selection channels. + dataChanSelect := make(chan byte) + respChanSelect := make(chan byte) + + // Run write data channel handler. + go func() { + for { + var writeData protocol.WriteData + chanSelect := <-dataChanSelect + + // Terminate transfers on write data channel 'last' flag. + isLast := false + for !isLast { + switch chanSelect { + case 0: + writeData = <-serverData0 + case 1: + writeData = <-serverData1 + case 2: + writeData = <-serverData2 + default: + writeData = <-serverData3 + } + clientData <- writeData + isLast = writeData.Last + } + } + }() + + // Run response channel handler. + go func() { + for { + chanSelect := <-respChanSelect + writeResp := <-clientResp + switch chanSelect { + case 0: + serverResp0 <- writeResp + case 1: + serverResp1 <- writeResp + case 2: + serverResp2 <- writeResp + default: + serverResp3 <- writeResp + } + } + }() + + // Use intermediate variables for efficient implementation. + var writeAddr protocol.Addr + var dataChanId byte + for { + select { + case writeAddr = <-serverAddr0: + dataChanId = 0 + case writeAddr = <-serverAddr1: + dataChanId = 1 + case writeAddr = <-serverAddr2: + dataChanId = 2 + case writeAddr = <-serverAddr3: + dataChanId = 3 + } + clientAddr <- writeAddr + dataChanSelect <- dataChanId + respChanSelect <- dataChanId + } +} + +// +// Goroutine which implements AXI arbitration between two AXI read interfaces. +// +func ReadArbitrateX2( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + serverAddr0 <-chan protocol.Addr, + serverData0 chan<- protocol.ReadData, + serverAddr1 <-chan protocol.Addr, + serverData1 chan<- protocol.ReadData) { + + // Specify the input selection channel. + dataChanSelect := make(chan byte) + + // Run read data channel handler. + go func() { + for { + chanSelect := <-dataChanSelect + + // Terminate transfers on write data channel 'last' flag. + isLast := false + for !isLast { + readData := <-clientData + switch chanSelect { + case 0: + serverData0 <- readData + isLast = readData.Last + default: + serverData1 <- readData + isLast = readData.Last + } + } + } + }() + + // Use intermediate variables for efficient implementation. + var readAddr protocol.Addr + var dataChanId byte + for { + select { + case readAddr = <-serverAddr0: + dataChanId = 0 + case readAddr = <-serverAddr1: + dataChanId = 1 + } + clientAddr <- readAddr + dataChanSelect <- dataChanId + } +} + +// +// Goroutine which implements AXI arbitration between three AXI read interfaces. +// +func ReadArbitrateX3( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + serverAddr0 <-chan protocol.Addr, + serverData0 chan<- protocol.ReadData, + serverAddr1 <-chan protocol.Addr, + serverData1 chan<- protocol.ReadData, + serverAddr2 <-chan protocol.Addr, + serverData2 chan<- protocol.ReadData) { + + // Specify the input selection channel. + dataChanSelect := make(chan byte) + + // Run read data channel handler. + go func() { + for { + chanSelect := <-dataChanSelect + + // Terminate transfers on write data channel 'last' flag. + isLast := false + for !isLast { + readData := <-clientData + switch chanSelect { + case 0: + serverData0 <- readData + isLast = readData.Last + case 1: + serverData1 <- readData + isLast = readData.Last + default: + serverData2 <- readData + isLast = readData.Last + } + } + } + }() + + // Use intermediate variables for efficient implementation. + var readAddr protocol.Addr + var dataChanId byte + for { + select { + case readAddr = <-serverAddr0: + dataChanId = 0 + case readAddr = <-serverAddr1: + dataChanId = 1 + case readAddr = <-serverAddr2: + dataChanId = 2 + } + clientAddr <- readAddr + dataChanSelect <- dataChanId + } +} + +// +// Goroutine which implements AXI arbitration between four AXI read interfaces. +// +func ReadArbitrateX4( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + serverAddr0 <-chan protocol.Addr, + serverData0 chan<- protocol.ReadData, + serverAddr1 <-chan protocol.Addr, + serverData1 chan<- protocol.ReadData, + serverAddr2 <-chan protocol.Addr, + serverData2 chan<- protocol.ReadData, + serverAddr3 <-chan protocol.Addr, + serverData3 chan<- protocol.ReadData) { + + // Specify the input selection channel. + dataChanSelect := make(chan byte) + + // Run read data channel handler. + go func() { + for { + chanSelect := <-dataChanSelect + + // Terminate transfers on write data channel 'last' flag. + isLast := false + for !isLast { + readData := <-clientData + switch chanSelect { + case 0: + serverData0 <- readData + isLast = readData.Last + case 1: + serverData1 <- readData + isLast = readData.Last + case 2: + serverData2 <- readData + isLast = readData.Last + default: + serverData3 <- readData + isLast = readData.Last + } + } + } + }() + + // Use intermediate variables for efficient implementation. + var readAddr protocol.Addr + var dataChanId byte + for { + select { + case readAddr = <-serverAddr0: + dataChanId = 0 + case readAddr = <-serverAddr1: + dataChanId = 1 + case readAddr = <-serverAddr2: + dataChanId = 2 + case readAddr = <-serverAddr3: + dataChanId = 3 + } + clientAddr <- readAddr + dataChanSelect <- dataChanId + } +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/axi.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/axi.go new file mode 100644 index 0000000..0846386 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/axi.go @@ -0,0 +1 @@ +package axi diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/memory/aximemory.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/memory/aximemory.go new file mode 100644 index 0000000..b4c4f45 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/memory/aximemory.go @@ -0,0 +1,934 @@ +// +// (c) 2017 ReconfigureIO +// +// +// + +// +// AXI access interface to memory mapped RAM and I/O. This defines the memory +// access functions to support reading and writing of the various Go primitive +// types over the AXI bus. Note that in order to ensure the correct ordering of +// AXI channel requests and responses, each AXI client/server interface must +// only ever be accessed sequentially from within the same goroutine. A suitable +// memory arbitration component from the axi/protocol package will be required +// to support concurrent memory accesses. +// + +/* + +Package memory provides high level operations for working an AXI bus + +*/ +package memory + +import ( + "github.com/ReconfigureIO/sdaccel/axi/protocol" +) + +// +// Sets the maximum AXI burst length to use. +// +const maxAxiBurstSize = 64 + +// +// WriteUInt64 writes a single 64-bit unsigned data value to a word aligned +// address on the specified AXI memory bus, with the bottom three address bits +// being ignored. The status of the write transaction is returned as the boolean +// 'writeOk' flag. +// +func WriteUInt64( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeData uint64) bool { + + // Issue write request. + go func() { + clientAddr <- protocol.Addr{ + Addr: writeAddr &^ uintptr(0x7), + Size: [3]bool{true, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Perform full width 64-bit AXI write. + writeStrobe := [8]bool{ + true, true, true, true, true, true, true, true} + clientData <- protocol.WriteData{ + Data: writeData, + Strb: writeStrobe, + Last: true} + writeResp := <-clientResp + return !writeResp.Resp[1] +} + +// +// ReadUInt64 reads a single 64-bit unsigned data value from a word aligned +// address on the specified AXI memory bus, with the bottom three address bits +// being ignored. TODO: The status of the read transaction should be returned +// as the boolean 'readOk' flag. +// +func ReadUInt64( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr) uint64 { + + // Issue read request. + go func() { + clientAddr <- protocol.Addr{ + Addr: readAddr &^ uintptr(0x7), + Size: [3]bool{true, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Process read response. + readResp := <-clientData + // TODO: return !readResp.Resp[1], readResp.Data + return readResp.Data +} + +// +// WriteUInt32 writes a single 32-bit unsigned data value to a word aligned +// address on the specified AXI memory bus, with the bottom two address bits +// being ignored. The status of the write transaction is returned as the boolean +// 'writeOk' flag. +// +func WriteUInt32( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeData uint32) bool { + + // Issue write request. + go func() { + clientAddr <- protocol.Addr{ + Addr: writeAddr &^ uintptr(0x3), + Size: [3]bool{false, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Map write data to appropriate byte lanes. + var writeData64 uint64 + var writeStrobe [8]bool + switch byte(writeAddr) & 0x4 { + case 0x0: + writeData64 = uint64(writeData) + writeStrobe = [8]bool{ + true, true, true, true, false, false, false, false} + default: + writeData64 = uint64(writeData) << 32 + writeStrobe = [8]bool{ + false, false, false, false, true, true, true, true} + } + + // Perform partial width 64-bit AXI write. + clientData <- protocol.WriteData{ + Data: writeData64, + Strb: writeStrobe, + Last: true} + writeResp := <-clientResp + return !writeResp.Resp[1] +} + +// +// ReadUInt32 reads a single 32-bit unsigned data value from a word aligned +// address on the specified AXI memory bus, with the bottom two address bits +// being ignored. TODO: The status of the read transaction should be returned as +// the boolean 'readOk' flag. +// +func ReadUInt32( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr) uint32 { + + // Issue read request. + go func() { + clientAddr <- protocol.Addr{ + Addr: readAddr &^ uintptr(0x3), + Size: [3]bool{false, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Select data from 64-bit read result. + readResp := <-clientData + var readData uint32 + switch byte(readAddr) & 0x4 { + case 0x0: + readData = uint32(readResp.Data) + default: + readData = uint32(readResp.Data >> 32) + } + // TODO: return !readResp.Resp[1], readData + return readData +} + +// +// WriteUInt16 writes a single 16-bit unsigned data value to a word aligned +// address on the specified AXI memory bus, with the bottom address bit being +// ignored. The status of the write transaction is returned as the boolean +// 'writeOk' flag. +// +func WriteUInt16( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeData uint16) bool { + + // Issue write request. + go func() { + clientAddr <- protocol.Addr{ + Addr: writeAddr &^ uintptr(0x1), + Size: [3]bool{true, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Map write data to appropriate byte lanes. + var writeData64 uint64 + var writeStrobe [8]bool + switch byte(writeAddr) & 0x6 { + case 0x0: + writeData64 = uint64(writeData) + writeStrobe = [8]bool{ + true, true, false, false, false, false, false, false} + case 0x2: + writeData64 = uint64(writeData) << 16 + writeStrobe = [8]bool{ + false, false, true, true, false, false, false, false} + case 0x4: + writeData64 = uint64(writeData) << 32 + writeStrobe = [8]bool{ + false, false, false, false, true, true, false, false} + default: + writeData64 = uint64(writeData) << 48 + writeStrobe = [8]bool{ + false, false, false, false, false, false, true, true} + } + + // Perform partial width 64-bit AXI write. + clientData <- protocol.WriteData{ + Data: writeData64, + Strb: writeStrobe, + Last: true} + writeResp := <-clientResp + return !writeResp.Resp[1] +} + +// +// ReadUInt16 reads a single 16-bit unsigned data value from a word aligned +// address on the specified AXI memory bus, with the bottom address bit being +// ignored. TODO: The status of the read transaction should be returned as the +// boolean 'readOk' flag. +// +func ReadUInt16( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr) uint16 { + + // Issue read request. + go func() { + clientAddr <- protocol.Addr{ + Addr: readAddr &^ uintptr(0x1), + Size: [3]bool{true, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Select data from 64-bit read result. + readResp := <-clientData + var readData uint16 + switch byte(readAddr) & 0x6 { + case 0x0: + readData = uint16(readResp.Data) + case 0x2: + readData = uint16(readResp.Data >> 16) + case 0x4: + readData = uint16(readResp.Data >> 32) + default: + readData = uint16(readResp.Data >> 48) + } + // TODO: return !readResp.Resp[1], readData + return readData +} + +// +// WriteUInt8 writes a single 8-bit unsigned data value to the specified AXI +// memory bus. The status of the write transaction is returned as the boolean +// 'writeOk' flag. +// +func WriteUInt8( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeData uint8) bool { + + // Issue write request. + go func() { + clientAddr <- protocol.Addr{ + Addr: writeAddr, + Size: [3]bool{false, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Map write data to appropriate byte lanes. + var writeData64 uint64 + var writeStrobe [8]bool + switch byte(writeAddr) & 0x7 { + case 0x0: + writeData64 = uint64(writeData) + writeStrobe = [8]bool{ + true, false, false, false, false, false, false, false} + case 0x1: + writeData64 = uint64(writeData) << 8 + writeStrobe = [8]bool{ + false, true, false, false, false, false, false, false} + case 0x2: + writeData64 = uint64(writeData) << 16 + writeStrobe = [8]bool{ + false, false, true, false, false, false, false, false} + case 0x3: + writeData64 = uint64(writeData) << 24 + writeStrobe = [8]bool{ + false, false, false, true, false, false, false, false} + case 0x4: + writeData64 = uint64(writeData) << 32 + writeStrobe = [8]bool{ + false, false, false, false, true, false, false, false} + case 0x5: + writeData64 = uint64(writeData) << 40 + writeStrobe = [8]bool{ + false, false, false, false, false, true, false, false} + case 0x6: + writeData64 = uint64(writeData) << 48 + writeStrobe = [8]bool{ + false, false, false, false, false, false, true, false} + default: + writeData64 = uint64(writeData) << 56 + writeStrobe = [8]bool{ + false, false, false, false, false, false, false, true} + } + + // Perform partial width 64-bit AXI write. + clientData <- protocol.WriteData{ + Data: writeData64, + Strb: writeStrobe, + Last: true} + writeResp := <-clientResp + return !writeResp.Resp[1] +} + +// +// ReadUInt8 reads a single 8-bit unsigned data value to the specified AXI +// memory bus. TODO: The status of the write transaction should be returned as +// the boolean 'readOk' flag. +// +func ReadUInt8( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr) uint8 { + + // Issue read request. + go func() { + clientAddr <- protocol.Addr{ + Addr: readAddr, + Size: [3]bool{false, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Select data from 64-bit read result. + readResp := <-clientData + var readData uint8 + switch byte(readAddr) & 0x7 { + case 0x0: + readData = uint8(readResp.Data) + case 0x1: + readData = uint8(readResp.Data >> 8) + case 0x2: + readData = uint8(readResp.Data >> 16) + case 0x3: + readData = uint8(readResp.Data >> 24) + case 0x4: + readData = uint8(readResp.Data >> 32) + case 0x5: + readData = uint8(readResp.Data >> 40) + case 0x6: + readData = uint8(readResp.Data >> 48) + default: + readData = uint8(readResp.Data >> 56) + } + // TODO: return !readResp.Resp[1], readData + return readData +} + +// +// WriteBurstUInt64 writes an incrementing burst of 64-bit unsigned data values +// to a word aligned address on the specified AXI memory bus, with the bottom +// three address bits being ignored. The status of the write transaction is +// returned as the boolean 'burstOk' flag. +// +func WriteBurstUInt64( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeLength uint32, + writeDataChan <-chan uint64) bool { + + // Get aligned address. + alignedAddr := writeAddr &^ uintptr(0x7) + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for writeLength != 0 { + if writeLength < maxAxiBurstSize { + burstSize = byte(writeLength) + } + + // Perform full width 64-bit AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{true, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops over the required number of burst transactions. + for i := burstSize; i != 0; i-- { + writeData := <-writeDataChan + clientData <- protocol.WriteData{ + Data: writeData, + Strb: [8]bool{ + true, true, true, true, + true, true, true, true}, + Last: i == 1} + } + + // Update the burst counter and status flag. + writeResp := <-clientResp + burstOk = burstOk && !writeResp.Resp[1] + writeLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) << 3 + } + return burstOk +} + +// +// ReadBurstUInt64 reads an incrementing burst of 64-bit unsigned data values +// from a word aligned address on the specified AXI memory bus, with the bottom +// three address bits being ignored. The status of the read transaction is +// returned as the boolean 'burstOk' flag. +// +func ReadBurstUInt64( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr, + readLength uint32, + readDataChan chan<- uint64) bool { + + // Divide the transaction into burst sequences. + alignedAddr := readAddr &^ uintptr(0x7) + burstSize := byte(maxAxiBurstSize) + burstOk := true + for readLength != 0 { + if readLength < maxAxiBurstSize { + burstSize = byte(readLength) + } + + // Perform full width 64-bit AXI burst reads. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{true, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops until read data contains 'last' flag. Only the final + // burst status is of interest. + getNext := true + for getNext { + readData := <-clientData + readDataChan <- readData.Data + if readData.Last { + burstOk = burstOk && !readData.Resp[1] + } + getNext = !readData.Last + } + + // Update the burst counter and status flag. + readLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) << 3 + } + return burstOk +} + +// +// WriteBurstUInt32 writes an incrementing burst of 32-bit unsigned data values +// to a word aligned address on the specified AXI memory bus, with the bottom +// two address bits being ignored. The status of the write transaction is +// returned as the boolean 'burstOk' flag. +// +func WriteBurstUInt32( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeLength uint32, + writeDataChan <-chan uint32) bool { + + // Get aligned address and initial strobe phase. + alignedAddr := writeAddr &^ uintptr(0x3) + strobePhase := byte(writeAddr) + var writeData64 uint64 + var writeStrobe [8]bool + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for writeLength != 0 { + if writeLength < maxAxiBurstSize { + burstSize = byte(writeLength) + } + + // Perform partial width AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{false, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops over the required number of burst transactions. + for i := burstSize; i != 0; i-- { + writeData := <-writeDataChan + + // Map write data to appropriate byte lanes. + switch strobePhase & 0x4 { + case 0x0: + writeData64 = uint64(writeData) + writeStrobe = [8]bool{ + true, true, true, true, false, false, false, false} + default: + writeData64 = uint64(writeData) << 32 + writeStrobe = [8]bool{ + false, false, false, false, true, true, true, true} + } + + // Perform partial width 64-bit AXI write. + clientData <- protocol.WriteData{ + Data: writeData64, + Strb: writeStrobe, + Last: i == 1} + strobePhase += 0x4 + } + + // Update the burst counter and status flag. + writeResp := <-clientResp + burstOk = burstOk && !writeResp.Resp[1] + writeLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) << 2 + } + return burstOk +} + +// +// ReadBurstUInt32 reads an incrementing burst of 32-bit unsigned data values +// from a word aligned address on the specified AXI memory bus, with the bottom +// two address bits being ignored. The status of the read transaction is +// returned as the boolean 'burstOk' flag. +// +func ReadBurstUInt32( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr, + readLength uint32, + readDataChan chan<- uint32) bool { + + // Get aligned address and initial read phase. + alignedAddr := readAddr &^ uintptr(0x3) + readPhase := byte(readAddr) + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for readLength != 0 { + if readLength < maxAxiBurstSize { + burstSize = byte(readLength) + } + + // Perform partial width AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{false, true, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops until read data contains 'last' flag. Only the final + // burst status is of interest. + getNext := true + for getNext { + readData := <-clientData + var dataVal uint32 + switch readPhase & 0x4 { + case 0x0: + dataVal = uint32(readData.Data) + default: + dataVal = uint32(readData.Data >> 32) + } + readDataChan <- dataVal + if readData.Last { + burstOk = burstOk && !readData.Resp[1] + } + readPhase += 0x4 + getNext = !readData.Last + } + + // Update the burst counter and status flag. + readLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) << 2 + } + return burstOk +} + +// +// WriteBurstUInt16 writes an incrementing burst of 16-bit unsigned data values +// to a word aligned address on the specified AXI memory bus, with the bottom +// address bit being ignored. The status of the write transaction is returned +// as the boolean 'burstOk' flag. +// +func WriteBurstUInt16( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeLength uint32, + writeDataChan <-chan uint16) bool { + + // Get aligned address and initial strobe phase. + alignedAddr := writeAddr &^ uintptr(0x1) + strobePhase := byte(writeAddr) + var writeData64 uint64 + var writeStrobe [8]bool + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for writeLength != 0 { + if writeLength < maxAxiBurstSize { + burstSize = byte(writeLength) + } + + // Perform partial width AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{true, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops over the required number of burst transactions. + for i := burstSize; i != 0; i-- { + writeData := <-writeDataChan + + // Map write data to appropriate byte lanes. + switch strobePhase & 0x6 { + case 0x0: + writeData64 = uint64(writeData) + writeStrobe = [8]bool{ + true, true, false, false, false, false, false, false} + case 0x2: + writeData64 = uint64(writeData) << 16 + writeStrobe = [8]bool{ + false, false, true, true, false, false, false, false} + case 0x4: + writeData64 = uint64(writeData) << 32 + writeStrobe = [8]bool{ + false, false, false, false, true, true, false, false} + default: + writeData64 = uint64(writeData) << 48 + writeStrobe = [8]bool{ + false, false, false, false, false, false, true, true} + } + + // Perform partial width 64-bit AXI write. + clientData <- protocol.WriteData{ + Data: writeData64, + Strb: writeStrobe, + Last: i == 1} + strobePhase += 0x2 + } + + // Update the burst counter and status flag. + writeResp := <-clientResp + burstOk = burstOk && !writeResp.Resp[1] + writeLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) << 1 + } + return burstOk +} + +// +// ReadBurstUInt16 reads an incrementing burst of 16-bit unsigned data values +// from a word aligned address on the specified AXI memory bus, with the bottom +// address bit being ignored. The status of the read transaction is returned as +// the boolean 'burstOk' flag. +// +func ReadBurstUInt16( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr, + readLength uint32, + readDataChan chan<- uint16) bool { + + // Get aligned address and initial read phase. + alignedAddr := readAddr &^ uintptr(0x1) + readPhase := byte(readAddr) + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for readLength != 0 { + if readLength < maxAxiBurstSize { + burstSize = byte(readLength) + } + + // Perform partial width AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{true, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops until read data contains 'last' flag. Only the final + // burst status is of interest. + getNext := true + for getNext { + readData := <-clientData + switch readPhase & 0x6 { + case 0x0: + readDataChan <- uint16(readData.Data) + case 0x2: + readDataChan <- uint16(readData.Data >> 16) + case 0x4: + readDataChan <- uint16(readData.Data >> 32) + default: + readDataChan <- uint16(readData.Data >> 48) + } + if readData.Last { + burstOk = burstOk && !readData.Resp[1] + } + readPhase += 0x2 + getNext = !readData.Last + } + + // Update the burst counter and status flag. + readLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) << 1 + } + return burstOk +} + +// +// WriteBurstUInt8 writes an incrementing burst of 8-bit unsigned data values +// on the specified AXI memory bus. The status of the write transaction is +// returned as the boolean 'burstOk' flag. +// +func WriteBurstUInt8( + clientAddr chan<- protocol.Addr, + clientData chan<- protocol.WriteData, + clientResp <-chan protocol.WriteResp, + bufferedAccess bool, + writeAddr uintptr, + writeLength uint32, + writeDataChan <-chan uint8) bool { + + // Get aligned address and initial strobe phase. + alignedAddr := writeAddr + strobePhase := byte(writeAddr) + var writeData64 uint64 + var writeStrobe [8]bool + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for writeLength != 0 { + if writeLength < maxAxiBurstSize { + burstSize = byte(writeLength) + } + + // Perform partial width AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{false, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops over the required number of burst transactions. + for i := burstSize; i != 0; i-- { + writeData := <-writeDataChan + + // Map write data to appropriate byte lanes. + switch strobePhase & 0x7 { + case 0x0: + writeData64 = uint64(writeData) + writeStrobe = [8]bool{ + true, false, false, false, false, false, false, false} + case 0x1: + writeData64 = uint64(writeData) << 8 + writeStrobe = [8]bool{ + false, true, false, false, false, false, false, false} + case 0x2: + writeData64 = uint64(writeData) << 16 + writeStrobe = [8]bool{ + false, false, true, false, false, false, false, false} + case 0x3: + writeData64 = uint64(writeData) << 24 + writeStrobe = [8]bool{ + false, false, false, true, false, false, false, false} + case 0x4: + writeData64 = uint64(writeData) << 32 + writeStrobe = [8]bool{ + false, false, false, false, true, false, false, false} + case 0x5: + writeData64 = uint64(writeData) << 40 + writeStrobe = [8]bool{ + false, false, false, false, false, true, false, false} + case 0x6: + writeData64 = uint64(writeData) << 48 + writeStrobe = [8]bool{ + false, false, false, false, false, false, true, false} + default: + writeData64 = uint64(writeData) << 56 + writeStrobe = [8]bool{ + false, false, false, false, false, false, false, true} + } + + // Perform partial width 64-bit AXI write. + clientData <- protocol.WriteData{ + Data: writeData64, + Strb: writeStrobe, + Last: i == 1} + strobePhase += 0x1 + } + + // Update the burst counter and status flag. + writeResp := <-clientResp + burstOk = burstOk && !writeResp.Resp[1] + writeLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) + } + return burstOk +} + +// +// ReadBurstUInt8 reads an incrementing burst of 8-bit unsigned data values +// from a word aligned address on the specified AXI memory bus, with the bottom +// address bit being ignored. The status of the read transaction is returned as +// the boolean 'burstOk' flag. +// +func ReadBurstUInt8( + clientAddr chan<- protocol.Addr, + clientData <-chan protocol.ReadData, + bufferedAccess bool, + readAddr uintptr, + readLength uint32, + readDataChan chan<- uint8) bool { + + // Get aligned address and initial read phase. + alignedAddr := readAddr + readPhase := byte(readAddr) + + // Divide the transaction into burst sequences. + burstSize := byte(maxAxiBurstSize) + burstOk := true + for readLength != 0 { + if readLength < maxAxiBurstSize { + burstSize = byte(readLength) + } + + // Perform partial width AXI burst writes. + go func() { + clientAddr <- protocol.Addr{ + Addr: alignedAddr, + Len: burstSize - 1, + Size: [3]bool{false, false, false}, + Burst: [2]bool{true, false}, + Cache: [4]bool{bufferedAccess, true, false, false}} + }() + + // Loops until read data contains 'last' flag. Only the final + // burst status is of interest. + getNext := true + for getNext { + readData := <-clientData + switch readPhase & 0x7 { + case 0x0: + readDataChan <- uint8(readData.Data) + case 0x1: + readDataChan <- uint8(readData.Data >> 8) + case 0x2: + readDataChan <- uint8(readData.Data >> 16) + case 0x3: + readDataChan <- uint8(readData.Data >> 24) + case 0x4: + readDataChan <- uint8(readData.Data >> 32) + case 0x5: + readDataChan <- uint8(readData.Data >> 40) + case 0x6: + readDataChan <- uint8(readData.Data >> 48) + default: + readDataChan <- uint8(readData.Data >> 56) + } + if readData.Last { + burstOk = burstOk && !readData.Resp[1] + } + readPhase += 0x1 + getNext = !readData.Last + } + + // Update the burst counter and status flag. + readLength -= uint32(burstSize) + alignedAddr += uintptr(burstSize) + } + return burstOk +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/protocol/axiprotocol.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/protocol/axiprotocol.go new file mode 100644 index 0000000..4330de9 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/axi/protocol/axiprotocol.go @@ -0,0 +1,98 @@ +// +// (c) 2017 ReconfigureIO +// +// +// + +// +// AXI protocol interface to memory mapped RAM and I/O. This defines the data +// types to be used on the AXI write address (AXI_AW), write data (AXI_W), +// write status response (AXI_B), read address (AXI_RA) and read data (AXI_R) +// channels. The protocol package also includes goroutines for disabling unused +// AXI inferface ports. The data bus width is fixed at 64 bits, which +// corresponds to the largest Go primitive data types. +// + +/* + +Package protocol provides low level primitives for working the AXI4 protocol + +*/ +package protocol + +// +// Type Addr specifies AXI memory address channel fields. +// +type Addr struct { + Id bool + Addr uintptr + Len byte + Size [3]bool + Burst [2]bool + Lock bool + Cache [4]bool + Prot [3]bool + Region [4]bool + Qos [4]bool + User bool +} + +// +// Type ReadData specifies AXI memory read data channel fields. +// +type ReadData struct { + Id bool + Data uint64 + Resp [2]bool + Last bool + User bool +} + +// +// Type WriteData specifies AXI memory write data channel fields. +// +type WriteData struct { + Data uint64 + Strb [8]bool + Last bool + User bool +} + +// +// Type WriteResp specifies AXI memory write response channel fields. +// +type WriteResp struct { + Id bool + Resp [2]bool + User bool +} + +// +// WriteDisable will disable AXI bus write transactions. Should be run once for each +// unused AXI write interface. This will block the calling goroutine. +// +func WriteDisable( + clientAddr chan<- Addr, + clientData chan<- WriteData, + clientResp <-chan WriteResp) { + + clientAddr <- Addr{} + clientData <- WriteData{Last: true} + for { + <-clientResp + } +} + +// +// ReadDisable will disable AXI bus read transactions. Should be run once for +// each unused AXI read interface. This will block the calling goroutine. +// +func ReadDisable( + clientAddr chan<- Addr, + clientData <-chan ReadData) { + + clientAddr <- Addr{} + for { + <-clientData + } +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/doc.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/doc.go new file mode 100644 index 0000000..a0c1510 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/doc.go @@ -0,0 +1,37 @@ +// // Copyright 2017 Reconfigure.io. +// Copyright 2011 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +/* +Fix finds Go programs for Reconfigure.io that use old APIs and rewrites them to use +newer ones. After you update to a new Go release, fix helps make +the necessary changes to your programs. + +Usage: + fix [-r name,...] [path ...] + +Without an explicit path, fix reads standard input and writes the +result to standard output. + +If the named path is a file, fix rewrites the named files in place. +If the named path is a directory, fix rewrites all .go files in that +directory tree. When fix rewrites a file, it prints a line to standard +error giving the name of the file and the rewrite applied. + +If the -diff flag is set, no files are rewritten. Instead fix prints +the differences a rewrite would introduce. + +The -r flag restricts the set of rewrites considered to those in the +named list. By default fix considers all known rewrites. Fix's +rewrites are idempotent, so that it is safe to apply fix to updated +or partially updated code even without using the -r flag. + +Fix prints the full list of fixes it can apply in its help output; +to see them, run go tool fix -help. + +Fix does not make backup copies of the files that it edits. +Instead, use a version control system's ``diff'' functionality to inspect +the changes that fix makes before committing them. +*/ +package main diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/fix.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/fix.go new file mode 100644 index 0000000..ab16a21 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/fix.go @@ -0,0 +1,848 @@ +// Copyright 2011 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import ( + "fmt" + "go/ast" + "go/parser" + "go/token" + "os" + "path" + "reflect" + "strconv" + "strings" +) + +type fix struct { + name string + date string // date that fix was introduced, in YYYY-MM-DD format + f func(*ast.File) bool + desc string +} + +// main runs sort.Sort(byName(fixes)) before printing list of fixes. +type byName []fix + +func (f byName) Len() int { return len(f) } +func (f byName) Swap(i, j int) { f[i], f[j] = f[j], f[i] } +func (f byName) Less(i, j int) bool { return f[i].name < f[j].name } + +// main runs sort.Sort(byDate(fixes)) before applying fixes. +type byDate []fix + +func (f byDate) Len() int { return len(f) } +func (f byDate) Swap(i, j int) { f[i], f[j] = f[j], f[i] } +func (f byDate) Less(i, j int) bool { return f[i].date < f[j].date } + +var fixes []fix + +func register(f fix) { + fixes = append(fixes, f) +} + +// walk traverses the AST x, calling visit(y) for each node y in the tree but +// also with a pointer to each ast.Expr, ast.Stmt, and *ast.BlockStmt, +// in a bottom-up traversal. +func walk(x interface{}, visit func(interface{})) { + walkBeforeAfter(x, nop, visit) +} + +func nop(interface{}) {} + +// walkBeforeAfter is like walk but calls before(x) before traversing +// x's children and after(x) afterward. +func walkBeforeAfter(x interface{}, before, after func(interface{})) { + before(x) + + switch n := x.(type) { + default: + panic(fmt.Errorf("unexpected type %T in walkBeforeAfter", x)) + + case nil: + + // pointers to interfaces + case *ast.Decl: + walkBeforeAfter(*n, before, after) + case *ast.Expr: + walkBeforeAfter(*n, before, after) + case *ast.Spec: + walkBeforeAfter(*n, before, after) + case *ast.Stmt: + walkBeforeAfter(*n, before, after) + + // pointers to struct pointers + case **ast.BlockStmt: + walkBeforeAfter(*n, before, after) + case **ast.CallExpr: + walkBeforeAfter(*n, before, after) + case **ast.FieldList: + walkBeforeAfter(*n, before, after) + case **ast.FuncType: + walkBeforeAfter(*n, before, after) + case **ast.Ident: + walkBeforeAfter(*n, before, after) + case **ast.BasicLit: + walkBeforeAfter(*n, before, after) + + // pointers to slices + case *[]ast.Decl: + walkBeforeAfter(*n, before, after) + case *[]ast.Expr: + walkBeforeAfter(*n, before, after) + case *[]*ast.File: + walkBeforeAfter(*n, before, after) + case *[]*ast.Ident: + walkBeforeAfter(*n, before, after) + case *[]ast.Spec: + walkBeforeAfter(*n, before, after) + case *[]ast.Stmt: + walkBeforeAfter(*n, before, after) + + // These are ordered and grouped to match ../../go/ast/ast.go + case *ast.Field: + walkBeforeAfter(&n.Names, before, after) + walkBeforeAfter(&n.Type, before, after) + walkBeforeAfter(&n.Tag, before, after) + case *ast.FieldList: + for _, field := range n.List { + walkBeforeAfter(field, before, after) + } + case *ast.BadExpr: + case *ast.Ident: + case *ast.Ellipsis: + walkBeforeAfter(&n.Elt, before, after) + case *ast.BasicLit: + case *ast.FuncLit: + walkBeforeAfter(&n.Type, before, after) + walkBeforeAfter(&n.Body, before, after) + case *ast.CompositeLit: + walkBeforeAfter(&n.Type, before, after) + walkBeforeAfter(&n.Elts, before, after) + case *ast.ParenExpr: + walkBeforeAfter(&n.X, before, after) + case *ast.SelectorExpr: + walkBeforeAfter(&n.X, before, after) + case *ast.IndexExpr: + walkBeforeAfter(&n.X, before, after) + walkBeforeAfter(&n.Index, before, after) + case *ast.SliceExpr: + walkBeforeAfter(&n.X, before, after) + if n.Low != nil { + walkBeforeAfter(&n.Low, before, after) + } + if n.High != nil { + walkBeforeAfter(&n.High, before, after) + } + case *ast.TypeAssertExpr: + walkBeforeAfter(&n.X, before, after) + walkBeforeAfter(&n.Type, before, after) + case *ast.CallExpr: + walkBeforeAfter(&n.Fun, before, after) + walkBeforeAfter(&n.Args, before, after) + case *ast.StarExpr: + walkBeforeAfter(&n.X, before, after) + case *ast.UnaryExpr: + walkBeforeAfter(&n.X, before, after) + case *ast.BinaryExpr: + walkBeforeAfter(&n.X, before, after) + walkBeforeAfter(&n.Y, before, after) + case *ast.KeyValueExpr: + walkBeforeAfter(&n.Key, before, after) + walkBeforeAfter(&n.Value, before, after) + + case *ast.ArrayType: + walkBeforeAfter(&n.Len, before, after) + walkBeforeAfter(&n.Elt, before, after) + case *ast.StructType: + walkBeforeAfter(&n.Fields, before, after) + case *ast.FuncType: + walkBeforeAfter(&n.Params, before, after) + if n.Results != nil { + walkBeforeAfter(&n.Results, before, after) + } + case *ast.InterfaceType: + walkBeforeAfter(&n.Methods, before, after) + case *ast.MapType: + walkBeforeAfter(&n.Key, before, after) + walkBeforeAfter(&n.Value, before, after) + case *ast.ChanType: + walkBeforeAfter(&n.Value, before, after) + + case *ast.BadStmt: + case *ast.DeclStmt: + walkBeforeAfter(&n.Decl, before, after) + case *ast.EmptyStmt: + case *ast.LabeledStmt: + walkBeforeAfter(&n.Stmt, before, after) + case *ast.ExprStmt: + walkBeforeAfter(&n.X, before, after) + case *ast.SendStmt: + walkBeforeAfter(&n.Chan, before, after) + walkBeforeAfter(&n.Value, before, after) + case *ast.IncDecStmt: + walkBeforeAfter(&n.X, before, after) + case *ast.AssignStmt: + walkBeforeAfter(&n.Lhs, before, after) + walkBeforeAfter(&n.Rhs, before, after) + case *ast.GoStmt: + walkBeforeAfter(&n.Call, before, after) + case *ast.DeferStmt: + walkBeforeAfter(&n.Call, before, after) + case *ast.ReturnStmt: + walkBeforeAfter(&n.Results, before, after) + case *ast.BranchStmt: + case *ast.BlockStmt: + walkBeforeAfter(&n.List, before, after) + case *ast.IfStmt: + walkBeforeAfter(&n.Init, before, after) + walkBeforeAfter(&n.Cond, before, after) + walkBeforeAfter(&n.Body, before, after) + walkBeforeAfter(&n.Else, before, after) + case *ast.CaseClause: + walkBeforeAfter(&n.List, before, after) + walkBeforeAfter(&n.Body, before, after) + case *ast.SwitchStmt: + walkBeforeAfter(&n.Init, before, after) + walkBeforeAfter(&n.Tag, before, after) + walkBeforeAfter(&n.Body, before, after) + case *ast.TypeSwitchStmt: + walkBeforeAfter(&n.Init, before, after) + walkBeforeAfter(&n.Assign, before, after) + walkBeforeAfter(&n.Body, before, after) + case *ast.CommClause: + walkBeforeAfter(&n.Comm, before, after) + walkBeforeAfter(&n.Body, before, after) + case *ast.SelectStmt: + walkBeforeAfter(&n.Body, before, after) + case *ast.ForStmt: + walkBeforeAfter(&n.Init, before, after) + walkBeforeAfter(&n.Cond, before, after) + walkBeforeAfter(&n.Post, before, after) + walkBeforeAfter(&n.Body, before, after) + case *ast.RangeStmt: + walkBeforeAfter(&n.Key, before, after) + walkBeforeAfter(&n.Value, before, after) + walkBeforeAfter(&n.X, before, after) + walkBeforeAfter(&n.Body, before, after) + + case *ast.ImportSpec: + case *ast.ValueSpec: + walkBeforeAfter(&n.Type, before, after) + walkBeforeAfter(&n.Values, before, after) + walkBeforeAfter(&n.Names, before, after) + case *ast.TypeSpec: + walkBeforeAfter(&n.Type, before, after) + + case *ast.BadDecl: + case *ast.GenDecl: + walkBeforeAfter(&n.Specs, before, after) + case *ast.FuncDecl: + if n.Recv != nil { + walkBeforeAfter(&n.Recv, before, after) + } + walkBeforeAfter(&n.Type, before, after) + if n.Body != nil { + walkBeforeAfter(&n.Body, before, after) + } + + case *ast.File: + walkBeforeAfter(&n.Decls, before, after) + + case *ast.Package: + walkBeforeAfter(&n.Files, before, after) + + case []*ast.File: + for i := range n { + walkBeforeAfter(&n[i], before, after) + } + case []ast.Decl: + for i := range n { + walkBeforeAfter(&n[i], before, after) + } + case []ast.Expr: + for i := range n { + walkBeforeAfter(&n[i], before, after) + } + case []*ast.Ident: + for i := range n { + walkBeforeAfter(&n[i], before, after) + } + case []ast.Stmt: + for i := range n { + walkBeforeAfter(&n[i], before, after) + } + case []ast.Spec: + for i := range n { + walkBeforeAfter(&n[i], before, after) + } + } + after(x) +} + +// imports reports whether f imports path. +func imports(f *ast.File, path string) bool { + return importSpec(f, path) != nil +} + +// importSpec returns the import spec if f imports path, +// or nil otherwise. +func importSpec(f *ast.File, path string) *ast.ImportSpec { + for _, s := range f.Imports { + if importPath(s) == path { + return s + } + } + return nil +} + +// importPath returns the unquoted import path of s, +// or "" if the path is not properly quoted. +func importPath(s *ast.ImportSpec) string { + t, err := strconv.Unquote(s.Path.Value) + if err == nil { + return t + } + return "" +} + +// declImports reports whether gen contains an import of path. +func declImports(gen *ast.GenDecl, path string) bool { + if gen.Tok != token.IMPORT { + return false + } + for _, spec := range gen.Specs { + impspec := spec.(*ast.ImportSpec) + if importPath(impspec) == path { + return true + } + } + return false +} + +// isPkgDot reports whether t is the expression "pkg.name" +// where pkg is an imported identifier. +func isPkgDot(t ast.Expr, pkg, name string) bool { + sel, ok := t.(*ast.SelectorExpr) + return ok && isTopName(sel.X, pkg) && sel.Sel.String() == name +} + +// isPtrPkgDot reports whether f is the expression "*pkg.name" +// where pkg is an imported identifier. +func isPtrPkgDot(t ast.Expr, pkg, name string) bool { + ptr, ok := t.(*ast.StarExpr) + return ok && isPkgDot(ptr.X, pkg, name) +} + +// isTopName reports whether n is a top-level unresolved identifier with the given name. +func isTopName(n ast.Expr, name string) bool { + id, ok := n.(*ast.Ident) + return ok && id.Name == name && id.Obj == nil +} + +// isName reports whether n is an identifier with the given name. +func isName(n ast.Expr, name string) bool { + id, ok := n.(*ast.Ident) + return ok && id.String() == name +} + +// isCall reports whether t is a call to pkg.name. +func isCall(t ast.Expr, pkg, name string) bool { + call, ok := t.(*ast.CallExpr) + return ok && isPkgDot(call.Fun, pkg, name) +} + +// If n is an *ast.Ident, isIdent returns it; otherwise isIdent returns nil. +func isIdent(n interface{}) *ast.Ident { + id, _ := n.(*ast.Ident) + return id +} + +// refersTo reports whether n is a reference to the same object as x. +func refersTo(n ast.Node, x *ast.Ident) bool { + id, ok := n.(*ast.Ident) + // The test of id.Name == x.Name handles top-level unresolved + // identifiers, which all have Obj == nil. + return ok && id.Obj == x.Obj && id.Name == x.Name +} + +// isBlank reports whether n is the blank identifier. +func isBlank(n ast.Expr) bool { + return isName(n, "_") +} + +// isEmptyString reports whether n is an empty string literal. +func isEmptyString(n ast.Expr) bool { + lit, ok := n.(*ast.BasicLit) + return ok && lit.Kind == token.STRING && len(lit.Value) == 2 +} + +func warn(pos token.Pos, msg string, args ...interface{}) { + if pos.IsValid() { + msg = "%s: " + msg + arg1 := []interface{}{fset.Position(pos).String()} + args = append(arg1, args...) + } + fmt.Fprintf(os.Stderr, msg+"\n", args...) +} + +// countUses returns the number of uses of the identifier x in scope. +func countUses(x *ast.Ident, scope []ast.Stmt) int { + count := 0 + ff := func(n interface{}) { + if n, ok := n.(ast.Node); ok && refersTo(n, x) { + count++ + } + } + for _, n := range scope { + walk(n, ff) + } + return count +} + +// rewriteUses replaces all uses of the identifier x and !x in scope +// with f(x.Pos()) and fnot(x.Pos()). +func rewriteUses(x *ast.Ident, f, fnot func(token.Pos) ast.Expr, scope []ast.Stmt) { + var lastF ast.Expr + ff := func(n interface{}) { + ptr, ok := n.(*ast.Expr) + if !ok { + return + } + nn := *ptr + + // The child node was just walked and possibly replaced. + // If it was replaced and this is a negation, replace with fnot(p). + not, ok := nn.(*ast.UnaryExpr) + if ok && not.Op == token.NOT && not.X == lastF { + *ptr = fnot(nn.Pos()) + return + } + if refersTo(nn, x) { + lastF = f(nn.Pos()) + *ptr = lastF + } + } + for _, n := range scope { + walk(n, ff) + } +} + +// assignsTo reports whether any of the code in scope assigns to or takes the address of x. +func assignsTo(x *ast.Ident, scope []ast.Stmt) bool { + assigned := false + ff := func(n interface{}) { + if assigned { + return + } + switch n := n.(type) { + case *ast.UnaryExpr: + // use of &x + if n.Op == token.AND && refersTo(n.X, x) { + assigned = true + return + } + case *ast.AssignStmt: + for _, l := range n.Lhs { + if refersTo(l, x) { + assigned = true + return + } + } + } + } + for _, n := range scope { + if assigned { + break + } + walk(n, ff) + } + return assigned +} + +// newPkgDot returns an ast.Expr referring to "pkg.name" at position pos. +func newPkgDot(pos token.Pos, pkg, name string) ast.Expr { + return &ast.SelectorExpr{ + X: &ast.Ident{ + NamePos: pos, + Name: pkg, + }, + Sel: &ast.Ident{ + NamePos: pos, + Name: name, + }, + } +} + +// renameTop renames all references to the top-level name old. +// It returns true if it makes any changes. +func renameTop(f *ast.File, old, new string) bool { + var fixed bool + + // Rename any conflicting imports + // (assuming package name is last element of path). + for _, s := range f.Imports { + if s.Name != nil { + if s.Name.Name == old { + s.Name.Name = new + fixed = true + } + } else { + _, thisName := path.Split(importPath(s)) + if thisName == old { + s.Name = ast.NewIdent(new) + fixed = true + } + } + } + + // Rename any top-level declarations. + for _, d := range f.Decls { + switch d := d.(type) { + case *ast.FuncDecl: + if d.Recv == nil && d.Name.Name == old { + d.Name.Name = new + d.Name.Obj.Name = new + fixed = true + } + case *ast.GenDecl: + for _, s := range d.Specs { + switch s := s.(type) { + case *ast.TypeSpec: + if s.Name.Name == old { + s.Name.Name = new + s.Name.Obj.Name = new + fixed = true + } + case *ast.ValueSpec: + for _, n := range s.Names { + if n.Name == old { + n.Name = new + n.Obj.Name = new + fixed = true + } + } + } + } + } + } + + // Rename top-level old to new, both unresolved names + // (probably defined in another file) and names that resolve + // to a declaration we renamed. + walk(f, func(n interface{}) { + id, ok := n.(*ast.Ident) + if ok && isTopName(id, old) { + id.Name = new + fixed = true + } + if ok && id.Obj != nil && id.Name == old && id.Obj.Name == new { + id.Name = id.Obj.Name + fixed = true + } + }) + + return fixed +} + +// matchLen returns the length of the longest prefix shared by x and y. +func matchLen(x, y string) int { + i := 0 + for i < len(x) && i < len(y) && x[i] == y[i] { + i++ + } + return i +} + +// addImport adds the import path to the file f, if absent. +func addImport(f *ast.File, ipath string) (added bool) { + if imports(f, ipath) { + return false + } + + // Determine name of import. + // Assume added imports follow convention of using last element. + _, name := path.Split(ipath) + + // Rename any conflicting top-level references from name to name_. + renameTop(f, name, name+"_") + + newImport := &ast.ImportSpec{ + Path: &ast.BasicLit{ + Kind: token.STRING, + Value: strconv.Quote(ipath), + }, + } + + // Find an import decl to add to. + var ( + bestMatch = -1 + lastImport = -1 + impDecl *ast.GenDecl + impIndex = -1 + ) + for i, decl := range f.Decls { + gen, ok := decl.(*ast.GenDecl) + if ok && gen.Tok == token.IMPORT { + lastImport = i + // Do not add to import "C", to avoid disrupting the + // association with its doc comment, breaking cgo. + if declImports(gen, "C") { + continue + } + + // Compute longest shared prefix with imports in this block. + for j, spec := range gen.Specs { + impspec := spec.(*ast.ImportSpec) + n := matchLen(importPath(impspec), ipath) + if n > bestMatch { + bestMatch = n + impDecl = gen + impIndex = j + } + } + } + } + + // If no import decl found, add one after the last import. + if impDecl == nil { + impDecl = &ast.GenDecl{ + Tok: token.IMPORT, + } + f.Decls = append(f.Decls, nil) + copy(f.Decls[lastImport+2:], f.Decls[lastImport+1:]) + f.Decls[lastImport+1] = impDecl + } + + // Ensure the import decl has parentheses, if needed. + if len(impDecl.Specs) > 0 && !impDecl.Lparen.IsValid() { + impDecl.Lparen = impDecl.Pos() + } + + insertAt := impIndex + 1 + if insertAt == 0 { + insertAt = len(impDecl.Specs) + } + impDecl.Specs = append(impDecl.Specs, nil) + copy(impDecl.Specs[insertAt+1:], impDecl.Specs[insertAt:]) + impDecl.Specs[insertAt] = newImport + if insertAt > 0 { + // Assign same position as the previous import, + // so that the sorter sees it as being in the same block. + prev := impDecl.Specs[insertAt-1] + newImport.Path.ValuePos = prev.Pos() + newImport.EndPos = prev.Pos() + } + + f.Imports = append(f.Imports, newImport) + return true +} + +// deleteImport deletes the import path from the file f, if present. +func deleteImport(f *ast.File, path string) (deleted bool) { + oldImport := importSpec(f, path) + + // Find the import node that imports path, if any. + for i, decl := range f.Decls { + gen, ok := decl.(*ast.GenDecl) + if !ok || gen.Tok != token.IMPORT { + continue + } + for j, spec := range gen.Specs { + impspec := spec.(*ast.ImportSpec) + if oldImport != impspec { + continue + } + + // We found an import spec that imports path. + // Delete it. + deleted = true + copy(gen.Specs[j:], gen.Specs[j+1:]) + gen.Specs = gen.Specs[:len(gen.Specs)-1] + + // If this was the last import spec in this decl, + // delete the decl, too. + if len(gen.Specs) == 0 { + copy(f.Decls[i:], f.Decls[i+1:]) + f.Decls = f.Decls[:len(f.Decls)-1] + } else if len(gen.Specs) == 1 { + gen.Lparen = token.NoPos // drop parens + } + if j > 0 { + // We deleted an entry but now there will be + // a blank line-sized hole where the import was. + // Close the hole by making the previous + // import appear to "end" where this one did. + gen.Specs[j-1].(*ast.ImportSpec).EndPos = impspec.End() + } + break + } + } + + // Delete it from f.Imports. + for i, imp := range f.Imports { + if imp == oldImport { + copy(f.Imports[i:], f.Imports[i+1:]) + f.Imports = f.Imports[:len(f.Imports)-1] + break + } + } + + return +} + +// rewriteImport rewrites any import of path oldPath to path newPath. +func rewriteImport(f *ast.File, oldPath, newPath string) (rewrote bool) { + for _, imp := range f.Imports { + if importPath(imp) == oldPath { + rewrote = true + // record old End, because the default is to compute + // it using the length of imp.Path.Value. + imp.EndPos = imp.End() + imp.Path.Value = strconv.Quote(newPath) + } + } + return +} + +func usesImport(f *ast.File, path string) (used bool) { + spec := importSpec(f, path) + if spec == nil { + return + } + + name := spec.Name.String() + switch name { + case "": + // If the package name is not explicitly specified, + // make an educated guess. This is not guaranteed to be correct. + lastSlash := strings.LastIndex(path, "/") + if lastSlash == -1 { + name = path + } else { + name = path[lastSlash+1:] + } + case "_", ".": + // Not sure if this import is used - err on the side of caution. + return true + } + + walk(f, func(n interface{}) { + sel, ok := n.(*ast.SelectorExpr) + if ok && isTopName(sel.X, name) { + used = true + } + }) + + return +} + +func expr(s string) ast.Expr { + x, err := parser.ParseExpr(s) + if err != nil { + panic("parsing " + s + ": " + err.Error()) + } + // Remove position information to avoid spurious newlines. + killPos(reflect.ValueOf(x)) + return x +} + +var posType = reflect.TypeOf(token.Pos(0)) + +func killPos(v reflect.Value) { + switch v.Kind() { + case reflect.Ptr, reflect.Interface: + if !v.IsNil() { + killPos(v.Elem()) + } + case reflect.Slice: + n := v.Len() + for i := 0; i < n; i++ { + killPos(v.Index(i)) + } + case reflect.Struct: + n := v.NumField() + for i := 0; i < n; i++ { + f := v.Field(i) + if f.Type() == posType { + f.SetInt(0) + continue + } + killPos(f) + } + } +} + +// A Rename describes a single renaming. +type rename struct { + OldImport string // only apply rename if this import is present + NewImport string // add this import during rewrite + Old string // old name: p.T or *p.T + New string // new name: p.T or *p.T +} + +func renameFix(tab []rename) func(*ast.File) bool { + return func(f *ast.File) bool { + return renameFixTab(f, tab) + } +} + +func parseName(s string) (ptr bool, pkg, nam string) { + i := strings.Index(s, ".") + if i < 0 { + panic("parseName: invalid name " + s) + } + if strings.HasPrefix(s, "*") { + ptr = true + s = s[1:] + i-- + } + pkg = s[:i] + nam = s[i+1:] + return +} + +func renameFixTab(f *ast.File, tab []rename) bool { + fixed := false + added := map[string]bool{} + check := map[string]bool{} + for _, t := range tab { + if !imports(f, t.OldImport) { + continue + } + optr, opkg, onam := parseName(t.Old) + walk(f, func(n interface{}) { + np, ok := n.(*ast.Expr) + if !ok { + return + } + x := *np + if optr { + p, ok := x.(*ast.StarExpr) + if !ok { + return + } + x = p.X + } + if !isPkgDot(x, opkg, onam) { + return + } + if t.NewImport != "" && !added[t.NewImport] { + addImport(f, t.NewImport) + added[t.NewImport] = true + } + *np = expr(t.New) + check[t.OldImport] = true + fixed = true + }) + } + + for ipath := range check { + if !usesImport(f, ipath) { + deleteImport(f, ipath) + } + } + return fixed +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/main.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/main.go new file mode 100644 index 0000000..8b62346 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/main.go @@ -0,0 +1,258 @@ +// Copyright 2011 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import ( + "bytes" + "flag" + "fmt" + "go/ast" + "go/format" + "go/parser" + "go/scanner" + "go/token" + "io/ioutil" + "os" + "os/exec" + "path/filepath" + "sort" + "strings" +) + +var ( + fset = token.NewFileSet() + exitCode = 0 +) + +var allowedRewrites = flag.String("r", "", + "restrict the rewrites to this comma-separated list") + +var forceRewrites = flag.String("force", "", + "force these fixes to run even if the code looks updated") + +var allowed, force map[string]bool + +var doDiff = flag.Bool("diff", false, "display diffs instead of rewriting files") + +// enable for debugging fix failures +const debug = false // display incorrectly reformatted source and exit + +func usage() { + fmt.Fprintf(os.Stderr, "usage: go tool fix [-diff] [-r fixname,...] [-force fixname,...] [path ...]\n") + flag.PrintDefaults() + fmt.Fprintf(os.Stderr, "\nAvailable rewrites are:\n") + sort.Sort(byName(fixes)) + for _, f := range fixes { + fmt.Fprintf(os.Stderr, "\n%s\n", f.name) + desc := strings.TrimSpace(f.desc) + desc = strings.Replace(desc, "\n", "\n\t", -1) + fmt.Fprintf(os.Stderr, "\t%s\n", desc) + } + os.Exit(2) +} + +func main() { + flag.Usage = usage + flag.Parse() + + sort.Sort(byDate(fixes)) + + if *allowedRewrites != "" { + allowed = make(map[string]bool) + for _, f := range strings.Split(*allowedRewrites, ",") { + allowed[f] = true + } + } + + if *forceRewrites != "" { + force = make(map[string]bool) + for _, f := range strings.Split(*forceRewrites, ",") { + force[f] = true + } + } + + if flag.NArg() == 0 { + if err := processFile("standard input", true); err != nil { + report(err) + } + os.Exit(exitCode) + } + + for i := 0; i < flag.NArg(); i++ { + path := flag.Arg(i) + switch dir, err := os.Stat(path); { + case err != nil: + report(err) + case dir.IsDir(): + walkDir(path) + default: + if err := processFile(path, false); err != nil { + report(err) + } + } + } + + os.Exit(exitCode) +} + +const parserMode = parser.ParseComments + +func gofmtFile(f *ast.File) ([]byte, error) { + var buf bytes.Buffer + if err := format.Node(&buf, fset, f); err != nil { + return nil, err + } + return buf.Bytes(), nil +} + +func processFile(filename string, useStdin bool) error { + var f *os.File + var err error + var fixlog bytes.Buffer + + if useStdin { + f = os.Stdin + } else { + f, err = os.Open(filename) + if err != nil { + return err + } + defer f.Close() + } + + src, err := ioutil.ReadAll(f) + if err != nil { + return err + } + + file, err := parser.ParseFile(fset, filename, src, parserMode) + if err != nil { + return err + } + + // Apply all fixes to file. + newFile := file + fixed := false + for _, fix := range fixes { + if allowed != nil && !allowed[fix.name] { + continue + } + if fix.f(newFile) { + fixed = true + fmt.Fprintf(&fixlog, " %s", fix.name) + + // AST changed. + // Print and parse, to update any missing scoping + // or position information for subsequent fixers. + newSrc, err := gofmtFile(newFile) + if err != nil { + return err + } + newFile, err = parser.ParseFile(fset, filename, newSrc, parserMode) + if err != nil { + if debug { + fmt.Printf("%s", newSrc) + report(err) + os.Exit(exitCode) + } + return err + } + } + } + if !fixed { + return nil + } + fmt.Fprintf(os.Stderr, "%s: fixed %s\n", filename, fixlog.String()[1:]) + + // Print AST. We did that after each fix, so this appears + // redundant, but it is necessary to generate gofmt-compatible + // source code in a few cases. The official gofmt style is the + // output of the printer run on a standard AST generated by the parser, + // but the source we generated inside the loop above is the + // output of the printer run on a mangled AST generated by a fixer. + newSrc, err := gofmtFile(newFile) + if err != nil { + return err + } + + if *doDiff { + data, err := diff(src, newSrc) + if err != nil { + return fmt.Errorf("computing diff: %s", err) + } + fmt.Printf("diff %s fixed/%s\n", filename, filename) + os.Stdout.Write(data) + return nil + } + + if useStdin { + os.Stdout.Write(newSrc) + return nil + } + + return ioutil.WriteFile(f.Name(), newSrc, 0) +} + +var gofmtBuf bytes.Buffer + +func gofmt(n interface{}) string { + gofmtBuf.Reset() + if err := format.Node(&gofmtBuf, fset, n); err != nil { + return "<" + err.Error() + ">" + } + return gofmtBuf.String() +} + +func report(err error) { + scanner.PrintError(os.Stderr, err) + exitCode = 2 +} + +func walkDir(path string) { + filepath.Walk(path, visitFile) +} + +func visitFile(path string, f os.FileInfo, err error) error { + if err == nil && isGoFile(f) { + err = processFile(path, false) + } + if err != nil { + report(err) + } + return nil +} + +func isGoFile(f os.FileInfo) bool { + // ignore non-Go files + name := f.Name() + return !f.IsDir() && !strings.HasPrefix(name, ".") && strings.HasSuffix(name, ".go") +} + +func diff(b1, b2 []byte) (data []byte, err error) { + f1, err := ioutil.TempFile("", "go-fix") + if err != nil { + return nil, err + } + defer os.Remove(f1.Name()) + defer f1.Close() + + f2, err := ioutil.TempFile("", "go-fix") + if err != nil { + return nil, err + } + defer os.Remove(f2.Name()) + defer f2.Close() + + f1.Write(b1) + f2.Write(b2) + + data, err = exec.Command("diff", "-u", f1.Name(), f2.Name()).CombinedOutput() + if len(data) > 0 { + // diff exits with a non-zero status when the files don't match. + // Ignore that failure as long as we get output. + err = nil + } + return +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/sdaccel.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/sdaccel.go new file mode 100644 index 0000000..2448ece --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/cmd/fix/sdaccel.go @@ -0,0 +1,31 @@ +// Copyright 2017 Reconfigure.io. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. +package main + +import ( + "go/ast" +) + +func init() { + register(sdaccel) +} + +var sdaccel = fix{ + name: "sdaccel", + date: "2017-12-12", + f: sdaccelFix, + desc: `Change imports of sdaccel to github.com/ReconfigureIO/sdaccel`, +} + +func sdaccelFix(f *ast.File) bool { + ret := false + ret = rewriteImport(f, "xcl", "github.com/ReconfigureIO/sdaccel/xcl") || ret + ret = rewriteImport(f, "sdaccel", "github.com/ReconfigureIO/sdaccel") || ret + ret = rewriteImport(f, "sdaccel/control", "github.com/ReconfigureIO/sdaccel/control") || ret + ret = rewriteImport(f, "axi", "github.com/ReconfigureIO/sdaccel/axi") || ret + ret = rewriteImport(f, "axi/protocol", "github.com/ReconfigureIO/sdaccel/axi/protocol") || ret + ret = rewriteImport(f, "axi/arbitrate", "github.com/ReconfigureIO/sdaccel/axi/arbitrate") || ret + ret = rewriteImport(f, "axi/memory", "github.com/ReconfigureIO/sdaccel/axi/memory") || ret + return ret +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/control/control.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/control/control.go new file mode 100644 index 0000000..987e414 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/control/control.go @@ -0,0 +1,70 @@ +// +// (c) 2017 ReconfigureIO +// +// +// + +// +// AXI-Lite interface definitions for interactive kernel control transactions. +// + +package control + +// Specifies AXI-Lite address channel fields. +type Addr struct { + Addr uint32 + Cache [4]bool + Prot [3]bool +} + +// Specifies AXI-Lite read data channel fields. +type ReadData struct { + Data uint32 + Resp [2]bool +} + +// Specifies AXI-Lite write data channel fields. +type WriteData struct { + Data uint32 + Strb [4]bool +} + +// Specifies AXI-Lite write response channel fields. +type WriteResp struct { + Resp [2]bool +} + +// Goroutine to disable control bus read transactions. Should only be run +// once for each control interface. +func DisableReads(controlReadAddr <-chan Addr, + controlReadData chan<- ReadData) { + for { + <-controlReadAddr + controlReadData <- ReadData{} + } +} + +// Goroutine to disable control bus write transactions. Should only be run once +// for each control interface. +func DisableWrites( + controlWriteAddr <-chan Addr, + controlWriteData <-chan WriteData, + controlWriteResp chan<- WriteResp) { + + for { + <-controlWriteAddr + <-controlWriteData + controlWriteResp <- WriteResp{} + } +} + +// Goroutine to disable control bus parameter RAM accesses. Should only be run +// once for each control interface. +func DisableParams( + paramAddr chan<- uint32, + paramData <-chan uint32) { + paramAddr <- 0 + for { + <-paramData + } +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/docker-compose.yml b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/docker-compose.yml new file mode 100644 index 0000000..177adc0 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/docker-compose.yml @@ -0,0 +1,7 @@ +version: '2' +services: + go: + image: golang:1.9 + working_dir: /go/src/github.com/ReconfigureIO/sdaccel + volumes: + - .:/go/src/github.com/ReconfigureIO/sdaccel diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/framework.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/framework.go new file mode 100644 index 0000000..abd3c23 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/framework.go @@ -0,0 +1,10 @@ +package sdaccel + +// #include verilog/sda_kernel_reset_handler.v +// #include verilog/sda_kernel_ctrl_reg_sel.v +// #include verilog/sda_kernel_ctrl_reg.v +// #include verilog/sda_kernel_ctrl_param.v +// #include verilog/sda_kernel_wrapper_gmem.v + +func init() { +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/fake.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/fake.go new file mode 100644 index 0000000..efc7fe0 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/fake.go @@ -0,0 +1,220 @@ +// +build !opencl + +package xcl + +import ( + "io" +) + +// World is an opaque structure that allows communication with FPGAs. +type World struct { +} + +// Program ways to lookup kernels +type Program struct { + world *World +} + +// Kernel is a a function that runs on an FGPA. +type Kernel struct { + program *Program +} + +// Memory represents a segment of RAM on the FGPA +type Memory struct { + world *World + size uint +} + +// MemoryWriter is an io.Writer to RAM on the FPGA +type MemoryWriter struct { + left uint + offset uint + memory *Memory +} + +// MemoryReader is an io.Reader to RAM on the FPGA +type MemoryReader struct { + left uint + offset uint + memory *Memory +} + +// Constants for opening RAM on the FGPA +const ( + ReadOnly = iota + WriteOnly + ReadWrite +) + +/* + +NewWorld creates a new World. This needs to be released when done. This can be done using `defer` + + world := xcl.NewWorld() + defer world.Release() + +*/ +func NewWorld() World { + return World{} +} + +/* + +Release cleans up a previously created World. + +*/ +func (world *World) Release() { +} + +/* + +Import will search for an appropriate xclbin and load their contents, +either in a simulator for hardware simulation, or onto an FPGA for +actual hardware. The input argument is the name of the program from +the build procedure (typically "kernel_test"). The returned value is +the program used for interacting with the loaded xclbin. + +This needs to be released when done. This can be done using defer. + + program := world.Import("kernel_test") + defer program.Release() + +*/ +func (world World) Import(program string) *Program { + return &Program{&world} +} + +/* + +GetKernel will return the specific Kernel from the Program. The input +argument is the name of the Kernel in the Program (typically +"reconfigure_io_sdaccel_builder_stub_0_1"). + +This needs to be released when done. + + + kernel := program.GetKernel("reconfigure_io_sdaccel_builder_stub_0_1") + defer kernel.Release() + +*/ +func (program *Program) GetKernel(kernelName string) *Kernel { + return &Kernel{program} +} + +/* + +Release a previously acquired Program. + +*/ +func (program *Program) Release() { +} + +/* + +Release a previously acquired Kernel + +*/ +func (kernel *Kernel) Release() { +} + +/* + +Malloc allocates a number of bytes on the FPGA. The resulting +structure represents a pointer to Memory on the FGPA. + +This needs to be freed when done. + + buff := world.Malloc(xcl.WriteOnly, 512) + defer buff.Free() + +*/ +func (world *World) Malloc(flags uint, size uint) *Memory { + return &Memory{world, size} +} + +/* + +Free a previously allocated Memory. + +*/ +func (mem *Memory) Free() { +} + +/* + +Writer constructs a one-time use writer for a Memory. This has the standard io.Writer interface. For example, to copy data to the FPGA with the binary package: + + var input [256]uint32 + err := binary.Write(buff.Writer(), binary.LittleEndian, &input) + +*/ +func (mem *Memory) Writer() *MemoryWriter { + return &MemoryWriter{mem.size, 0, mem} +} + +func (writer *MemoryWriter) Write(bytes []byte) (n int, err error) { + if writer.left == 0 { + return 0, io.ErrShortWrite + } + toWrite := uint(len(bytes)) + if toWrite > writer.left { + toWrite = writer.left + } + writer.left -= toWrite + writer.offset += toWrite + return int(toWrite), nil +} + +/* + +Reader constructs a one-time use reader for a Memory. This has the standard io.Reader interface. For example, to copy from the FPGA with the binary package: + + var input [256]uint32 + err := binary.Read(buff.Reader(), binary.LittleEndian, &input) + +*/ +func (mem *Memory) Reader() *MemoryReader { + return &MemoryReader{mem.size, 0, mem} +} + +func (reader *MemoryReader) Read(bytes []byte) (n int, err error) { + if reader.left == 0 { + return 0, io.EOF + } + toRead := uint(len(bytes)) + if toRead > reader.left { + toRead = reader.left + } + + reader.left -= toRead + reader.offset += toRead + return int(toRead), nil +} + +/* + +SetMemoryArg passes the pointer to Memory as an argument to the +Kernel. The resulting type on the kernel will be a uintptr. + +*/ +func (kernel *Kernel) SetMemoryArg(index uint, mem *Memory) { +} + +/* + +SetArg passes the uint32 as an argument to the Kernel. The resulting +type on the kernel will be a uint32. + +*/ +func (kernel *Kernel) SetArg(index uint, val uint32) { +} + +/* +Run will start execution of the Kernel with the number of dimensions. Most uses of this should be called as + + kernel.Run(1,1,1) + +*/ +func (kernel *Kernel) Run(x, y, z uint) { +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.c b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.c new file mode 100644 index 0000000..b4b1e1d --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.c @@ -0,0 +1,496 @@ +// +build opencl + +/********** +Copyright (c) 2016, Xilinx, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation +and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software +without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +**********/ + + +#include +#include +#include +#include +#include + +#include +#include + +#include "xcl.h" + +static void* smalloc(size_t size) { + void* ptr; + + ptr = malloc(size); + + if (ptr == NULL) { + printf("Error: Cannot allocate memory\n"); + exit(EXIT_FAILURE); + } + + return ptr; +} + +static int load_file_to_memory(const char *filename, char **result) { + unsigned int size; + + FILE *f = fopen(filename, "rb"); + if (f == NULL) { + *result = NULL; + printf("Error: Could not read file %s\n", filename); + exit(EXIT_FAILURE); + } + + fseek(f, 0, SEEK_END); + size = ftell(f); + fseek(f, 0, SEEK_SET); + + *result = (char *) smalloc(sizeof(char)*(size+1)); + + if (size != fread(*result, sizeof(char), size, f)) { + free(*result); + printf("Error: read of kernel failed\n"); + exit(EXIT_FAILURE); + } + + fclose(f); + (*result)[size] = 0; + + return size; +} + +char* xcl_create_and_set(const char* str) { + size_t len = strlen(str); + char *ret = (char*) malloc(sizeof(char)*len); + if (ret == NULL) { + printf("ERROR: Out of Memory\n"); + exit(EXIT_FAILURE); + } + strcpy(ret, str); + + return ret; +} + +xcl_world xcl_world_single() { + int err; + xcl_world world; + cl_uint num_platforms; + + char *xcl_mode = getenv("XCL_EMULATION_MODE"); + char *xcl_target = getenv("XCL_TARGET"); + + if(xcl_mode == NULL) { + world.mode = xcl_create_and_set("hw"); + } else { + /* if xcl_mode is set then check if it's equal to true*/ + if(strcmp(xcl_mode,"true") == 0) { + /* if it's true, then check if xcl_target is set */ + if(xcl_target == NULL) { + /* default if emulation but not specified is software emulation */ + world.mode = xcl_create_and_set("sw_emu"); + } else { + /* otherwise, it's what ever is specified in XCL_TARGET */ + world.mode = xcl_create_and_set(xcl_target); + } + } else { + /* if it's not equal to true then it should be whatever + * XCL_EMULATION_MODE is set to */ + world.mode = xcl_create_and_set(xcl_mode); + } + + err = setenv("XCL_EMULATION_MODE", "true", 1); + if(err != 0) { + printf("Error: cannot set XCL_EMULATION_MODE\n"); + exit(EXIT_FAILURE); + } + } + + err = clGetPlatformIDs(0, NULL, &num_platforms); + if (err != CL_SUCCESS) { + printf("Error: no platforms available or OpenCL install broken\n"); + exit(EXIT_FAILURE); + } + + cl_platform_id *platform_ids = (cl_platform_id *) malloc(sizeof(cl_platform_id) * num_platforms); + + if (platform_ids == NULL) { + printf("Error: Out of Memory\n"); + exit(EXIT_FAILURE); + } + + err = clGetPlatformIDs(num_platforms, platform_ids, NULL); + if (err != CL_SUCCESS) { + printf("Error: Failed to find an OpenCL platform!\n"); + exit(EXIT_FAILURE); + } + + size_t i; + for(i = 0; i < num_platforms; i++) { + size_t platform_name_size; + err = clGetPlatformInfo(platform_ids[i], CL_PLATFORM_NAME, + 0, NULL, &platform_name_size); + if( err != CL_SUCCESS) { + printf("Error: Could not determine platform name!\n"); + exit(EXIT_FAILURE); + } + + char *platform_name = (char*) malloc(sizeof(char)*platform_name_size); + if(platform_name == NULL) { + printf("Error: out of memory!\n"); + exit(EXIT_FAILURE); + } + + err = clGetPlatformInfo(platform_ids[i], CL_PLATFORM_NAME, + platform_name_size, platform_name, NULL); + if(err != CL_SUCCESS) { + printf("Error: could not determine platform name!\n"); + exit(EXIT_FAILURE); + } + + if (!strcmp(platform_name, "Xilinx")) { + free(platform_name); + world.platform_id = platform_ids[i]; + break; + } + + free(platform_name); + } + + free(platform_ids); + + if (i == num_platforms) { + printf("Error: Failed to find Xilinx platform\n"); + exit(EXIT_FAILURE); + } + + err = clGetDeviceIDs(world.platform_id, CL_DEVICE_TYPE_ALL, + 1, &world.device_id, NULL); + if (err != CL_SUCCESS) { + printf("Error: could not get device ids\n"); + exit(EXIT_FAILURE); + } + + size_t device_name_size; + err = clGetDeviceInfo(world.device_id, CL_DEVICE_NAME, + 0, NULL, &device_name_size); + if(err != CL_SUCCESS) { + printf("Error: could not determine device name\n"); + exit(EXIT_FAILURE); + } + + world.device_name = (char*) malloc(sizeof(char)*device_name_size); + + if(world.device_name == NULL) { + printf("Error: Out of Memory!\n"); + exit(EXIT_FAILURE); + } + + err = clGetDeviceInfo(world.device_id, CL_DEVICE_NAME, + device_name_size, world.device_name, NULL); + if(err != CL_SUCCESS) { + printf("Error: could not determine device name\n"); + exit(EXIT_FAILURE); + } + + world.context = clCreateContext(0, 1, &world.device_id, + NULL, NULL, &err); + if (err != CL_SUCCESS) { + printf("Error: Failed to create a compute context!\n"); + exit(EXIT_FAILURE); + } + + world.command_queue = clCreateCommandQueue(world.context, + world.device_id, + CL_QUEUE_PROFILING_ENABLE, + &err); + if (err != CL_SUCCESS) { + printf("Error: Failed to create a command queue!\n"); + exit(EXIT_FAILURE); + } + + return world; +} + +void xcl_release_world(xcl_world world) { + clReleaseCommandQueue(world.command_queue); + clReleaseContext(world.context); + free(world.device_name); + free(world.mode); +} + +cl_program xcl_import_binary_file(xcl_world world, + const char *xclbin_file_name +) { + int err; + + if(access(xclbin_file_name, R_OK) != 0) { + printf("ERROR: %s xclbin not available please build\n", xclbin_file_name); + exit(EXIT_FAILURE); + } + + char *krnl_bin; + const size_t krnl_size = load_file_to_memory(xclbin_file_name, &krnl_bin); + + cl_program program = clCreateProgramWithBinary(world.context, 1, + &world.device_id, &krnl_size, + (const unsigned char**) &krnl_bin, + NULL, &err); + if ((!program) || (err!=CL_SUCCESS)) { + printf("Error: Failed to create compute program from binary %d!\n", + err); + printf("Test failed\n"); + exit(EXIT_FAILURE); + } + + err = clBuildProgram(program, 0, NULL, NULL, NULL, NULL); + if (err != CL_SUCCESS) { + size_t len; + char buffer[2048]; + + clGetProgramBuildInfo(program, world.device_id, CL_PROGRAM_BUILD_LOG, + sizeof(buffer), buffer, &len); + printf("%s\n", buffer); + printf("Error: Failed to build program executable!\n"); + exit(EXIT_FAILURE); + } + + free(krnl_bin); + + return program; +} + +cl_program xcl_import_binary(xcl_world world, + const char *xclbin_name +) { + char *xcl_bindir = getenv("XCL_BINDIR"); + + // typical locations of directory containing xclbin files + const char *dirs[] = { + xcl_bindir, // $XCL_BINDIR-specified + "xclbin", // command line build + "..", // gui build + run + ".", // gui build, run in build directory + NULL + }; + const char **search_dirs = dirs; + if (xcl_bindir == NULL) { + search_dirs++; + } + + char *device_name = strdup(world.device_name); + if (device_name == NULL) { + printf("Error: Out of Memory\n"); + exit(EXIT_FAILURE); + } + + // fix up device name to avoid colons and dots. + // xilinx:xil-accel-rd-ku115:4ddr-xpr:3.2 -> xilinx_xil-accel-rd-ku115_4ddr-xpr_3_2 + for (char *c = device_name; *c != 0; c++) { + if (*c == ':' || *c == '.') { + *c = '_'; + } + } + + const char *file_patterns[] = { + "%1$s/%2$s.%3$s.%4$s.xclbin", // ...xclbin + "%1$s/binary_container_1.xclbin", // default for gui projects + "%1$s/%2$s.xclbin", // .xclbin + NULL + }; + char xclbin_file_name[PATH_MAX]; + memset(xclbin_file_name, 0, PATH_MAX); + ino_t ino = 0; // used to avoid errors if an xclbin found via multiple/repeated paths + for (const char **dir = search_dirs; *dir != NULL; dir++) { + struct stat sb; + if (stat(*dir, &sb) == 0 && S_ISDIR(sb.st_mode)) { + for (const char **pattern = file_patterns; *pattern != NULL; pattern++) { + char file_name[PATH_MAX]; + memset(file_name, 0, PATH_MAX); + snprintf(file_name, PATH_MAX, *pattern, *dir, xclbin_name, world.mode, device_name); + if (stat(file_name, &sb) == 0 && S_ISREG(sb.st_mode)) { + world.bindir = strdup(*dir); + if (world.bindir == NULL) { + printf("Error: Out of Memory\n"); + exit(EXIT_FAILURE); + } + if (*xclbin_file_name && sb.st_ino != ino) { + printf("Error: multiple xclbin files discovered:\n %s\n %s\n", file_name, xclbin_file_name); + exit(EXIT_FAILURE); + } + ino = sb.st_ino; + strncpy(xclbin_file_name, file_name, PATH_MAX); + } + } + } + } + // if no xclbin found, preferred path for error message from xcl_import_binary_file() + if (*xclbin_file_name == '\0') { + snprintf(xclbin_file_name, PATH_MAX, file_patterns[0], *search_dirs, xclbin_name, world.mode, device_name); + } + + free(device_name); + + return xcl_import_binary_file(world, xclbin_file_name); +} + +cl_program xcl_import_source(xcl_world world, + const char *krnl_file +) { + int err; + + char *krnl_bin; + load_file_to_memory(krnl_file, &krnl_bin); + + cl_program program = clCreateProgramWithSource(world.context, 1, + (const char**) &krnl_bin, + 0, &err); + if ((err!=CL_SUCCESS) || (!program)) { + printf("Error: Failed to create compute program from binary %d!\n", + err); + printf("Test failed\n"); + exit(EXIT_FAILURE); + } + + err = clBuildProgram(program, 0, NULL, NULL, NULL, NULL); + if (err != CL_SUCCESS) { + size_t len; + char buffer[2048]; + + printf("Error: Failed to build program executable!\n"); + clGetProgramBuildInfo(program, world.device_id, CL_PROGRAM_BUILD_LOG, + sizeof(buffer), buffer, &len); + printf("%s\n", buffer); + printf("Test failed\n"); + exit(EXIT_FAILURE); + } + + free(krnl_bin); + + return program; +} + +cl_kernel xcl_get_kernel(cl_program program, + const char *krnl_name +) { + int err; + + cl_kernel kernel = clCreateKernel(program, krnl_name, &err); + if (!kernel || err != CL_SUCCESS) { + printf("Error: Failed to create kernel for %s: %d\n", krnl_name, err); + exit(EXIT_FAILURE); + } + + return kernel; +} + +void xcl_set_kernel_arg(cl_kernel krnl, + cl_uint num, + size_t size, + const void *ptr +) { + int err = clSetKernelArg(krnl, num, size, ptr); + + if(err != CL_SUCCESS) { + printf("Error: Failed to set kernel arg\n"); + exit(EXIT_FAILURE); + } +} + +cl_mem xcl_malloc(xcl_world world, cl_mem_flags flags, size_t size) { + cl_mem mem = clCreateBuffer(world.context, flags, size, NULL, NULL); + + if (!mem) { + printf("Error: Failed to allocate device memory!\n"); + exit(EXIT_FAILURE); + } + + return mem; +} + +void xcl_memcpy_to_device(xcl_world world, cl_mem dest, void* src, + size_t size) { + int err = clEnqueueWriteBuffer(world.command_queue, dest, CL_TRUE, 0, size, + src, 0, NULL, NULL); + if (err != CL_SUCCESS) { + printf("Error: Failed to write to source array! %d\n", err); + exit(EXIT_FAILURE); + } +} + +void xcl_memcpy_from_device(xcl_world world, void* dest, + cl_mem src, size_t size +) { + int err = clEnqueueReadBuffer(world.command_queue, src, CL_TRUE, 0, size, + dest, 0, NULL, NULL); + if (err != CL_SUCCESS) { + printf("Error: Failed to read output array! %d\n", err); + exit(EXIT_FAILURE); + } +} + +unsigned long xcl_get_event_duration(cl_event event) { + unsigned long start, stop; + + clGetEventProfilingInfo(event, CL_PROFILING_COMMAND_QUEUED, + sizeof(unsigned long), &start, NULL); + clGetEventProfilingInfo(event, CL_PROFILING_COMMAND_END, + sizeof(unsigned long), &stop, NULL); + + return stop - start; +} + +unsigned long xcl_run_kernel3d(xcl_world world, cl_kernel krnl, + size_t x, size_t y, size_t z +) { + size_t size[3] = {x, y, z}; + cl_event event; + + int err = clEnqueueNDRangeKernel(world.command_queue, krnl, 3, + NULL, size, size, 0, NULL, &event); + if( err != CL_SUCCESS) { + printf("Error: failed to execute kernel! %d\n", err); + exit(EXIT_FAILURE); + } + + clFinish(world.command_queue); + + return xcl_get_event_duration(event); +} + +void xcl_run_kernel3d_nb(xcl_world world, cl_kernel krnl,cl_event *event, + size_t x, size_t y, size_t z) { + size_t size[3] = {x, y, z}; + + int err = clEnqueueNDRangeKernel(world.command_queue, krnl, 3, + NULL, size, size, 0, NULL, event); + if( err != CL_SUCCESS) { + printf("Error: failed to execute kernel! %d\n", err); + printf("Test failed\n"); + exit(EXIT_FAILURE); + } + + return; +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.go b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.go new file mode 100644 index 0000000..dc60896 --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.go @@ -0,0 +1,313 @@ +// +build opencl + +// Package xcl provides primitives for working with kernels from the host +package xcl + +// #cgo CFLAGS: -std=gnu99 +// #cgo LDFLAGS: -lxilinxopencl -llmx6.0 +// #include "xcl.h" +// #include +// +// cl_int setMemArg(cl_kernel kernel, cl_uint arg_index, cl_mem m) { +// return clSetKernelArg(kernel, arg_index, sizeof(cl_mem), &m); +// } +// +import "C" + +import ( + "errors" + "fmt" + "io" + "unsafe" +) + +// World is an opaque structure that allows communication with FPGAs. +type World struct { + cw C.xcl_world +} + +// Program ways to lookup kernels +type Program struct { + world *World + program C.cl_program +} + +// Kernel is a a function that runs on an FGPA. +type Kernel struct { + program *Program + kernel C.cl_kernel +} + +// Memory represents a segment of RAM on the FGPA +type Memory struct { + world *World + size uint + mem C.cl_mem +} + +// MemoryWriter is an io.Writer to RAM on the FPGA +type MemoryWriter struct { + left uint + offset uint + memory *Memory +} + +// MemoryReader is an io.Reader to RAM on the FPGA +type MemoryReader struct { + left uint + offset uint + memory *Memory +} + +// Constants for opening RAM on the FGPA +const ( + ReadOnly = iota + WriteOnly + ReadWrite +) + +/* + +NewWorld creates a new World. This needs to be released when done. This can be done using `defer` + + world := xcl.NewWorld() + defer world.Release() + +*/ +func NewWorld() World { + return World{C.xcl_world_single()} +} + +/* + +Release cleans up a previously created World. + +*/ +func (world *World) Release() { + C.xcl_release_world(world.cw) +} + +/* + +Import will search for an appropriate xclbin and load their contents, +either in a simulator for hardware simulation, or onto an FPGA for +actual hardware. The input argument is the name of the program from +the build procedure (typically "kernel_test"). The returned value is +the program used for interacting with the loaded xclbin. + +This needs to be released when done. This can be done using defer. + + program := world.Import("kernel_test") + defer program.Release() + +*/ +func (world World) Import(program string) *Program { + s := C.CString(program) + p := C.xcl_import_binary(world.cw, s) + C.free(unsafe.Pointer(s)) + return &Program{&world, p} +} + +/* + +GetKernel will return the specific Kernel from the Program. The input +argument is the name of the Kernel in the Program (typically +"reconfigure_io_sdaccel_builder_stub_0_1"). + +This needs to be released when done. + + + kernel := program.GetKernel("reconfigure_io_sdaccel_builder_stub_0_1") + defer kernel.Release() + +*/ +func (program *Program) GetKernel(kernelName string) *Kernel { + s := C.CString(kernelName) + k := C.xcl_get_kernel(C.cl_program(program.program), s) + C.free(unsafe.Pointer(s)) + return &Kernel{program, k} +} + +/* + +Release a previously acquired Program. + +*/ +func (program *Program) Release() { + C.clReleaseProgram(program.program) +} + +/* + +Release a previously acquired Kernel + +*/ +func (kernel *Kernel) Release() { + C.clReleaseKernel(kernel.kernel) +} + +/* + +Malloc allocates a number of bytes on the FPGA. The resulting +structure represents a pointer to Memory on the FGPA. + +This needs to be freed when done. + + buff := world.Malloc(xcl.WriteOnly, 512) + defer buff.Free() + +*/ +func (world *World) Malloc(flags uint, size uint) *Memory { + var f C.cl_mem_flags + switch flags { + case ReadOnly: + f = C.CL_MEM_READ_ONLY + case WriteOnly: + f = C.CL_MEM_WRITE_ONLY + case ReadWrite: + f = C.CL_MEM_READ_WRITE + } + m := C.xcl_malloc(world.cw, f, C.size_t(size)) + return &Memory{world, size, m} +} + +/* + +Free a previously allocated Memory. + +*/ +func (mem *Memory) Free() { + C.clReleaseMemObject(mem.mem) +} + +/* + +Writer constructs a one-time use writer for a Memory. This has the standard io.Writer interface. For example, to copy data to the FPGA with the binary package: + + var input [256]uint32 + err := binary.Write(buff.Writer(), binary.LittleEndian, &input) + +*/ +func (mem *Memory) Writer() *MemoryWriter { + return &MemoryWriter{mem.size, 0, mem} +} + +func errorCode(code C.cl_int) error { + switch code { + case C.CL_SUCCESS: + return nil + case C.CL_INVALID_COMMAND_QUEUE: + return errors.New("CL_INVALID_COMMAND_QUEUE") + case C.CL_INVALID_CONTEXT: + return errors.New("CL_INVALID_CONTEXT") + case C.CL_INVALID_MEM_OBJECT: + return errors.New("CL_INVALID_MEM_OBJECT") + case C.CL_INVALID_VALUE: + return errors.New("CL_INVALID_VALUE") + case C.CL_INVALID_EVENT_WAIT_LIST: + return errors.New("CL_INVALID_EVENT_WAIT_LIST") + case C.CL_MISALIGNED_SUB_BUFFER_OFFSET: + return errors.New("CL_MISALIGNED_SUB_BUFFER_OFFSET") + case C.CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST: + return errors.New("CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST") + case C.CL_MEM_OBJECT_ALLOCATION_FAILURE: + return errors.New("CL_MEM_OBJECT_ALLOCATION_FAILURE") + case C.CL_INVALID_OPERATION: + return errors.New("CL_INVALID_OPERATION") + case C.CL_OUT_OF_RESOURCES: + return errors.New("CL_OUT_OF_RESOURCES") + case C.CL_OUT_OF_HOST_MEMORY: + return errors.New("CL_OUT_OF_HOST_MEMORY") + default: + return fmt.Errorf("Unknown error code %d", code) + } +} + +func (writer *MemoryWriter) Write(bytes []byte) (n int, err error) { + if writer.left == 0 { + return 0, io.ErrShortWrite + } + toWrite := uint(len(bytes)) + if toWrite > writer.left { + toWrite = writer.left + } + // I think we can make this zero copy like in Read + p := C.CBytes(bytes[0:toWrite]) + + ret := C.clEnqueueWriteBuffer( + writer.memory.world.cw.command_queue, + writer.memory.mem, + C.CL_TRUE, + C.size_t(writer.offset), C.size_t(toWrite), p, C.cl_uint(0), nil, nil) + + err = errorCode(ret) + C.free(p) + writer.left -= toWrite + writer.offset += toWrite + return int(toWrite), err +} + +/* + +Reader constructs a one-time use reader for a Memory. This has the standard io.Reader interface. For example, to copy from the FPGA with the binary package: + + var input [256]uint32 + err := binary.Read(buff.Reader(), binary.LittleEndian, &input) + +*/ +func (mem *Memory) Reader() *MemoryReader { + return &MemoryReader{mem.size, 0, mem} +} + +func (reader *MemoryReader) Read(bytes []byte) (n int, err error) { + if reader.left == 0 { + return 0, io.EOF + } + toRead := uint(len(bytes)) + if toRead > reader.left { + toRead = reader.left + } + + p := unsafe.Pointer(&bytes[0]) + + ret := C.clEnqueueReadBuffer( + reader.memory.world.cw.command_queue, + reader.memory.mem, + C.CL_TRUE, + C.size_t(reader.offset), C.size_t(toRead), p, C.cl_uint(0), nil, nil) + + err = errorCode(ret) + reader.left -= toRead + reader.offset += toRead + return int(toRead), err +} + +/* + +SetMemoryArg passes the pointer to Memory as an argument to the +Kernel. The resulting type on the kernel will be a uintptr. + +*/ +func (kernel *Kernel) SetMemoryArg(index uint, mem *Memory) { + C.setMemArg(kernel.kernel, C.cl_uint(index), mem.mem) +} + +/* + +SetArg passes the uint32 as an argument to the Kernel. The resulting +type on the kernel will be a uint32. + +*/ +func (kernel *Kernel) SetArg(index uint, val uint32) { + C.clSetKernelArg(kernel.kernel, C.cl_uint(index), C.size_t(unsafe.Sizeof(val)), unsafe.Pointer(&val)) +} + +/* +Run will start execution of the Kernel with the number of dimensions. Most uses of this should be called as + + kernel.Run(1,1,1) + +*/ +func (kernel *Kernel) Run(x, y, z uint) { + C.xcl_run_kernel3d(kernel.program.world.cw, kernel.kernel, C.size_t(x), C.size_t(y), C.size_t(z)) +} diff --git a/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.h b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.h new file mode 100644 index 0000000..c56639e --- /dev/null +++ b/scripts/files/vendor/github.com/ReconfigureIO/sdaccel/xcl/xcl.h @@ -0,0 +1,239 @@ +/********** +Copyright (c) 2016, Xilinx, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation +and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software +without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +**********/ + + +#pragma once + +#include + +typedef struct { + char *mode; + char *bindir; + char *device_name; + cl_context context; + cl_platform_id platform_id; + cl_device_id device_id; + cl_command_queue command_queue; +} xcl_world; + +/* xcl_world_single + * + * Description: + * Setup an xcl_world for the case when there is a single + * device in the system. + * + * Inputs: + * + * Returns: + * A struct containing the platform_id, device_id, context, and command + * queue. + */ +xcl_world xcl_world_single(); + +/* xcl_release_world + * + * Description: + * Release memory used by xcl_world struct. + * + * Inputs: + * world - xcl_world to release memory from. + */ +void xcl_release_world(xcl_world world); + +/* xcl_import_binary + * + * Description: + * Import precompiled program (as commonly created by the Xilinx OpenCL + * flow). + * + * Inputs: + * world - xcl_world to import into. + * xclbin_file - base name of the xclbin to import. + * krnl_name - name of kernel. + * + * Returns: + * An opencl program object that was created from krnl_name file. + */ +cl_program xcl_import_binary(xcl_world world, const char *xclbin_file); + +/* xcl_import_binary_file + * + * Description: + * Import precompiled program (as commonly created by the Xilinx OpenCL + * flow). + * + * Inputs: + * world - xcl_world to import into. + * xclbin_file - file name of xclbin to import. + * + * Returns: + * An opencl program object that was created from krnl_name file. + */ +cl_program xcl_import_binary_file(xcl_world world, const char *xclbin_file_name); + + +/* xcl_import_source + * + * Description: + * Import opencl source code. + * + * Inputs: + * world - xcl_world to import into. + * krnl_file - file name of the kernel to import. + * krnl_name - name of kernel. + * + * Returns: + * An opencl program object that was created from krnl_name file. + */ +cl_program xcl_import_source(xcl_world world, const char *krnl_file); + +/* xcl_get_kernel + * + * Description: + * Get kernel from program + * + * Input: + * program - program that was built + * krnl_name - name of kernel + * + * Returns: + * An opencl kernel object that was created from the krnl_name + */ +cl_kernel xcl_get_kernel(cl_program program, const char *krnl_name); + +/* xcl_create_kernel + * + * Description: + * Create kernel in program and return kernel object + * + * Inputs: + * world - program in which kernel is created + * krnl_name - name of kernel. + * + * Returns: + * An opencl kernel object that was created from krnl_name file. + */ +cl_kernel xcl_create_kernel(cl_program program, const char *krnl_name); + + +/* xcl_set_kernel_arg + * + * Description: + * Set kernel arguments + * + * Inputs: + * krnl - kernel to set values for + * num - which kernel arg to set + * size - size of argument + * ptr - address of value + */ +void xcl_set_kernel_arg(cl_kernel krnl, cl_uint num, size_t size, const void *ptr); + +/* xcl_malloc + * + * Description: + * Allocate memory for a buffer on the FPGA device. Exit program on + * error. + * + * Inputs: + * world - xcl_world of the device to create buffer on. + * flags - passed to clCreateBuffer. + * size - buffer size in bytes (like malloc). + */ +cl_mem xcl_malloc(xcl_world world, cl_mem_flags flags, size_t size); + +/* xcl_memcpy_to_device/xcl_memcpy_from_device + * + * Description: + * Copy memory from the host to the FPGA device (or vice a verse.) The + * memory on the FPGA must be allocated with xcl_malloc (or the lower + * level opencl functions) + * + * Inputs: + * world - xcl_world to copy the buffer into. + * dest - memory address on the FPGA to copy to. + * src - memory address on the host to copy from. + * size - number of bytes in src to copy to dest. + */ +void xcl_memcpy_to_device(xcl_world world, cl_mem dest, void* src, + size_t size); +void xcl_memcpy_from_device(xcl_world world, void* dest, cl_mem src, + size_t size); + +/* xcl_get_event_duration + * + * Description: + * Determine the duration of an event + * + * Inputs: + * event - determine the duration of this event + * + * Returns: + * time that the event took to run to completion. + */ +unsigned long xcl_get_event_duration(cl_event event); + +/* xcl_run_kernel3d + * + * Description: + * Run a kernel with a 3 dimensional thread array. In this configuration, + * there will be x*y*z threads created with a rank in each dimension. + * + * Inputs: + * world - xcl_world to use for running the kernel. + * krnl - application to run on the device. + * x - number of threads in the x direction. + * y - number of threads in the y direction. + * z - number of threads in the z direction. + * + * Returns: + * For purposes of benchmarking, the return of this program is the length of + * time that the kernel took to run to completion. + */ +unsigned long xcl_run_kernel3d(xcl_world world, cl_kernel krnl, + size_t x, size_t y, size_t z); + +/* xcl_run_kernel3d_nb + * + * Description: + * Run a kernel with a 3 dimensional thread array and return immediately. In this configuration, + * there will be x*y*z threads created with a rank in each dimension. + * + * Inputs: + * world - xcl_world to use for running the kernel. + * krnl - application to run on the device. + * x - number of threads in the x direction. + * y - number of threads in the y direction. + * z - number of threads in the z direction. + * + * Returns: No Return + * + */ +void xcl_run_kernel3d_nb(xcl_world world, cl_kernel krnl, cl_event *evt, + size_t x, size_t y, size_t z);