From 7cb19a4f3b8e097ba39387480f41cde6297610a9 Mon Sep 17 00:00:00 2001
From: TimRudy <3942818+TimRudy@users.noreply.github.com>
Date: Sun, 19 Jan 2020 21:17:02 -0500
Subject: [PATCH] More initial

---
 source-7400/74139-tb.v | 14 +++++++-------
 source-7400/74153-tb.v | 18 +++++++++---------
 source-7400/74155-tb.v | 20 ++++++++++----------
 source-7400/74160-tb.v | 12 ++++++------
 source-7400/74161-tb.v | 12 ++++++------
 source-7400/74266-tb.v | 15 +++++++--------
 source-7400/74266.v    |  7 +++----
 source-7400/74352-tb.v | 18 +++++++++---------
 source-7400/7486-tb.v  | 14 +++++++-------
 source-7400/7486.v     |  6 +++---
 10 files changed, 67 insertions(+), 69 deletions(-)

diff --git a/source-7400/74139-tb.v b/source-7400/74139-tb.v
index a189c83..a0eee82 100644
--- a/source-7400/74139-tb.v
+++ b/source-7400/74139-tb.v
@@ -47,7 +47,7 @@ begin
   tbassert(YOutputs == 2'b10, "Test 1");
   tbassert(ZOutputs == 2'b10, "Test 1");
 #0
-  // select A: disabled in first BLOCK -> output is 11 instead of 10
+  // select A: disabled in first block -> output is 11 instead of 10
   Enable_bar[0] = 1'b1;
 #6
   {ZOutputs, YOutputs, XOutputs} = Y;
@@ -55,7 +55,7 @@ begin
   tbassert(YOutputs == 2'b10, "Test 2");
   tbassert(ZOutputs == 2'b10, "Test 2");
 #0
-  // select A: disabled in second BLOCK, enabled in first BLOCK
+  // select A: disabled in second block, enabled in first block
   Enable_bar[0] = 1'b0;
   Enable_bar[1] = 1'b1;
 #6
@@ -76,7 +76,7 @@ begin
   tbassert(YOutputs == 2'b11, "Test 4");
   tbassert(ZOutputs == 2'b11, "Test 4");
 #0
-  // select B: enabled in second and third BLOCKs -> second output is 0 where enabled
+  // select B: enabled in second and third blocks -> second output is 0 where enabled
   Enable_bar[1] = 1'b0;
   Enable_bar[2] = 1'b0;
 #10
@@ -85,7 +85,7 @@ begin
   tbassert(YOutputs == 2'b01, "Test 5");
   tbassert(ZOutputs == 2'b01, "Test 5");
 #0
-  // select A: enabled in second and third BLOCKs -> first output is 0 where enabled
+  // select A: enabled in second and third blocks -> first output is 0 where enabled
   A = {BLOCKS{1'b0}};
 #10
   {ZOutputs, YOutputs, XOutputs} = Y;
@@ -93,7 +93,7 @@ begin
   tbassert(YOutputs == 2'b10, "Test 6");
   tbassert(ZOutputs == 2'b10, "Test 6");
 #0
-  // select A: enabled in first and third BLOCKs
+  // select A: enabled in first and third blocks
   Enable_bar[0] = 1'b0;
   Enable_bar[1] = 1'b1;
   Enable_bar[2] = 1'b0;
@@ -154,7 +154,7 @@ begin
   tbassert(YOutputs == 2'b10, "Test 11");
   tbassert(ZOutputs == 2'b01, "Test 11");
 #0
-  // same selects but disabled in first BLOCK -> output is 11 instead of 01
+  // same selects but disabled in first block -> output is 11 instead of 01
   Enable_bar[0] = 1'b1;
 #6
   {ZOutputs, YOutputs, XOutputs} = Y;
@@ -162,7 +162,7 @@ begin
   tbassert(YOutputs == 2'b10, "Test 12");
   tbassert(ZOutputs == 2'b01, "Test 12");
 #0
-  // same selects but disabled in second BLOCK, enabled in first BLOCK -> output is 11
+  // same selects but disabled in second block, enabled in first block -> output is 11
   // instead of 10
   Enable_bar[0] = 1'b0;
   Enable_bar[1] = 1'b1;
diff --git a/source-7400/74153-tb.v b/source-7400/74153-tb.v
index 0be3131..71926d8 100644
--- a/source-7400/74153-tb.v
+++ b/source-7400/74153-tb.v
@@ -44,12 +44,12 @@ begin
 #6
   tbassert(Y == 3'b011, "Test 1");
 #0
-  // select A: disabled in first BLOCK -> output is 0s where disabled
+  // select A: disabled in first block -> output is 0s where disabled
   Enable_bar[0] = 1'b1;
 #6
   tbassert(Y == 3'b010, "Test 2");
 #0
-  // select A: disabled in second BLOCK, enabled in first BLOCK
+  // select A: disabled in second block, enabled in first block
   Enable_bar[0] = 1'b0;
   Enable_bar[1] = 1'b1;
 #6
@@ -61,18 +61,18 @@ begin
 #10
   tbassert(Y == 3'b000, "Test 4");
 #0
-  // select B: enabled in second and third BLOCKs
+  // select B: enabled in second and third blocks
   Enable_bar[1] = 1'b0;
   Enable_bar[2] = 1'b0;
 #10
   tbassert(Y == 3'b110, "Test 5");
 #0
-  // select A: enabled in second and third BLOCKs
+  // select A: enabled in second and third blocks
   Select = 2'b00;
 #10
   tbassert(Y == 3'b010, "Test 6");
 #0
-  // select D: enabled in second and third BLOCKs
+  // select D: enabled in second and third blocks
   Select = 2'b11;
 #10
   tbassert(Y == 3'b100, "Test 7");
@@ -95,12 +95,12 @@ begin
 #10
   tbassert(Y == 3'b111, "Test 10");
 #0
-  // select C: disabled in first BLOCK
+  // select C: disabled in first block
   Enable_bar[0] = 1'b1;
 #6
   tbassert(Y == 3'b110, "Test 11");
 #0
-  // select A: disabled in first and third BLOCKs
+  // select A: disabled in first and third blocks
   Enable_bar[2] = 1'b1;
   Select = 2'b00;
 #10
@@ -170,7 +170,7 @@ begin
 #10
   tbassert(Y == 3'b111, "Test 18");
 #0
-  // while enabled in second and third BLOCKs: change to select A from select B and
+  // while enabled in second and third blocks: change to select A from select B and
   // change to different inputs with null effect on output 1s
   Enable_bar = 3'b001;
 #6
@@ -184,7 +184,7 @@ begin
 #10
   tbassert(Y == 3'b110, "Test 19");
 #0
-  // while enabled in second and third BLOCKs: change back to select B from select A
+  // while enabled in second and third blocks: change back to select B from select A
   Select = 2'b01;
 #10
   tbassert(Y == 3'b000, "Test 20");
diff --git a/source-7400/74155-tb.v b/source-7400/74155-tb.v
index d56b692..eed0ee8 100644
--- a/source-7400/74155-tb.v
+++ b/source-7400/74155-tb.v
@@ -52,14 +52,14 @@ begin
   tbassert(Block1 == 8'b11111110, "Test 1");
   tbassert(Block2 == 8'b11111110, "Test 1");
 #0
-  // select Addr 0: disabled in first BLOCK -> output is 1s where disabled
+  // select Addr 0: disabled in first block -> output is 1s where disabled
   Enable1C = 1'b0;
 #6
   {Block2, Block1} = Y;
   tbassert(Block1 == 8'b11111111, "Test 2");
   tbassert(Block2 == 8'b11111110, "Test 2");
 #0
-  // select Addr 0: disabled in second BLOCK, enabled in first BLOCK
+  // select Addr 0: disabled in second block, enabled in first block
   Enable1C = 1'b1;
   Enable2C_bar = 1'b1;
 #6
@@ -67,7 +67,7 @@ begin
   tbassert(Block1 == 8'b11111110, "Test 3");
   tbassert(Block2 == 8'b11111111, "Test 3");
 #0
-  // select Addr 0: disabled by the other enable input in second BLOCK, enabled in first BLOCK
+  // select Addr 0: disabled by the other enable input in second block, enabled in first block
   Enable2C_bar = 1'b0;
   Enable2G_bar = 1'b1;
 #6
@@ -86,7 +86,7 @@ begin
   tbassert(Block1 == 8'b11111111, "Test 5");
   tbassert(Block2 == 8'b11111111, "Test 5");
 #0
-  // select Addr 1: enabled in second BLOCK -> second output is 0 where enabled
+  // select Addr 1: enabled in second block -> second output is 0 where enabled
   Enable2C_bar = 1'b0;
   Enable2G_bar = 1'b0;
 #10
@@ -94,14 +94,14 @@ begin
   tbassert(Block1 == 8'b11111111, "Test 6");
   tbassert(Block2 == 8'b11111101, "Test 6");
 #0
-  // select Addr 1: enabled in second BLOCK, disabled by only one enable input in first BLOCK
+  // select Addr 1: enabled in second block, disabled by only one enable input in first block
   Enable1G_bar = 1'b0;
 #10
   {Block2, Block1} = Y;
   tbassert(Block1 == 8'b11111111, "Test 7");
   tbassert(Block2 == 8'b11111101, "Test 7");
 #0
-  // select Addr 1: enabled in second BLOCK, disabled by the other enable input in first BLOCK
+  // select Addr 1: enabled in second block, disabled by the other enable input in first block
   Enable1C = 1'b1;
   Enable1G_bar = 1'b1;
 #10
@@ -109,7 +109,7 @@ begin
   tbassert(Block1 == 8'b11111111, "Test 8");
   tbassert(Block2 == 8'b11111101, "Test 8");
 #0
-  // select Addr 1: from enabled to disabled in both BLOCKs -> output 1s
+  // select Addr 1: from enabled to disabled in both blocks -> output 1s
   Enable1G_bar = 1'b0;
 #10
   {Block2, Block1} = Y;
@@ -123,7 +123,7 @@ begin
   tbassert(Block1 == 8'b11111111, "Test 9");
   tbassert(Block2 == 8'b11111111, "Test 9");
 #0
-  // while disabled in both BLOCKs: all enable inputs transition from previous with null change to
+  // while disabled in both blocks: all enable inputs transition from previous with null change to
   // output 1s
   Enable1C = 1'b1;
   Enable1G_bar = 1'b1;
@@ -143,7 +143,7 @@ begin
   tbassert(Block1 == 8'b11111111, "Test 10");
   tbassert(Block2 == 8'b11111111, "Test 10");
 #0
-  // select Addr 1: from disabled to enabled in both BLOCKs -> second output is 0
+  // select Addr 1: from disabled to enabled in both blocks -> second output is 0
   Enable1C = 1'b1;
   Enable2C_bar = 1'b0;
 #10
@@ -205,7 +205,7 @@ begin
   // end repeat tests
 #0
 
-  // repeat tests: while enabled only in second BLOCK: change to select Addr n-1 from select Addr n
+  // repeat tests: while enabled only in second block: change to select Addr n-1 from select Addr n
 
   Enable1C = 1'b0;
 
diff --git a/source-7400/74160-tb.v b/source-7400/74160-tb.v
index de56591..fa4b41a 100644
--- a/source-7400/74160-tb.v
+++ b/source-7400/74160-tb.v
@@ -177,13 +177,13 @@ begin
   tbassert(Q == 4'b1101, "Test 6");
   tbassert(RCO == 1'b0, "Test 6");
 #2
-  // asynchronous clear from 1101 -> outputs 0, not enough time for clock pulse
+  // asynchronous clear from 1101, not enough time for clock pulse -> outputs 0
   tbassert(Q == 4'b0000, "Test 6");
   tbassert(RCO == 1'b0, "Test 6");
 #150
   Clear_bar = 1'b1;
 #150
-  // asynchronous clear from 0110 with input ENT set -> outputs 0, enough time for clock pulse
+  // asynchronous clear from 0110 with input ENT set, enough time for clock pulse -> outputs 0
   ENT = 1'b1;
   parallel_load_and_tick(4'b0110);
 #50
@@ -197,7 +197,7 @@ begin
 #15
   Clear_bar = 1'b1;
 #15
-  // asynchronous clear from 1001 with input ENT set -> outputs 0, enough time for clock pulse
+  // asynchronous clear from 1001 with input ENT set, enough time for clock pulse -> outputs 0
   ENT = 1'b1;
   parallel_load_and_tick(4'b1001);
 #50
@@ -211,7 +211,7 @@ begin
 #20
   Clear_bar = 1'b1;
 #15
-  // asynchronous clear from 1001 with input ENT set -> outputs 0, not enough time for clock pulse
+  // asynchronous clear from 1001 with input ENT set, not enough time for clock pulse -> outputs 0
   ENT = 1'b1;
   parallel_load_and_tick(4'b1001);
 #20
@@ -250,7 +250,7 @@ begin
   tbassert(Q === 4'bxxxx, "Test 11");
   tbassert(RCO === 1'bx, "Test 11");
 #2
-  // asynchronous clear from initial state -> outputs 0, no clock edge nearby
+  // asynchronous clear from initial state, no clock edge nearby -> outputs 0
   tbassert(Q == 4'b0000, "Test 11");
   tbassert(RCO == 1'b0, "Test 11");
 #75
@@ -274,7 +274,7 @@ begin
   tbassert(Q === 4'bxxxx, "Test 12");
   tbassert(RCO === 1'bx, "Test 12");
 #2
-  // asynchronous clear from initial state -> outputs 0, near or at clock edge
+  // asynchronous clear from initial state, near or at clock edge -> outputs 0
   tbassert(Q == 4'b0000, "Test 12");
   tbassert(RCO == 1'b0, "Test 12");
 #75
diff --git a/source-7400/74161-tb.v b/source-7400/74161-tb.v
index 90d3cb7..876ca18 100644
--- a/source-7400/74161-tb.v
+++ b/source-7400/74161-tb.v
@@ -168,13 +168,13 @@ begin
   tbassert(Q == 3'b011, "Test 5");
   tbassert(RCO == 1'b0, "Test 5");
 #2
-  // asynchronous clear from 011 -> outputs 0, not enough time for clock pulse
+  // asynchronous clear from 011, not enough time for clock pulse -> outputs 0
   tbassert(Q == 3'b000, "Test 5");
   tbassert(RCO == 1'b0, "Test 5");
 #150
   Clear_bar = 1'b1;
 #150
-  // asynchronous clear from 110 with input ENT set -> outputs 0, enough time for clock pulse
+  // asynchronous clear from 110 with input ENT set, enough time for clock pulse -> outputs 0
   ENT = 1'b1;
   parallel_load_and_tick(3'b110);
 #50
@@ -188,7 +188,7 @@ begin
 #15
   Clear_bar = 1'b1;
 #15
-  // asynchronous clear from 111 with input ENT set -> outputs 0, enough time for clock pulse
+  // asynchronous clear from 111 with input ENT set, enough time for clock pulse -> outputs 0
   ENT = 1'b1;
   parallel_load_and_tick(3'b111);
 #50
@@ -202,7 +202,7 @@ begin
 #20
   Clear_bar = 1'b1;
 #15
-  // asynchronous clear from 111 with input ENT set -> outputs 0, not enough time for clock pulse
+  // asynchronous clear from 111 with input ENT set, not enough time for clock pulse -> outputs 0
   ENT = 1'b1;
   parallel_load_and_tick(3'b111);
 #20
@@ -241,7 +241,7 @@ begin
   tbassert(Q === 3'bxxx, "Test 10");
   tbassert(RCO === 1'bx, "Test 10");
 #2
-  // asynchronous clear from initial state -> outputs 0, no clock edge nearby
+  // asynchronous clear from initial state, no clock edge nearby -> outputs 0
   tbassert(Q == 3'b000, "Test 10");
   tbassert(RCO == 1'b0, "Test 10");
 #75
@@ -265,7 +265,7 @@ begin
   tbassert(Q === 3'bxxx, "Test 11");
   tbassert(RCO === 1'bx, "Test 11");
 #2
-  // asynchronous clear from initial state -> outputs 0, near or at clock edge
+  // asynchronous clear from initial state, near or at clock edge -> outputs 0
   tbassert(Q == 3'b000, "Test 11");
   tbassert(RCO == 1'b0, "Test 11");
 #75
diff --git a/source-7400/74266-tb.v b/source-7400/74266-tb.v
index 2af401f..5ebc542 100644
--- a/source-7400/74266-tb.v
+++ b/source-7400/74266-tb.v
@@ -1,5 +1,12 @@
 // Test: Quad 2-input XNOR gate (OC)
 
+// Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR (or XNOR)
+// - this is the behaviour in Verilog for xnor(a, b, ...), and follows the precedent of
+//   3-input XOR gate 741G386
+// - conforms to chaining of XNOR to create arbitrary wider input, e.g. "(A XNOR B) XNOR C"
+// - the alternative behaviour is a "1 and only 1" or "one-hot checker" instead of a
+//   parity checker
+
 module test;
 
 `TBASSERT_METHOD(tbassert)
@@ -30,14 +37,6 @@ begin
   $dumpfile("74266-tb.vcd");
   $dumpvars;
 
-  // Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR
-  //       (or XNOR)
-  // - this is the behaviour in Verilog for xnor(a, b, ...), and follows the precedent of
-  //   3-input XOR gate 741G386
-  // - conforms to chaining of XNOR to create arbitrary wider input, e.g. "(A XNOR B) XNOR C"
-  // - the alternative behaviour is a "1 and only 1" or "one-hot checker" instead of a
-  //   parity checker
-
   // all zeroes -> 1
   Block1 = {WIDTH_IN{1'b0}};
   Block2 = {WIDTH_IN{1'b0}};
diff --git a/source-7400/74266.v b/source-7400/74266.v
index aaffcf4..a7f4a32 100644
--- a/source-7400/74266.v
+++ b/source-7400/74266.v
@@ -1,5 +1,8 @@
 // Quad 2-input XNOR gate (OC)
 
+// Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR (or XNOR)
+// - conforms to chaining of XNOR to create arbitrary wider input, e.g. "(A XNOR B) XNOR C"
+
 module ttl_74266 #(parameter BLOCKS = 4, WIDTH_IN = 2, DELAY_RISE = 0, DELAY_FALL = 0)
 (
   input [BLOCKS*WIDTH_IN-1:0] A_2D,
@@ -13,10 +16,6 @@ integer i;
 
 always @(*)
 begin
-  // Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR
-  //       (or XNOR)
-  // - follows the precedent of 3-input XOR gate 741G386
-  // - conforms to chaining of XNOR to create arbitrary wider input, e.g. "(A XNOR B) XNOR C"
   for (i = 0; i < BLOCKS; i++)
     computed[i] = ~(^A[i]);
 end
diff --git a/source-7400/74352-tb.v b/source-7400/74352-tb.v
index a9feea6..5e6bc2a 100644
--- a/source-7400/74352-tb.v
+++ b/source-7400/74352-tb.v
@@ -44,12 +44,12 @@ begin
 #6
   tbassert(Y_bar == 3'b100, "Test 1");
 #0
-  // select A: disabled in first BLOCK -> output is 1s where disabled
+  // select A: disabled in first block -> output is 1s where disabled
   Enable_bar[0] = 1'b1;
 #6
   tbassert(Y_bar == 3'b101, "Test 2");
 #0
-  // select A: disabled in second BLOCK, enabled in first BLOCK
+  // select A: disabled in second block, enabled in first block
   Enable_bar[0] = 1'b0;
   Enable_bar[1] = 1'b1;
 #6
@@ -61,18 +61,18 @@ begin
 #10
   tbassert(Y_bar == 3'b111, "Test 4");
 #0
-  // select B: enabled in second and third BLOCKs
+  // select B: enabled in second and third blocks
   Enable_bar[1] = 1'b0;
   Enable_bar[2] = 1'b0;
 #10
   tbassert(Y_bar == 3'b001, "Test 5");
 #0
-  // select A: enabled in second and third BLOCKs
+  // select A: enabled in second and third blocks
   Select = 2'b00;
 #10
   tbassert(Y_bar == 3'b101, "Test 6");
 #0
-  // select D: enabled in second and third BLOCKs
+  // select D: enabled in second and third blocks
   Select = 2'b11;
 #10
   tbassert(Y_bar == 3'b011, "Test 7");
@@ -95,12 +95,12 @@ begin
 #10
   tbassert(Y_bar == 3'b000, "Test 10");
 #0
-  // select C: disabled in first BLOCK
+  // select C: disabled in first block
   Enable_bar[0] = 1'b1;
 #6
   tbassert(Y_bar == 3'b001, "Test 11");
 #0
-  // select A: disabled in first and third BLOCKs
+  // select A: disabled in first and third blocks
   Enable_bar[2] = 1'b1;
   Select = 2'b00;
 #10
@@ -170,7 +170,7 @@ begin
 #10
   tbassert(Y_bar == 3'b000, "Test 18");
 #0
-  // while enabled in second and third BLOCKs: change to select A from select B and
+  // while enabled in second and third blocks: change to select A from select B and
   // change to different inputs with null effect on output 0s
   Enable_bar = 3'b001;
 #6
@@ -184,7 +184,7 @@ begin
 #10
   tbassert(Y_bar == 3'b001, "Test 19");
 #0
-  // while enabled in second and third BLOCKs: change back to select B from select A
+  // while enabled in second and third blocks: change back to select B from select A
   Select = 2'b01;
 #10
   tbassert(Y_bar == 3'b111, "Test 20");
diff --git a/source-7400/7486-tb.v b/source-7400/7486-tb.v
index 8187a1a..9e19ece 100644
--- a/source-7400/7486-tb.v
+++ b/source-7400/7486-tb.v
@@ -1,5 +1,12 @@
 // Test: Quad 2-input XOR gate
 
+// Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR
+// - this is the behaviour in Verilog for xor(a, b, ...), and follows the precedent of
+//   3-input XOR gate 741G386
+// - conforms to chaining of XOR to create arbitrary wider input, e.g. "(A XOR B) XOR C"
+// - the alternative behaviour is a "1 and only 1" or "one-hot checker" instead of a
+//   parity checker
+
 module test;
 
 `TBASSERT_METHOD(tbassert)
@@ -30,13 +37,6 @@ begin
   $dumpfile("7486-tb.vcd");
   $dumpvars;
 
-  // Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR
-  // - this is the behaviour in Verilog for xor(a, b, ...), and follows the precedent of
-  //   3-input XOR gate 741G386
-  // - conforms to chaining of XOR to create arbitrary wider input, e.g. "(A XOR B) XOR C"
-  // - the alternative behaviour is a "1 and only 1" or "one-hot checker" instead of a
-  //   parity checker
-
   // all zeroes -> 0
   Block1 = {WIDTH_IN{1'b0}};
   Block2 = {WIDTH_IN{1'b0}};
diff --git a/source-7400/7486.v b/source-7400/7486.v
index 347ad24..ba45119 100644
--- a/source-7400/7486.v
+++ b/source-7400/7486.v
@@ -1,5 +1,8 @@
 // Quad 2-input XOR gate
 
+// Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR
+// - conforms to chaining of XOR to create arbitrary wider input, e.g. "(A XOR B) XOR C"
+
 module ttl_7486 #(parameter BLOCKS = 4, WIDTH_IN = 2, DELAY_RISE = 0, DELAY_FALL = 0)
 (
   input [BLOCKS*WIDTH_IN-1:0] A_2D,
@@ -13,9 +16,6 @@ integer i;
 
 always @(*)
 begin
-  // Note: For WIDTH_IN > 2, this is the "parity checker" interpretation of multi-input XOR
-  // - follows the precedent of 3-input XOR gate 741G386
-  // - conforms to chaining of XOR to create arbitrary wider input, e.g. "(A XOR B) XOR C"
   for (i = 0; i < BLOCKS; i++)
     computed[i] = ^A[i];
 end