diff --git a/.gitattributes b/.gitattributes
index 3ea1f6f..88d050a 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -1,9 +1,9 @@
-*               text=auto
+*              text=auto
 
-.gitattributes  text
-.gitignore      text
-.editorconfig   text
+.gitattributes text
+.gitignore     text
+.editorconfig  text
 
-.gitattributes  export-ignore
-.gitignore      export-ignore
-.travis.yml     export-ignore
+.gitattributes export-ignore
+.gitignore     export-ignore
+.travis.yml    export-ignore
diff --git a/scripts/.editorconfig b/scripts/.editorconfig
index 63249e7..dd5e380 100644
--- a/scripts/.editorconfig
+++ b/scripts/.editorconfig
@@ -5,3 +5,7 @@ charset = utf-8
 end_of_line = lf
 indent_style = tab
 indent_size = 4
+
+[*.json]
+indent_style = space
+indent_size = 2
diff --git a/scripts/package.json b/scripts/package.json
index be798fa..daa7287 100644
--- a/scripts/package.json
+++ b/scripts/package.json
@@ -3,69 +3,15 @@
   "version": "0.9.0",
   "description": "Generates and Validates the IceChips source files",
   "keywords": [
-    "74",
-    "74x",
-    "74xx",
-    "7400",
-    "TTL",
-    "HC",
-    "HCT",
-    "74HC",
-    "74LS",
-    "4000",
-    "4000 Series",
-    "CMOS",
-    "ECL",
-    "Verilog",
-    "iverilog",
-    "Icarus",
-    "Icestorm",
-    "Icestudio",
-    "Simulate",
-    "Simulation",
-    "Model",
-    "Behavioural Model",
-    "Design",
-    "EDA",
-    "EDA Tool",
-    "Free EDA",
-    "Open Source",
-    "FOSS",
-    "Verilog Components",
-    "Verilog Module",
-    "Validated",
-    "Verified",
-    "Collection",
-    "Library",
-    "Cell Library",
-    "Circuit Library",
-    "Logic Family",
-    "Discrete Logic",
-    "Glue Logic",
-    "Logic Circuit",
-    "ALU",
-    "Arithmetic Logic Unit",
-    "SSI",
-    "MSI",
-    "IC",
-    "Chip",
-    "Device",
-    "Hardware",
-    "RTL",
-    "FPGA",
-    "FPGAwars",
-    "IP",
-    "IP Core",
-    "IP Design",
-    "Verification IP",
-    "Test Bench",
-    "Synthesis",
-    "Yosys",
-    "Verilator",
-    "HDL",
-    "VHDL",
-    "Gateware",
-    "OpenCores"
+    "74", "74x", "74xx", "7400", "74181", "TTL", "HC", "HCT", "74HC", "74LS", "CMOS", "ECL",
+    "4000", "4000 Series", "Icestudio", "Icestorm", "Verilog", "iverilog", "Icarus", "Simulate",
+    "Simulation", "Model", "Behavioural Model", "Design", "EDA", "EDA Tool", "Free EDA",
+    "Open Source", "FOSS EDA", "FOSS Logic", "Verilog Components", "Verilog Module", "Validated",
+    "Verified", "Collection", "Library", "Cell Library", "Circuit Library", "Logic Family",
+    "Discrete Logic", "Glue Logic", "Logic Circuit", "ALU", "Arithmetic Logic Unit", "SSI", "MSI",
+    "IC", "Chip", "Device", "Hardware", "RTL", "FPGA", "FPGAwars", "IP", "IP Core", "IP Design",
+    "Verification IP", "Test Bench", "Synthesis", "Yosys", "Verilator", "HDL", "VHDL",
+    "Gateware", "OpenCores"
   ],
   "bugs": "https://github.com/TimRudy/ice-chips-verilog/issues",
   "license": "GPL-3.0-or-later",