How to disable loop optimization during synthesis?

[Arthuuuuroo]

Hello,

I'm trying to use Yosys in order to synthetize a design of ring-oscillator. It is composed of a loop with 1 Nand and 6 inverters.

I have noticed that Yosys synth command is composed of various opt steps. I tried to execute step by step the synth command without this opt steps but it seems that Yosys still optimized my design or just don't understand it anymore because some opt steps seems to be mandatory to synthetize.

My question is how can I perform synthesis without any optimization? I want that yosys don't touch my inverter loop and keep them.

Thanks in advance.

[povik]

Hi Arthuro,

this is better suited under discussions, so I've transferred it.

I have noticed that Yosys synth command is composed of various opt steps. I tried to execute step by step the synth command without this opt steps but it seems that Yosys still optimized my design or just don't understand it anymore because some opt steps seems to be mandatory to synthetize.

Be sure to check out https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/synthesis/index.html and https://www.youtube.com/watch?v=s7KLNb8G_sI if you want to understand more about how the individual passes in Yosys work together.

My question is how can I perform synthesis without any optimization? I want that yosys don't touch my inverter loop and keep them.

You might get there by attaching the (* keep *) attribute on elements of your inverter loop but I'd recommend writing low-level structural Verilog for the oscillator, i.e. directly instancing the technology cells you want connected together.

[Arthuuuuroo]

I tried to use the keep syntax in my code, it seems to work for the moment thanks