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Compile and install yosys 0.40 or yosys 0.47 (I did not try other versions) from the release tarball on Debian GNU/Linux testing on aarch64. I was not able to reproduce the issue using yosys 0.47 (I did not try other versions) on
Debian GNU/Linux testing on amd64.
Try to compile the attached Verilog source via yosys -l icesynth2.yosyslog -p "read_verilog -sv cpu2_nosv.v; synth_ice40 -top cpu -json icesynth2.json"
Given the below this is probably a Yosys bug (not an ABC bug) in that we have prepared the XAIGER input wrong.
ABC: The command has to terminate. Boxes are not in a topological order.
ABC: The following information may help debugging (numbers are 0-based):
ABC: Input 0 of BoxA 379 (1stCI = 872; 1stCO = 1815) has TFI with CI 1005,
ABC: which corresponds to output 0 of BoxB 452 (1stCI = 1005; 1stCO = 2128).
ABC: In a correct topological order, BoxB should precede BoxA.
Version
0.47 (also 0.40)
On which OS did this happen?
Linux
Reproduction Steps
Compile and install yosys 0.40 or yosys 0.47 (I did not try other versions) from the release tarball on Debian GNU/Linux testing on aarch64. I was not able to reproduce the issue using yosys 0.47 (I did not try other versions) on
Debian GNU/Linux testing on amd64.
Try to compile the attached Verilog source via
yosys -l icesynth2.yosyslog -p "read_verilog -sv cpu2_nosv.v; synth_ice40 -top cpu -json icesynth2.json"
cpu2_nosv.v.gz
Expected Behavior
The source gets compiled.
Actual Behavior
I get an error message:
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