read_verilog gives multiple drivers to variables initialized both in declaration and initial

[widlarizer]

Version

Yosys 0.47 (git sha1 647d61dd9, ccache clang++ 16.0.6 -fPIC -O3 -flto=thin)

On which OS did this happen?

Linux

Reproduction Steps

read_verilog a.v; proc -noopt; check

module a;
	integer i = 1'b1;
	initial begin
		i = i + 1'b0;
	end
endmodule

Expected Behavior

The tool evaluates the assignments in some order (Verilog 2005 LRM 6.2.1). For SystemVerilog, the order has to be such that the declaration assignment is evaluated first (SV 2012 LRM 6.8).

Actual Behavior

The tool evaluates both assignments with no concept of sequence, creating conflicting drivers for the variable and a logic loop. This could lead to incorrect synthesis and prevents efficient optimization (see #4782 #4783)