.gitignore

running_dir/*

#############
#FPGA
#############
FPGA/db/.cmp.kpt
FPGA/db/*
FPGA/incremental_db/*
FPGA/output_files/*
FPGA/greybox_tmp/cbx_args.txt
FPGA/CPU_GARAGE.qws

#############
# modelsim generated files
#############
*.swp
*.bak
modelsim/work/*
modelsim/*
target/*
transcript
!modelsim/README*
!modelsim/work/README*
!target/README*
!FPGA/output_files/*.sof
source/lotr/work/_info
source/lotr/work/_lib.qdb
source/lotr/work/_vmake
source/lotr/work/_lib1_5.qtl
source/lotr/work/_lib1_5.qdb
source/lotr/work/_lib1_5.qpg
source/uart_io/pyterminal/src/__pycache__/file_parser.cpython-310.pyc
source/uart_io/work/_info
*.qdb
source/uart_io/work/_lib1_4.qpg
source/uart_io/work/_lib1_4.qtl
source/uart_io/work/_vmake
source/vsim.wlf
*.qpg
*.qtl
source/work/_info
source/work/_vmake
*.do
source/wlfteyyzdd
source/wlfts7gwwf
source/wlftzc8ds5
source/wlftx71fay
source/wlft26at4y
source/wlftc6t7jy
source/wlftdsegq5
source/wlftezmxa0
source/wlftzx8z3h