CR & SR - Control Registers & Status Registers

[amichai-bd]

In the CR Space (which we should probably rename - we cant call it CSR),
We should add 2 types of register:
CR - control registers
SR - Status registers

The CR will control and config the core/threads - mainly writing from the "fabric/io/ROM" (not the core itself).
The SR will indicate the status of the core/thread - mainly writing from the Core itself. (can be used for DFD -Design For Debug)

Example:

CR:

• thread_id
• core_id
• en_pc_thread_<#>
• rst_pc_thread_<#>
• en_pc_core
• rst_pc_core

SR:

• thread_<#>_pc
• thead_<#>_frozen
• core_frozen
• err_miss_aligh_data_access_thread_<#>
• err_sp_out_of_range

@DL8 - You are welcome to add and document in the sw_arch any CR/SR you need/want so the HW will need to be aligned to your specifications.
and let us suggest a new name for the CR region. "Memory-mapped control and Status"?
or "memory-mapped indications"

I'm trying to avoid "CSR" due to RISCV using that terminology for "Zicsr" Extention.