Exception codes should be aligned with RISC-V spec

[DL8]

RISC-V privileged arch spec defines the mcause register to hold the exception code. To be more future-compatible, the value in GPC_CR_THREAD<i>_EXCEPTION_CODE in case of an exception should be a standard-defined exception cause (see table 3.6 in section 3.1.16 of the privileged instruction spec). For example, illegal instruction is code 2 and mistaligned load is 4

[amichai-bd]

Sure.
Let's try to keep it as close to the privileged spec - but we are not necessary must be aligned and support all exception codes and events.
When we document and write the RTL code for the "_EXCEPTION_CODE " we will use the mcause register as a reference.

[DL8]

Of course, I don't expect everything to be supported. I updated the HW-SW interface with a reference to mcause for exception codes. The table is left in case custom exceptions are needed (the spec reserves some codes for custom use)