axi_ad9361 : add non DPA mode support

For Intel projects: In cases where the clock of source synchronous interface is not routed through a clock capable pin the DPA receive mode can't be used. Instead the clock will be routed through a clock buffer from an IO to the clock tree and from there to the IOPLL.
analogdevicesinc · Feb 24, 2020 · 00166d8 · 00166d8
1 parent 0a34f82
commit 00166d8
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Showing 6 changed files with 84 additions and 30 deletions.
diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
@@ -67,7 +67,8 @@ module axi_ad9361 #(
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
   parameter   MIMO_ENABLE = 0,
   parameter   USE_SSI_CLK = 1,
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200,
+  parameter   RX_NODPA = 0) (
 
   // physical interface (receive-lvds)
 
@@ -400,7 +401,8 @@ module axi_ad9361 #(
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
     .CLK_DESKEW (MIMO_ENABLE),
     .USE_SSI_CLK (USE_SSI_CLK),
-    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
+    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
+    .RX_NODPA (RX_NODPA))
   i_dev_if (
     .rx_clk_in_p (rx_clk_in_p),
     .rx_clk_in_n (rx_clk_in_n),

diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -70,6 +70,7 @@ ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0
 ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
 ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
 ad_ip_parameter MIMO_ENABLE INTEGER 0
+ad_ip_parameter RX_NODPA INTEGER 0
 
 adi_add_auto_fpga_spec_params
 
@@ -178,21 +179,24 @@ proc axi_ad9361_elab {} {
   if {$m_fpga_technology == 103} {
 
     add_hdl_instance axi_ad9361_serdes_clk intel_serdes
-    set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} $m_fpga_technology
+    set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} {Arria 10}
     set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK}
     set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1}
     set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4}
     set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0}
 
+    set rx_serdes_mode IN
+    if {$rx_nodpa == 1} {set rx_serdes_mode IN_NODPA}
+
     add_hdl_instance axi_ad9361_serdes_in intel_serdes
-    set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} $m_fpga_technology
-    set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN}
+    set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} {Arria 10}
+    set_instance_parameter_value axi_ad9361_serdes_in {MODE} $rx_serdes_mode
     set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1}
     set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4}
     set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0}
 
     add_hdl_instance axi_ad9361_serdes_out intel_serdes
-    set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} $m_fpga_technology
+    set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} {Arria 10}
     set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT}
     set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1}
     set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4}
@@ -203,6 +207,10 @@ proc axi_ad9361_elab {} {
     set_instance_parameter_value axi_ad9361_data_out {PIN_TYPE_GUI} {Output}
     set_instance_parameter_value axi_ad9361_data_out {SIZE} {1}
     set_instance_parameter_value axi_ad9361_data_out {gui_io_reg_mode} {DDIO}
+
+    add_hdl_instance clk_buffer altclkctrl
+    set_instance_parameter_value clk_buffer {DEVICE_FAMILY} {Arria 10}
+
   }
 
   add_interface device_if conduit end

diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl
@@ -102,6 +102,8 @@ set_property value "ACTIVE_HIGH" $reset_polarity
 
 ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
 
+ipgui::remove_param -component [ipx::current_core] [ipgui::get_guiparamspec -name "RX_NODPA" -component [ipx::current_core]]
+
 adi_add_auto_fpga_spec_params
 ipx::create_xgui_files [ipx::current_core]
 

diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if.v
@@ -44,7 +44,8 @@ module axi_ad9361_lvds_if #(
   // Dummy parameters, required keep the code consistency(used on Xilinx)
   parameter   USE_SSI_CLK = 1,
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
-  parameter   DELAY_REFCLK_FREQUENCY = 0) (
+  parameter   DELAY_REFCLK_FREQUENCY = 0,
+  parameter   RX_NODPA = 0) (
 
   // physical interface (receive)
 
@@ -528,7 +529,9 @@ endgenerate
 
   generate
   if (FPGA_TECHNOLOGY == ARRIA10) begin
-  axi_ad9361_lvds_if_10 i_axi_ad9361_lvds_if_10 (
+  axi_ad9361_lvds_if_10 #(
+    .RX_NODPA (RX_NODPA))
+  i_axi_ad9361_lvds_if_10 (
     .rx_clk_in_p (rx_clk_in_p),
     .rx_clk_in_n (rx_clk_in_n),
     .rx_frame_in_p (rx_frame_in_p),

diff --git a/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v b/library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
@@ -35,7 +35,9 @@
 
 `timescale 1ns/100ps
 
-module axi_ad9361_lvds_if_10 (
+module axi_ad9361_lvds_if_10  #(
+
+  parameter   RX_NODPA = 0) (
 
   // physical interface (receive)
 
@@ -106,6 +108,7 @@ module axi_ad9361_lvds_if_10 (
   wire                lvds_clk;
   wire                lvds_loaden;
   wire    [ 7:0]      lvds_phase;
+  wire                rx_clk;
 
   // pll reset
 
@@ -197,27 +200,62 @@ module axi_ad9361_lvds_if_10 (
   genvar i;
   generate
   for (i = 0; i < 6; i = i + 1) begin: g_rx_data
-  axi_ad9361_serdes_in i_rx_data (
-    .data_in_export (rx_data_in_p[i]),
-    .clk_export (lvds_clk),
-    .loaden_export (lvds_loaden),
-    .div_clk_export (clk),
-    .hs_phase_export (lvds_phase),
-    .locked_export (rx_data_locked_s[i]),
-    .data_s_export (rx_data_s[((i*4)+3):(i*4)]),
-    .delay_locked_export (rx_delay_locked_s[i]));
+    if (RX_NODPA == 0) begin
+      axi_ad9361_serdes_in i_rx_data (
+        .data_in_export (rx_data_in_p[i]),
+        .clk_export (lvds_clk),
+        .loaden_export (lvds_loaden),
+        .div_clk_export (clk),
+        .hs_phase_export (lvds_phase),
+        .locked_export (rx_data_locked_s[i]),
+        .data_s_export (rx_data_s[((i*4)+3):(i*4)]),
+        .delay_locked_export (rx_delay_locked_s[i]));
+    end else begin
+      axi_ad9361_serdes_in i_rx_data (
+        .data_in_export (rx_data_in_p[i]),
+        .clk_export (lvds_clk),
+        .loaden_export (lvds_loaden),
+        .div_clk_export (clk),
+        .data_s_export (rx_data_s[((i*4)+3):(i*4)]));
+
+      assign rx_data_locked_s[i] = 1'b1;
+      assign rx_delay_locked_s[i] = 1'b1;
+
+    end
   end
-  endgenerate
 
-  axi_ad9361_serdes_in i_rx_frame (
-    .data_in_export (rx_frame_in_p),
-    .clk_export (lvds_clk),
-    .loaden_export (lvds_loaden),
-    .div_clk_export (clk),
-    .hs_phase_export (lvds_phase),
-    .locked_export (rx_data_locked_s[6]),
-    .data_s_export (rx_data_s[27:24]),
-    .delay_locked_export (rx_delay_locked_s[6]));
+    if (RX_NODPA == 0) begin
+
+      axi_ad9361_serdes_in i_rx_frame (
+        .data_in_export (rx_frame_in_p),
+        .clk_export (lvds_clk),
+        .loaden_export (lvds_loaden),
+        .div_clk_export (clk),
+        .hs_phase_export (lvds_phase),
+        .locked_export (rx_data_locked_s[6]),
+        .data_s_export (rx_data_s[27:24]),
+        .delay_locked_export (rx_delay_locked_s[6]));
+
+     assign rx_clk = rx_clk_in_p;
+
+    end else begin
+
+      axi_ad9361_serdes_in i_rx_frame (
+        .data_in_export (rx_frame_in_p),
+        .clk_export (lvds_clk),
+        .loaden_export (lvds_loaden),
+        .div_clk_export (clk),
+        .data_s_export (rx_data_s[27:24]) );
+
+      assign rx_data_locked_s[6] = 1'b1;
+      assign rx_delay_locked_s[6] = 1'b1;
+
+      clk_buffer clk_buf (
+        .inclk (rx_clk_in_p),
+        .outclk (rx_clk));
+
+    end
+  endgenerate
 
   generate
   for (i = 0; i < 6; i = i + 1) begin: g_tx_data
@@ -256,7 +294,7 @@ module axi_ad9361_lvds_if_10 (
 
   axi_ad9361_serdes_clk i_clk (
     .rst_reset (pll_rst),
-    .ref_clk_clk (rx_clk_in_p),
+    .ref_clk_clk (rx_clk),
     .locked_export (locked_s),
     .hs_phase_phout (lvds_phase),
     .hs_clk_lvds_clk (lvds_clk),

diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
@@ -42,7 +42,8 @@ module axi_ad9361_lvds_if #(
   parameter   IO_DELAY_GROUP = "dev_if_delay_group",
   parameter   CLK_DESKEW = 0,
   parameter   USE_SSI_CLK = 1,
-  parameter   DELAY_REFCLK_FREQUENCY = 200) (
+  parameter   DELAY_REFCLK_FREQUENCY = 200,
+  parameter   RX_NODPA = 0) (
 
   // physical interface (receive)