Skip to content

Commit

Permalink
axi_ad9371: Updates for ad_dds phase acc wrapper
Browse files Browse the repository at this point in the history
  • Loading branch information
@AndreiGrozav
AndreiGrozav committed Jul 18, 2018
1 parent 42abe0c commit 25dbca7
Show file tree
Hide file tree
Showing 6 changed files with 48 additions and 80 deletions.
3 changes: 3 additions & 0 deletions library/axi_ad9371/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,9 @@ LIBRARY_NAME := axi_ad9371
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
Expand All @@ -28,6 +30,7 @@ GENERIC_DEPS += axi_ad9371_rx_os.v
GENERIC_DEPS += axi_ad9371_tx.v
GENERIC_DEPS += axi_ad9371_tx_channel.v

XILINX_DEPS += ../common/ad_dds_2.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
Expand Down
6 changes: 4 additions & 2 deletions library/axi_ad9371/axi_ad9371.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ module axi_ad9371 #(
parameter ID = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0,
parameter ADC_DATAPATH_DISABLE = 0) (

Expand Down Expand Up @@ -263,8 +264,9 @@ module axi_ad9371 #(

axi_ad9371_tx #(
.ID (ID),
.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.dac_rst (dac_rst),
Expand Down
1 change: 1 addition & 0 deletions library/axi_ad9371/axi_ad9371_hw.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/alt
add_fileset_file ad_dds_cordic_pipe.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v
add_fileset_file ad_dds_sine_cordic.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine_cordic.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_2.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_2.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
Expand Down
1 change: 1 addition & 0 deletions library/axi_ad9371/axi_ad9371_ip.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ adi_ip_files axi_ad9371 [list \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
Expand Down
25 changes: 15 additions & 10 deletions library/axi_ad9371/axi_ad9371_tx.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,9 @@
module axi_ad9371_tx #(

parameter ID = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (

// dac interface
Expand Down Expand Up @@ -131,8 +132,9 @@ module axi_ad9371_tx #(
axi_ad9371_tx_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_TYPE (DDS_TYPE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
Expand Down Expand Up @@ -162,8 +164,9 @@ module axi_ad9371_tx #(
axi_ad9371_tx_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_TYPE (DDS_TYPE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
Expand Down Expand Up @@ -193,8 +196,9 @@ module axi_ad9371_tx #(
axi_ad9371_tx_channel #(
.CHANNEL_ID (2),
.Q_OR_I_N (0),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_TYPE (DDS_TYPE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
Expand Down Expand Up @@ -224,8 +228,9 @@ module axi_ad9371_tx #(
axi_ad9371_tx_channel #(
.CHANNEL_ID (3),
.Q_OR_I_N (1),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_TYPE (DDS_TYPE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
Expand Down
92 changes: 24 additions & 68 deletions library/axi_ad9371/axi_ad9371_tx_channel.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,9 @@ module axi_ad9371_tx_channel #(

parameter CHANNEL_ID = 32'h0,
parameter Q_OR_I_N = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (

// dac interface
Expand Down Expand Up @@ -75,18 +76,10 @@ module axi_ad9371_tx_channel #(
// internal registers

reg [31:0] dac_pat_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [31:0] dac_dds_data = 'd0;

// internal signals

wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [31:0] dac_dds_data_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
Expand Down Expand Up @@ -141,7 +134,7 @@ module axi_ad9371_tx_channel #(
4'h3: dac_data_iq_out <= 32'd0;
4'h2: dac_data_iq_out <= dac_data_in;
4'h1: dac_data_iq_out <= dac_pat_data;
default: dac_data_iq_out <= dac_dds_data;
default: dac_data_iq_out <= dac_dds_data_s;
endcase
end

Expand All @@ -153,64 +146,27 @@ module axi_ad9371_tx_channel #(

// dds

always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[14:0], 1'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[14:0], 1'd0};
dac_dds_data <= 32'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= {dac_dds_data_1_s, dac_dds_data_0_s};
end
end

// dds

generate
if (DATAPATH_DISABLE == 1) begin

assign dac_dds_data_0_s = 16'd0;
assign dac_dds_data_1_s = 16'd0;

end else begin

ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_0 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));

ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_1 (
.DISABLE (DATAPATH_DISABLE),
.DDS_DW (16),
.PHASE_DW (16),
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (2))
i_dds (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
.dac_valid (1'b1),
.tone_1_scale (dac_dds_scale_1_s),
.tone_2_scale (dac_dds_scale_2_s),
.tone_1_init_offset (dac_dds_init_1_s),
.tone_2_init_offset (dac_dds_init_2_s),
.tone_1_freq_word (dac_dds_incr_1_s),
.tone_2_freq_word (dac_dds_incr_2_s),
.dac_dds_data (dac_dds_data_s));

end
endgenerate

// single channel processor

Expand Down Expand Up @@ -254,7 +210,7 @@ module axi_ad9371_tx_channel #(
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));

endmodule

// ***************************************************************************
Expand Down

0 comments on commit 25dbca7

Please sign in to comment.