util_axis_fifo: Refactoring

Refactor the AXI4 stream FIFO implementation. - Define a single address generator which supports both single and double clock mode. (synchronous and asynchronous) - Fix FIFO status bits (empty/full). NOTE: In asynchronous mode the flags can have a several clock cycle delay in function of the upstream/downstream clock ratio. - In synchronous none FIFO mode (ADDRESS_WIDTH==0), the module acts as an AXI4 stream pipeline.
analogdevicesinc · Dec 4, 2020 · 5ac7283 · 5ac7283
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diff --git a/library/util_axis_fifo/Makefile b/library/util_axis_fifo/Makefile
@@ -6,9 +6,8 @@
 LIBRARY_NAME := util_axis_fifo
 
 GENERIC_DEPS += ../common/ad_mem.v
-GENERIC_DEPS += address_gray.v
-GENERIC_DEPS += address_gray_pipelined.v
-GENERIC_DEPS += address_sync.v
+GENERIC_DEPS += ../common/ad_mem_asym.v
+GENERIC_DEPS += util_axis_fifo_address_generator.v
 GENERIC_DEPS += util_axis_fifo.v
 
 XILINX_DEPS += util_axis_fifo_ip.tcl

diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v
diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v