From 677c154134e4d136ccb551191a0f73fafa1c5633 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 16 Feb 2021 12:50:09 +0000 Subject: [PATCH] adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings Set the same inter clock skew characteristics as used in LVDS mode. The physical lanes/routes are common on both modes. --- projects/adrv9001/zcu102/cmos_constr.xdc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/projects/adrv9001/zcu102/cmos_constr.xdc b/projects/adrv9001/zcu102/cmos_constr.xdc index 317e04286e..84825bb745 100644 --- a/projects/adrv9001/zcu102/cmos_constr.xdc +++ b/projects/adrv9001/zcu102/cmos_constr.xdc @@ -47,8 +47,10 @@ create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_in_p] create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_in_p] create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_in_p] -set_clock_latency -source -early 2 [get_clocks rx1_dclk_out] -set_clock_latency -source -early 2 [get_clocks rx2_dclk_out] +set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out] +set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out] + +set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out] +set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out] + -set_clock_latency -source -late 5 [get_clocks rx1_dclk_out] -set_clock_latency -source -late 5 [get_clocks rx2_dclk_out]