From 6b7a46410c13013c647467247ee7ad028fcf18fc Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 11 Sep 2015 10:46:55 +0200
Subject: [PATCH] axi_dmac: address_generator: Remove resets from data path

There is no need to reset the data path in the address generator. The
values of the register on the data path are not used until they have been
explicitly initialized. Removing the reset simplifies the structure and
reduces the fan-out of the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_dmac/address_generator.v | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/library/axi_dmac/address_generator.v b/library/axi_dmac/address_generator.v
index 372ed5fc56..c9bcf2f109 100644
--- a/library/axi_dmac/address_generator.v
+++ b/library/axi_dmac/address_generator.v
@@ -109,6 +109,7 @@ end
 
 always @(posedge clk) begin
   if (addr_valid == 1'b0) begin
+    last <= eot;
     if (eot == 1'b1)
       length <= last_burst_len;
     else
@@ -117,17 +118,16 @@ always @(posedge clk) begin
 end
 
 always @(posedge clk) begin
-  if (resetn == 1'b0) begin
-    last <= 1'b0;
-  end else if (addr_valid == 1'b0) begin
-    last <= eot;
+  if (req_ready == 1'b1) begin
+    address <= req_address;
+    last_burst_len <= req_last_burst_length;
+  end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
+    address <= address + MAX_BEATS_PER_BURST;
   end
 end
 
 always @(posedge clk) begin
   if (resetn == 1'b0) begin
-    address <= 'h00;
-    last_burst_len <= 'h00;
     req_ready <= 1'b1;
     addr_valid <= 1'b0;
   end else begin
@@ -135,13 +135,10 @@ always @(posedge clk) begin
       req_ready <= 1'b1;
     end else if (req_ready) begin
       if (req_valid && enable) begin
-        address <= req_address;
         req_ready <= 1'b0;
-        last_burst_len <= req_last_burst_length;
       end
     end else begin
       if (addr_valid && addr_ready) begin
-        address <= address + MAX_BEATS_PER_BURST;
         addr_valid <= 1'b0;
         if (last)
           req_ready <= 1'b1;