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axi_dmac: Fix debug ID order
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Commit e6aacd2 ("axi_dmac: Better support debug IDs when ID_WIDTH !=
3") managed to get the order of the IDs in the debug register wrong.
Restore the original order.

Signed-off-by: Lars-Peter Clausen <[email protected]>
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larsclausen committed May 4, 2018
1 parent 00faa5a commit 7a804c1
Showing 1 changed file with 6 additions and 6 deletions.
12 changes: 6 additions & 6 deletions library/axi_dmac/axi_dmac.v
Original file line number Diff line number Diff line change
Expand Up @@ -340,15 +340,15 @@ wire up_dma_req_sync_transfer_start;
wire up_dma_req_last;

assign dbg_ids0 = {
{DBG_ID_PADDING{1'b0}}, dest_data_id,
{DBG_ID_PADDING{1'b0}}, dest_response_id,
{DBG_ID_PADDING{1'b0}}, dest_data_id,
{DBG_ID_PADDING{1'b0}}, dest_address_id,
{DBG_ID_PADDING{1'b0}}, dest_request_id
};

assign dbg_ids1 = {
{DBG_ID_PADDING{1'b0}}, src_data_id,
{DBG_ID_PADDING{1'b0}}, src_response_id,
{DBG_ID_PADDING{1'b0}}, src_data_id,
{DBG_ID_PADDING{1'b0}}, src_address_id,
{DBG_ID_PADDING{1'b0}}, src_request_id
};
Expand Down Expand Up @@ -568,12 +568,12 @@ dmac_request_arb #(

// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_data_id),
.dbg_dest_data_id(dest_address_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_data_id),
.dbg_src_data_id(src_address_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status)
);
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