Add ad_dds.v

It will act as a wrapper for the previous dds modules(phase to angle conv.)
this module will furthermore contain the phase accumulator logic.

library/common/ad_dds.v

@@ -0,0 +1,142 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+// single channel dds (dual tone)
+module ad_dds #(
+
+  parameter DISABLE = 0,
+  // range 8-24
+  parameter DDS_DW = 16,
+  // range 8-16 (FIX ME)
+  parameter PHASE_DW = 16,
+  // set 1 for CORDIC or 2 for Polynomial
+  parameter DDS_TYPE = 1,
+  // range 8-24
+  parameter CORDIC_DW = 16,
+  // range 8-24 (make sure CORDIC_PHASE_DW < CORDIC_DW)
+  parameter CORDIC_PHASE_DW = 16,
+  // the clock radtio between the device clock(sample rate) and the dac_core clock
+  parameter CLK_RATIO = 1) (
+
+  // interface
+
+  input                                 clk,
+  input                                 rst,
+  input                                 dac_dds_format,
+  input                                 dac_data_sync,
+  input       [                  15:0]  tone_1_scale,
+  input       [                  15:0]  tone_2_scale,
+  input       [                  15:0]  tone_1_init_offset,
+  input       [                  15:0]  tone_2_init_offset,
+  input       [          PHASE_DW-1:0]  tone_1_freq_word,
+  input       [          PHASE_DW-1:0]  tone_2_freq_word,
+  output  reg [DDS_DW*CLK_RATIO-1:0]  dac_dds_data
+  );
+
+  // internal registers
+
+  reg         [PHASE_DW-1:0]  dac_dds_incr_0 = 'd0;
+  reg         [PHASE_DW-1:0]  dac_dds_incr_1 = 'd0;
+
+  // dds solution
+
+  genvar i;
+
+  generate
+
+    if (DISABLE == 1) begin
+      always @(posedge clk) begin
+        dac_dds_data <= {(DDS_DW*CLK_RATIO-1){1'b0}};
+      end
+    end else begin
+      // enable dds
+
+      reg  [PHASE_DW-1:0]  dac_dds_phase_0[1:CLK_RATIO];
+      reg  [PHASE_DW-1:0]  dac_dds_phase_1[1:CLK_RATIO];
+      wire [  DDS_DW-1:0]  dac_dds_data_s[1:CLK_RATIO];
+
+      for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase
+
+        always @(posedge clk) begin
+             if (dac_data_sync == 1'b1) begin
+               dac_dds_data[DDS_DW*i-1:DDS_DW*(i-1)] <= {(DDS_DW-1){1'b0}};
+             end else begin
+               dac_dds_data[DDS_DW*i-1:DDS_DW*(i-1)] <= dac_dds_data_s[i];
+             end
+        end
+
+        //  phase accumulator
+        always @(posedge clk) begin
+          // phase incrementaion accross 2^N (0<N<5) phase clock ratio
+          dac_dds_incr_0 <= tone_1_freq_word * CLK_RATIO;
+          dac_dds_incr_1 <= tone_2_freq_word * CLK_RATIO;
+
+            if (dac_data_sync == 1'b1) begin
+              if (i == 1) begin
+                dac_dds_phase_0[1] <= tone_1_init_offset;
+                dac_dds_phase_1[1] <= tone_2_init_offset;
+              end else begin
+                dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word;
+                dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word;
+              end
+            end else begin
+              dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0;
+              dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1;
+            end
+        end
+
+        // phase to amplitude convertor
+         ad_dds_2 #(
+           .DDS_DW (DDS_DW),
+           .DDS_TYPE (DDS_TYPE),
+           .CORDIC_DW (CORDIC_DW),
+           .CORDIC_PHASE_DW (CORDIC_PHASE_DW))
+         i_dds_2 (
+          .clk (clk),
+          .dds_format (dac_dds_format),
+          .dds_phase_0 (dac_dds_phase_0[i]),
+          .dds_scale_0 (tone_1_scale),
+          .dds_phase_1 (dac_dds_phase_1[i]),
+          .dds_scale_1 (tone_2_scale),
+          .dds_data (dac_dds_data_s[i])
+        );
+
+      end
+    end
+  endgenerate
+
+endmodule

library/common/ad_dds_1.v

@@ -57,25 +57,22 @@ module ad_dds_1 #(
 
   // internal signals
 
-  wire    [  DDS_D_DW-1:0] sine_s;
-  wire    [           3:0] zeros;
+  wire    [ DDS_D_DW-1:0] sine_s;
   wire    [DDS_D_DW+17:0] s1_data_s;
 
-  assign zeros = 0;
-
   // sine
 
   generate
     if (DDS_TYPE == DDS_CORDIC_TYPE) begin
 
       // the cordic module input angle width must be equal with it's width
       // at this point the phase is only generated on 16 bits
-      wire    [CORDIC_PHASE_DW:0] angle_s;
+      wire    [DDS_P_DW-1:0] angle_s;
 
-      if (CORDIC_PHASE_DW >= 16) begin
-        assign angle_s = {angle,{CORDIC_PHASE_DW-15{1'b0}}};
+      if (DDS_P_DW >= 16) begin
+        assign angle_s = {angle,{DDS_P_DW-15{1'b0}}};
       end else begin
-        assign angle_s = {angle[15:16-CORDIC_PHASE_DW],1'b0};
+        assign angle_s = {angle[15:16-DDS_P_DW],1'b0};
       end
 
       ad_dds_sine_cordic #(
@@ -84,7 +81,7 @@ module ad_dds_1 #(
         .DELAY_DW(1))
       i_dds_sine (
         .clk (clk),
-        .angle (angle),
+        .angle (angle_s),
         .sine (sine_s),
         .cosine (),
         .ddata_in (1'b0),

library/common/ad_dds_2.v

@@ -35,7 +35,7 @@
 
 `timescale 1ns/100ps
 
-module ad_dds #(
+module ad_dds_2 #(
 
   // Disable DDS
   parameter   DISABLE = 0,
@@ -124,8 +124,8 @@ module ad_dds #(
 
        ad_dds_1 #(
          .DDS_TYPE(DDS_TYPE),
-         .CORDIC_DW(CORDIC_DW),
-         .CORDIC_PHASE_DW(CORDIC_PHASE_DW))
+         .DDS_D_DW(CORDIC_DW),
+         .DDS_P_DW(CORDIC_PHASE_DW))
        i_dds_1_0 (
          .clk (clk),
          .angle (dds_phase_0),
@@ -136,8 +136,8 @@ module ad_dds #(
 
        ad_dds_1 #(
          .DDS_TYPE(DDS_TYPE),
-         .CORDIC_DW(CORDIC_DW),
-         .CORDIC_PHASE_DW(CORDIC_PHASE_DW))
+         .DDS_D_DW(DDS_D_DW),
+         .DDS_P_DW(DDS_P_DW))
        i_dds_1_1 (
          .clk (clk),
          .angle (dds_phase_1),