axi_dmac: TLAST support for 2d transfers

In MM2S applications like video DMA it is useful to mark the end of the stream with the TLAST. The change enables the generation of the TLAST on the last beat of the last row of the 2d transfer.
analogdevicesinc · Jul 13, 2018 · e79992f · e79992f
1 parent c5b62a0
commit e79992f
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Showing 2 changed files with 9 additions and 2 deletions.
diff --git a/library/axi_dmac/2d_transfer.v b/library/axi_dmac/2d_transfer.v
@@ -54,13 +54,15 @@ module dmac_2d_transfer #(
   input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
   input req_sync_transfer_start,
   output reg req_eot,
+  input req_last,
 
   output reg out_req_valid,
   input out_req_ready,
   output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
   output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
   output [DMA_LENGTH_WIDTH-1:0] out_req_length,
   output reg out_req_sync_transfer_start,
+  output out_req_last,
   input out_eot
 );
 
@@ -71,6 +73,8 @@ reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
 reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
 reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
 
+reg gen_last = 'h0;
+
 reg [1:0] req_id = 'h00;
 reg [1:0] eot_id = 'h00;
 reg [3:0] last_req = 'h00;
@@ -116,6 +120,7 @@ always @(posedge req_aclk) begin
     dest_stride <= req_dest_stride;
     src_stride <= req_src_stride;
     out_req_sync_transfer_start <= req_sync_transfer_start;
+    gen_last <= req_last;
   end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
     dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
     src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
@@ -140,4 +145,6 @@ always @(posedge req_aclk) begin
   end
 end
 
+assign out_req_last = out_last & gen_last;
+
 endmodule
diff --git a/library/axi_dmac/axi_dmac_transfer.v b/library/axi_dmac/axi_dmac_transfer.v
@@ -257,18 +257,18 @@ dmac_2d_transfer #(
   .req_dest_stride (req_dest_stride),
   .req_src_stride (req_src_stride),
   .req_sync_transfer_start (req_sync_transfer_start),
+  .req_last (req_last),
 
   .out_req_valid (dma_req_valid),
   .out_req_ready (dma_req_ready),
   .out_req_dest_address (dma_req_dest_address),
   .out_req_src_address (dma_req_src_address),
   .out_req_length (dma_req_length),
   .out_req_sync_transfer_start (dma_req_sync_transfer_start),
+  .out_req_last (dma_req_last),
   .out_eot (dma_req_eot)
 );
 
-assign dma_req_last = 1'b0;
-
 end else begin
 
 /* Request */