axi_dmac: Reduce the width of ID signals to minimum

Reduce the width of ID signals to avoid size mismatches in Arria 10 SoC
projects where the ID width of the hard IP is 4.
The width of ID that reaches the slave can be increased by the interconnect if
multiple masters access the slave so we end up with mismatches.

Since these signals are unused it is safe to reduce them to minimum width and
let the interconnect zero-extend them as required.

library/axi_dmac/axi_dmac.v

@@ -54,8 +54,8 @@ module axi_dmac #(
   parameter DMA_AXI_ADDR_WIDTH = 32,
   parameter MAX_BYTES_PER_BURST = 128,
   parameter FIFO_SIZE = 8, // In bursts
-  parameter AXI_ID_WIDTH_SRC = 4,
-  parameter AXI_ID_WIDTH_DEST = 4,
+  parameter AXI_ID_WIDTH_SRC = 1,
+  parameter AXI_ID_WIDTH_DEST = 1,
   parameter DISABLE_DEBUG_REGISTERS = 0,
   parameter ENABLE_DIAGNOSTICS_IF = 0)(
   // Slave AXI interface

library/axi_dmac/axi_dmac_hw.tcl

@@ -366,13 +366,13 @@ proc add_axi_master_interface {axi_type port suffix} {
   # Some signals are mandatory in Altera's implementation of AXI3
   # awid, awlock, wid, bid, arid, arlock, rid, rlast
   # Hide them in AXI4
-  add_interface_port $port ${port}_awid awid Output 4
+  add_interface_port $port ${port}_awid awid Output 1
   add_interface_port $port ${port}_awlock awlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
-  add_interface_port $port ${port}_wid wid Output 4
-  add_interface_port $port ${port}_arid arid Output 4
+  add_interface_port $port ${port}_wid wid Output 1
+  add_interface_port $port ${port}_arid arid Output 1
   add_interface_port $port ${port}_arlock arlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
-  add_interface_port $port ${port}_rid rid Input 4
-  add_interface_port $port ${port}_bid bid Input 4
+  add_interface_port $port ${port}_rid rid Input 1
+  add_interface_port $port ${port}_bid bid Input 1
   add_interface_port $port ${port}_rlast rlast Input 1
   if {$axi_type == "axi4"} {
     set_port_property ${port}_awid TERMINATION true