library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer

Update the file according to HDL guideline. Replace all occurrences of 2d_transfer with dmac_2d_transfer. Update axi_dmac/Makefile.
analogdevicesinc · Apr 1, 2022 · fe713a5 · fe713a5
1 parent d9ec446
commit fe713a5
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diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
@@ -8,7 +8,6 @@ LIBRARY_NAME := axi_dmac
 
 GENERIC_DEPS += ../common/ad_mem_asym.v
 GENERIC_DEPS += ../common/up_axi.v
-GENERIC_DEPS += 2d_transfer.v
 GENERIC_DEPS += address_generator.v
 GENERIC_DEPS += axi_dmac.v
 GENERIC_DEPS += axi_dmac_burst_memory.v
@@ -24,6 +23,7 @@ GENERIC_DEPS += data_mover.v
 GENERIC_DEPS += dest_axi_mm.v
 GENERIC_DEPS += dest_axi_stream.v
 GENERIC_DEPS += dest_fifo_inf.v
+GENERIC_DEPS += dmac_2d_transfer.v
 GENERIC_DEPS += inc_id.vh
 GENERIC_DEPS += request_arb.v
 GENERIC_DEPS += request_generator.v

diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl
@@ -37,7 +37,7 @@ ad_ip_files axi_dmac [list \
   request_generator.v \
   response_handler.v \
   axi_register_slice.v \
-  2d_transfer.v \
+  dmac_2d_transfer.v \
   dest_axi_mm.v \
   dest_axi_stream.v \
   dest_fifo_inf.v \

diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl
@@ -25,7 +25,7 @@ adi_ip_files axi_dmac [list \
   "request_generator.v" \
   "response_handler.v" \
   "axi_register_slice.v" \
-  "2d_transfer.v" \
+  "dmac_2d_transfer.v" \
   "dest_axi_mm.v" \
   "dest_axi_stream.v" \
   "dest_fifo_inf.v" \

diff --git a/library/axi_dmac/2d_transfer.v → library/axi_dmac/dmac_2d_transfer.v b/library/axi_dmac/2d_transfer.v → library/axi_dmac/dmac_2d_transfer.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -41,7 +41,7 @@ module dmac_2d_transfer #(
   parameter DMA_LENGTH_WIDTH = 24,
   parameter BYTES_PER_BURST_WIDTH = 7,
   parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
-  parameter BYTES_PER_BEAT_WIDTH_DEST = 3)(
+  parameter BYTES_PER_BEAT_WIDTH_DEST = 3) (
 
   input req_aclk,
   input req_aresetn,
@@ -78,116 +78,120 @@ module dmac_2d_transfer #(
   input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length,
   input out_response_partial,
   input out_response_valid,
-  output reg out_response_ready = 1'b1
+  output reg out_response_ready = 1'b1);
 
-);
+  // internal registers
 
-reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
-reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
-reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;
-reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
-reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
-reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
+  reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
+  reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
+  reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;
+  reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
+  reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
+  reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
 
-reg gen_last = 'h0;
+  reg gen_last = 'h0;
 
-reg [1:0] req_id = 'h00;
-reg [1:0] eot_id = 'h00;
-reg [3:0] last_req = 'h00;
+  reg [1:0] req_id = 'h00;
+  reg [1:0] eot_id = 'h00;
+  reg [3:0] last_req = 'h00;
 
-wire out_last;
+  // internal signals
 
-assign out_req_dest_address = dest_address;
-assign out_req_src_address = src_address;
-assign out_req_length = x_length;
-assign out_last = y_length == 'h00;
+  wire out_last;
 
-always @(posedge req_aclk) begin
-  if (req_aresetn == 1'b0) begin
-    req_id <= 2'b0;
-    eot_id <= 2'b0;
-    req_eot <= 1'b0;
-  end else begin
-    if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
-      req_id <= req_id + 1'b1;
-    end
+  // signal name changes
 
-    if (out_eot == 1'b1 && out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
-      eot_id <= eot_id + 1'b1;
-      req_eot <= last_req[eot_id];
-    end else begin
+  assign out_req_dest_address = dest_address;
+  assign out_req_src_address = src_address;
+  assign out_req_length = x_length;
+  assign out_last = y_length == 'h00;
+
+  always @(posedge req_aclk) begin
+    if (req_aresetn == 1'b0) begin
+      req_id <= 2'b0;
+      eot_id <= 2'b0;
       req_eot <= 1'b0;
+    end else begin
+      if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
+        req_id <= req_id + 1'b1;
+      end
+
+      if (out_eot == 1'b1 && out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
+        eot_id <= eot_id + 1'b1;
+        req_eot <= last_req[eot_id];
+      end else begin
+        req_eot <= 1'b0;
+      end
     end
   end
-end
 
-always @(posedge req_aclk) begin
-  if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
-    last_req[req_id] <= out_last;
+  always @(posedge req_aclk) begin
+    if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
+      last_req[req_id] <= out_last;
+    end
   end
-end
 
-always @(posedge req_aclk) begin
-  if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
-    req_measured_burst_length <= out_measured_burst_length;
-    req_response_partial <= out_response_partial;
+  always @(posedge req_aclk) begin
+    if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
+      req_measured_burst_length <= out_measured_burst_length;
+      req_response_partial <= out_response_partial;
+    end
   end
-end
 
-always @(posedge req_aclk) begin
-  if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
-    req_response_valid <= 1'b1;
-  end else if (req_response_ready == 1'b1) begin
-    req_response_valid <= 1'b0;
-  end
-end
-
-always @(posedge req_aclk) begin
-  if (req_aresetn == 1'b0) begin
-    out_response_ready <= 1'b1;
-  end else if (out_response_ready == 1'b1) begin
-    out_response_ready <= ~out_response_valid;
-  end else if (req_response_ready == 1'b1) begin
-    out_response_ready <= 1'b1;
+  always @(posedge req_aclk) begin
+    if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
+      req_response_valid <= 1'b1;
+    end else if (req_response_ready == 1'b1) begin
+      req_response_valid <= 1'b0;
+    end
   end
-end
-
-always @(posedge req_aclk) begin
-  if (req_ready == 1'b1 && req_valid == 1'b1) begin
-    dest_address <= req_dest_address;
-    src_address <= req_src_address;
-    x_length <= req_x_length;
-    y_length <= req_y_length;
-    dest_stride <= req_dest_stride;
-    src_stride <= req_src_stride;
-    out_req_sync_transfer_start <= req_sync_transfer_start;
-    gen_last <= req_last;
-  end else if (out_abort_req == 1'b1) begin
-    y_length <= 0;
-  end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
-    dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
-    src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
-    y_length <= y_length - 1'b1;
-    out_req_sync_transfer_start <= 1'b0;
+
+  always @(posedge req_aclk) begin
+    if (req_aresetn == 1'b0) begin
+      out_response_ready <= 1'b1;
+    end else if (out_response_ready == 1'b1) begin
+      out_response_ready <= ~out_response_valid;
+    end else if (req_response_ready == 1'b1) begin
+      out_response_ready <= 1'b1;
+    end
   end
-end
 
-always @(posedge req_aclk) begin
-  if (req_aresetn == 1'b0) begin
-    req_ready <= 1'b1;
-    out_req_valid <= 1'b0;
-  end else begin
+  always @(posedge req_aclk) begin
     if (req_ready == 1'b1 && req_valid == 1'b1) begin
-      req_ready <= 1'b0;
-      out_req_valid <= 1'b1;
-    end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 &&
-                 out_last == 1'b1) begin
-      out_req_valid <= 1'b0;
+      dest_address <= req_dest_address;
+      src_address <= req_src_address;
+      x_length <= req_x_length;
+      y_length <= req_y_length;
+      dest_stride <= req_dest_stride;
+      src_stride <= req_src_stride;
+      out_req_sync_transfer_start <= req_sync_transfer_start;
+      gen_last <= req_last;
+    end else if (out_abort_req == 1'b1) begin
+      y_length <= 0;
+    end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
+      dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
+      src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
+      y_length <= y_length - 1'b1;
+      out_req_sync_transfer_start <= 1'b0;
+    end
+  end
+
+  always @(posedge req_aclk) begin
+    if (req_aresetn == 1'b0) begin
       req_ready <= 1'b1;
+      out_req_valid <= 1'b0;
+    end else begin
+      if (req_ready == 1'b1 && req_valid == 1'b1) begin
+        req_ready <= 1'b0;
+        out_req_valid <= 1'b1;
+      end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 &&
+                   out_last == 1'b1) begin
+        out_req_valid <= 1'b0;
+        req_ready <= 1'b1;
+      end
     end
   end
-end
 
-assign out_req_last = out_last & gen_last;
+  assign out_req_last = out_last & gen_last;
 
 endmodule
diff --git a/library/axi_dmac/tb/dma_read_shutdown_tb b/library/axi_dmac/tb/dma_read_shutdown_tb
@@ -3,7 +3,7 @@
 SOURCE="$0.v"
 SOURCE+=" axi_read_slave.v axi_slave.v"
 SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
-SOURCE+=" ../2d_transfer.v"
+SOURCE+=" ../dmac_2d_transfer.v"
 SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"

diff --git a/library/axi_dmac/tb/dma_read_tb b/library/axi_dmac/tb/dma_read_tb
@@ -2,7 +2,7 @@
 
 SOURCE="dma_read_tb.v"
 SOURCE+=" axi_read_slave.v axi_slave.v"
-SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
+SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
 SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"

diff --git a/library/axi_dmac/tb/dma_write_shutdown_tb b/library/axi_dmac/tb/dma_write_shutdown_tb
@@ -3,7 +3,7 @@
 SOURCE="$0.v"
 SOURCE+=" axi_write_slave.v axi_slave.v"
 SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
-SOURCE+=" ../2d_transfer.v"
+SOURCE+=" ../dmac_2d_transfer.v"
 SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"

diff --git a/library/axi_dmac/tb/dma_write_tb b/library/axi_dmac/tb/dma_write_tb
@@ -2,7 +2,7 @@
 
 SOURCE="dma_write_tb.v"
 SOURCE+=" axi_write_slave.v axi_slave.v"
-SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
+SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
 SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
 SOURCE+=" ../axi_dmac_burst_memory.v"
 SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"