arch: arm: zynq-pluto*.dts*: Update device tree to reflect phasor

This commit introduces the required entries to reflect the hardware
in the pluto phasor configuration.

The new AXI TDD driver is a platform driver which we need to access
through the IIO framework. Using the fake iio this should be now
possible.

This commit also introduces an internal one-bit-adc-dac to control the
PS-PL-GPIO pin which is responsible for enabling the phaser logic. This
allows the user to access this GPIO pin over the usual IIO interface
(And thus remotely).

Signed-off-by: Ionut Podgoreanu <[email protected]>
Signed-off-by: Michael Hennerich <[email protected]>

arch/arm/boot/dts/zynq-pluto-sdr-revc.dts

@@ -33,6 +33,34 @@
 };
 
 &amba {
+	axi_tdd_0: axi-tdd-0@7C440000 {
+		compatible = "adi,axi-tdd";
+		reg = <0x7C440000 0x10000>;
+		clocks = <&clkc 15>, <&adc0_ad9364 20>;
+		clock-names = "s_axi_aclk", "intf_clk";
+	};
+
+	iio_axi_tdd_0@0 {
+		compatible = "adi,iio-fake-platform-device";
+		adi,faked-dev = <&axi_tdd_0>;
+		adi,attribute-names =
+		"version", "core_id", "scratch", "magic",
+		"sync_soft", "sync_external", "sync_internal", "sync_reset",
+		"enable", "startup_delay_raw", "startup_delay_ms",
+		"burst_count", "frame_length_raw", "frame_length_ms",
+		"state", "internal_sync_period_raw", "internal_sync_period_ms",
+		"out_channel0_enable", "out_channel0_polarity",
+		"out_channel0_on_raw", "out_channel0_on_ms",
+		"out_channel0_off_raw", "out_channel0_off_ms",
+		"out_channel1_enable", "out_channel1_polarity",
+		"out_channel1_on_raw", "out_channel1_on_ms",
+		"out_channel1_off_raw", "out_channel1_off_ms",
+		"out_channel2_enable", "out_channel2_polarity",
+		"out_channel2_on_raw", "out_channel2_on_ms",
+		"out_channel2_off_raw", "out_channel2_off_ms";
+		label = "iio-axi-tdd-0";
+	};
+
 	axi_spi: spi@7C430000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -91,4 +119,24 @@
 			linux,code = <BTN_MISC>;
 		};
 	};
+
+	one-bit-adc-dac@0 {
+		compatible = "adi,one-bit-adc-dac";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		in-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
+		out-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
+
+		channel@0 {
+			reg = <0>;
+			label = "muxout";
+		};
+
+		channel@1 {
+			reg = <1>;
+			label = "phaser_enable";
+		};
+	};
 };