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dts: Update deprecated axi-dmac channel bindings
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The old AXI-DMAC channel bindings are ADI only and not supported in
upstream. We want to eventually drop support for those.

But for that to happen there should be no more users of those bindings for
a while.

Update all devicetrees that still use the old binding to the new binding.

Signed-off-by: Lars-Peter Clausen <[email protected]>
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@larsclausen
larsclausen committed Oct 25, 2018
1 parent a44ccb9 commit f0fd895
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Showing 26 changed files with 460 additions and 144 deletions.
14 changes: 11 additions & 3 deletions arch/arm/boot/dts/adi-zynq-cn0363.dtsi
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Expand Up @@ -18,9 +18,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 15>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <32>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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31 changes: 24 additions & 7 deletions arch/arm/boot/dts/socfpga_cyclone5_sockit_arradio.dts
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Expand Up @@ -179,10 +179,18 @@
#dma-cells = <1>;
clocks = <&axi_dmac0_clk>;
clock-names = "axi_dmac0_clkin";
dma-channel {
adi,buswidth = <64>;
adi,type = <1>;
adi,cyclic;

adi,channels {
#address-cells = <1>;
#size-cells = <0>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <2>;
};
};
};

Expand All @@ -194,9 +202,18 @@
#dma-cells = <1>;
clocks = <&axi_dmac0_clk>;
clock-names = "axi_dmac0_clkin";
dma-channel {
adi,buswidth = <64>;
adi,type = <0>;

adi,channels {
#address-cells = <1>;
#size-cells = <0>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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29 changes: 22 additions & 7 deletions arch/arm/boot/dts/zynq-zc702-adv7511-ad9361-fmcomms5.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <128>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

Expand All @@ -30,10 +38,17 @@
interrupts = <0 56 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <1>;
adi,cyclic;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <128>;
adi,destination-bus-type = <2>;
};
};
};

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29 changes: 22 additions & 7 deletions arch/arm/boot/dts/zynq-zc702-adv7511-fmcomms1.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

Expand All @@ -24,10 +32,17 @@
interrupts = <0 56 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <1>;
adi,cyclic;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <2>;
};
};
};

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14 changes: 11 additions & 3 deletions arch/arm/boot/dts/zynq-zc706-adv7511-ad6676-fmc.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -103,9 +103,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#address-cells = <1>;
#size-cells = <0>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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13 changes: 11 additions & 2 deletions arch/arm/boot/dts/zynq-zc706-adv7511-ad9265-fmc-125ebz.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <16>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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13 changes: 11 additions & 2 deletions arch/arm/boot/dts/zynq-zc706-adv7511-ad9434-fmc-500ebz.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,17 @@
interrupts = <0 57 0>; /* 57 */
clocks = <&clkc 16>;

dma-channel {
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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14 changes: 11 additions & 3 deletions arch/arm/boot/dts/zynq-zc706-adv7511-ad9625-fmcadc2.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -78,9 +78,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#address-cells = <1>;
#size-cells = <0>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <1>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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16 changes: 12 additions & 4 deletions arch/arm/boot/dts/zynq-zc706-adv7511-ad9739a-fmc.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -43,10 +43,18 @@
#dma-cells = <1>;
interrupts = <0 56 0>;
clocks = <&clkc 16>;
dma-channel {
adi,buswidth = <64>;
adi,type = <1>;
adi,cyclic;

adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <256>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <256>;
adi,destination-bus-type = <2>;
};
};
};

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43 changes: 33 additions & 10 deletions arch/arm/boot/dts/zynq-zc706-adv7511-adrv9371.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

Expand All @@ -47,9 +55,17 @@
interrupts = <0 55 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

Expand All @@ -60,10 +76,17 @@
interrupts = <0 56 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <128>;
adi,type = <1>;
adi,cyclic;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <128>;
adi,destination-bus-type = <1>;
};
};
};

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15 changes: 11 additions & 4 deletions arch/arm/boot/dts/zynq-zc706-adv7511-fmcadc4.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,10 +11,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,source-bus-width = <64>;
adi,destination-bus-width = <64>;
adi,type = <0>;
adi,channels {
#address-cells = <1>;
#size-cells = <0>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <1>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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14 changes: 11 additions & 3 deletions arch/arm/boot/dts/zynq-zc706-adv7511-fmcdaq1.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,17 @@
interrupts = <0 57 0>;
clocks = <&clkc 16>;

dma-channel {
adi,buswidth = <64>;
adi,type = <0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;

dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};

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