diff --git a/ares/md/m32x/bus-internal.cpp b/ares/md/m32x/bus-internal.cpp
index 7e63a41b1..dbb834fdf 100644
--- a/ares/md/m32x/bus-internal.cpp
+++ b/ares/md/m32x/bus-internal.cpp
@@ -1,6 +1,6 @@
 auto M32X::readInternal(n1 upper, n1 lower, n32 address, n16 data) -> n16 {
   if(address >= 0x0000'0000 && address <= 0x0000'3fff) {
-    if(shm.active()) shm.step(1); if(shs.active()) shs.step(1);
+    if(shm.active()) shm.internalStep(1); if(shs.active()) shs.internalStep(1);
     if(shm.active()) return shm.bootROM[address >> 1];
     if(shs.active()) return shs.bootROM[address >> 1];
   }
@@ -12,17 +12,17 @@ auto M32X::readInternal(n1 upper, n1 lower, n32 address, n16 data) -> n16 {
   if(address >= 0x0200'0000 && address <= 0x023f'ffff) {
     while(dreq.vram) {
       // SH2 ROM accesses stall while RV is set
-      if(shm.active()) shm.step(1);
-      if(shs.active()) shs.step(1);
+      if(shm.active()) shm.internalStep(1);
+      if(shs.active()) shs.internalStep(1);
     }
 
     // TODO: SH2 ROM accesses need to stall while the m68k is on the bus
-    if(shm.active()) shm.step(6); if(shs.active()) shs.step(6);
+    if(shm.active()) shm.internalStep(6); if(shs.active()) shs.internalStep(6);
     return cartridge.child->read(upper, lower, address, data);
   }
 
   if(address >= 0x0400'0000 && address <= 0x0405'ffff) {
-    if(shm.active()) shm.step(5); if(shs.active()) shs.step(5);
+    if(shm.active()) shm.internalStep(5); if(shs.active()) shs.internalStep(5);
     return vdp.bbram[address >> 1 & 0xffff];
   }
 
@@ -41,7 +41,7 @@ auto M32X::writeInternal(n1 upper, n1 lower, n32 address, n16 data) -> void {
   if(address >= 0x0400'0000 && address <= 0x0401'ffff) {
     if (!vdp.framebufferAccess) return;
     if(!data && (!upper || !lower)) return;  //8-bit 0x00 writes do not go through
-    if(shm.active()) shm.step(4); if(shs.active()) shs.step(4);
+    if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     if(upper) vdp.bbram[address >> 1 & 0xffff].byte(1) = data.byte(1);
     if(lower) vdp.bbram[address >> 1 & 0xffff].byte(0) = data.byte(0);
     return;
@@ -49,7 +49,7 @@ auto M32X::writeInternal(n1 upper, n1 lower, n32 address, n16 data) -> void {
 
   if(address >= 0x0402'0000 && address <= 0x0403'ffff) {
     if (!vdp.framebufferAccess) return;
-    if(shm.active()) shm.step(4); if(shs.active()) shs.step(4);
+    if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     if(upper && data.byte(1)) vdp.bbram[address >> 1 & 0xffff].byte(1) = data.byte(1);
     if(lower && data.byte(0)) vdp.bbram[address >> 1 & 0xffff].byte(0) = data.byte(0);
     return;
@@ -58,7 +58,7 @@ auto M32X::writeInternal(n1 upper, n1 lower, n32 address, n16 data) -> void {
   if(address >= 0x0404'0000 && address <= 0x0405'ffff) {
     if (!vdp.framebufferAccess) return;
     if(!data && (!upper || !lower)) return;  //8-bit 0x00 writes do not go through
-    if(shm.active()) shm.step(4); if(shs.active()) shs.step(4);
+    if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     if(upper) vdp.bbram[address >> 1 & 0xffff].byte(1) = data.byte(1);
     if(lower) vdp.bbram[address >> 1 & 0xffff].byte(0) = data.byte(0);
     return;
diff --git a/ares/md/m32x/io-internal.cpp b/ares/md/m32x/io-internal.cpp
index 6facf4510..962bf2f58 100644
--- a/ares/md/m32x/io-internal.cpp
+++ b/ares/md/m32x/io-internal.cpp
@@ -1,5 +1,5 @@
 auto M32X::readInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> n16 {
-  if(shm.active()) shm.step(1); if(shs.active()) shs.step(1);
+  if(shm.active()) shm.internalStep(1); if(shs.active()) shs.internalStep(1);
 
   //interrupt mask
   if(address == 0x4000) {
@@ -152,7 +152,7 @@ auto M32X::readInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> n16 {
 
   //palette
   if(address >= 0x4200 && address <= 0x43ff) {
-    if(shm.active()) shm.step(4); if(shs.active()) shs.step(4);
+    if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     data = vdp.cram[address >> 1 & 0xff];
   }
 
@@ -160,7 +160,7 @@ auto M32X::readInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> n16 {
 }
 
 auto M32X::writeInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> void {
-  if(shm.active()) shm.step(1); if(shs.active()) shs.step(1);
+  if(shm.active()) shm.internalStep(1); if(shs.active()) shs.internalStep(1);
 
   //interrupt mask
   if(address == 0x4000) {
@@ -338,7 +338,7 @@ auto M32X::writeInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> void {
   //palette
   if(address >= 0x4200 && address <= 0x43ff) {
     if (!vdp.framebufferAccess) return;
-    if(shm.active()) shm.step(4); if(shs.active()) shs.step(4);
+    if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     if(upper) vdp.cram[address >> 1 & 0xff].byte(1) = data.byte(1);
     if(lower) vdp.cram[address >> 1 & 0xff].byte(0) = data.byte(0);
   }
diff --git a/ares/md/m32x/m32x.hpp b/ares/md/m32x/m32x.hpp
index be08e0e6f..864ad6c08 100644
--- a/ares/md/m32x/m32x.hpp
+++ b/ares/md/m32x/m32x.hpp
@@ -40,6 +40,7 @@ struct M32X {
     auto main() -> void;
     auto instructionPrologue(u16 instruction) -> void override;
     auto step(u32 clocks) -> void override;
+    auto internalStep(u32 clocks) -> void;
     auto power(bool reset) -> void;
     auto restart() -> void;
     auto syncOtherSh2() -> void;
diff --git a/ares/md/m32x/sh7604.cpp b/ares/md/m32x/sh7604.cpp
index 728266e84..2e832c812 100644
--- a/ares/md/m32x/sh7604.cpp
+++ b/ares/md/m32x/sh7604.cpp
@@ -49,6 +49,15 @@ auto M32X::SH7604::instructionPrologue(u16 instruction) -> void {
   debugger.instruction(instruction);
 }
 
+auto M32X::SH7604::internalStep(u32 clocks) -> void {
+  if(SH2::Accuracy::Recompiler && m32x.shm.recompiler.enabled) {
+    regs.CCR += clocks;
+    return;
+  }
+
+  step(clocks);
+}
+
 auto M32X::SH7604::step(u32 clocks) -> void {
   SH2::frt.run(clocks);
   SH2::wdt.run(clocks);