diff --git a/ares/md/m32x/bus-internal.cpp b/ares/md/m32x/bus-internal.cpp
index c0683fac0..008a9c715 100644
--- a/ares/md/m32x/bus-internal.cpp
+++ b/ares/md/m32x/bus-internal.cpp
@@ -11,12 +11,12 @@ auto M32X::readInternal(n1 upper, n1 lower, n32 address, n16 data) -> n16 {
 
   if(address >= 0x0200'0000 && address <= 0x03ff'ffff) {
     while(dreq.vram) {
-      // SH2 ROM accesses stall while RV is set
+      //SH2 ROM accesses stall while RV is set
       if(shm.active()) { shm.internalStep(1); shm.syncM68k(true); }
       if(shs.active()) { shs.internalStep(1); shs.syncM68k(true); }
     }
 
-    // TODO: SH2 ROM accesses need to stall while the m68k is on the bus
+    //TODO: SH2 ROM accesses need to stall while the m68k is on the bus
     if(shm.active()) shm.internalStep(6); if(shs.active()) shs.internalStep(6);
     return cartridge.child->read(upper, lower, address, data);
   }
diff --git a/ares/md/m32x/io-internal.cpp b/ares/md/m32x/io-internal.cpp
index 57d535570..e65c35a11 100644
--- a/ares/md/m32x/io-internal.cpp
+++ b/ares/md/m32x/io-internal.cpp
@@ -157,8 +157,8 @@ auto M32X::readInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> n16 {
   if(address >= 0x4200 && address <= 0x43ff) {
     if(!vdp.framebufferAccess) return data;
     while(vdp.paletteEngaged()) {
-      if(shm.active()) { shm.internalStep(1); shm.syncAll(); }
-      if(shs.active()) { shs.internalStep(1); shs.syncAll(); }
+      if(shm.active()) { shm.internalStep(1); shm.syncAll(true); }
+      if(shs.active()) { shs.internalStep(1); shs.syncAll(true); }
     }
     if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     data = vdp.cram[address >> 1 & 0xff];
@@ -347,8 +347,8 @@ auto M32X::writeInternalIO(n1 upper, n1 lower, n29 address, n16 data) -> void {
   if(address >= 0x4200 && address <= 0x43ff) {
     if(!vdp.framebufferAccess) return;
     while(vdp.paletteEngaged()) {
-      if(shm.active()) { shm.internalStep(1); shm.syncAll(); }
-      if(shs.active()) { shs.internalStep(1); shs.syncAll(); }
+      if(shm.active()) { shm.internalStep(1); shm.syncAll(true); }
+      if(shs.active()) { shs.internalStep(1); shs.syncAll(true); }
     }
     if(shm.active()) shm.internalStep(4); if(shs.active()) shs.internalStep(4);
     if(upper) vdp.cram[address >> 1 & 0xff].byte(1) = data.byte(1);