diff --git a/arch/ARM/ARMGenCSMappingInsn.inc b/arch/ARM/ARMGenCSMappingInsn.inc index 3124c37a53..7860838f5a 100644 --- a/arch/ARM/ARMGenCSMappingInsn.inc +++ b/arch/ARM/ARMGenCSMappingInsn.inc @@ -26955,7 +26955,7 @@ }, { /* vscclrm{$p} $regs */ - ARM_VSCCLRMD /* 3449 */, ARM_INS_VSCCLRM_, + ARM_VSCCLRMD /* 3449 */, ARM_INS_VSCCLRM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_FEATURE_HASV8_1MMAINLINE, ARM_FEATURE_HAS8MSECEXT, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }} @@ -26963,7 +26963,7 @@ }, { /* vscclrm{$p} $regs */ - ARM_VSCCLRMS /* 3450 */, ARM_INS_VSCCLRM_, + ARM_VSCCLRMS /* 3450 */, ARM_INS_VSCCLRM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_FEATURE_HASV8_1MMAINLINE, ARM_FEATURE_HAS8MSECEXT, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }} @@ -31147,7 +31147,7 @@ }, { /* adr{$p}.w $Rd, $addr */ - ARM_t2ADR /* 3989 */, ARM_INS_ADR_, + ARM_t2ADR /* 3989 */, ARM_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_FEATURE_ISTHUMB2, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }} @@ -34319,7 +34319,7 @@ }, { /* adr{$p} $Rd, $addr */ - ARM_tADR /* 4386 */, ARM_INS_ADR_, + ARM_tADR /* 4386 */, ARM_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_FEATURE_ISTHUMB, 0 }, 0, 0, { .aarch64 = { .mem_acc = CS_AC_INVALID }} diff --git a/arch/ARM/ARMGenCSMappingInsnName.inc b/arch/ARM/ARMGenCSMappingInsnName.inc index 6e2a2194fd..2105c7b0f9 100644 --- a/arch/ARM/ARMGenCSMappingInsnName.inc +++ b/arch/ARM/ARMGenCSMappingInsnName.inc @@ -577,7 +577,7 @@ "vrsqrts", // ARM_INS_VRSQRTS "vrsra", // ARM_INS_VRSRA "vrsubhn", // ARM_INS_VRSUBHN - "vscclrm_", // ARM_INS_VSCCLRM_ + "vscclrm", // ARM_INS_VSCCLRM "vsdot", // ARM_INS_VSDOT "vseleq", // ARM_INS_VSELEQ "vselge", // ARM_INS_VSELGE @@ -608,7 +608,6 @@ "vuzp", // ARM_INS_VUZP "vzip", // ARM_INS_VZIP "addw", // ARM_INS_ADDW - "adr_", // ARM_INS_ADR_ "aut", // ARM_INS_AUT "autg", // ARM_INS_AUTG "bfl", // ARM_INS_BFL diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc index a783383b66..749cdb85d8 100644 --- a/arch/ARM/ARMGenCSMappingInsnOp.inc +++ b/arch/ARM/ARMGenCSMappingInsnOp.inc @@ -28521,7 +28521,7 @@ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { 0 } }}, -{ /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM_ - vscclrm{$p} $regs */ +{ /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */ { { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ @@ -28529,7 +28529,7 @@ { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ { 0 } }}, -{ /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM_ - vscclrm{$p} $regs */ +{ /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */ { { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ @@ -32923,7 +32923,7 @@ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { 0 } }}, -{ /* ARM_t2ADR (3989) - ARM_INS_ADR_ - adr{$p}.w $Rd, $addr */ +{ /* ARM_t2ADR (3989) - ARM_INS_ADR - adr{$p}.w $Rd, $addr */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ @@ -36491,7 +36491,7 @@ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { 0 } }}, -{ /* ARM_tADR (4386) - ARM_INS_ADR_ - adr{$p} $Rd, $addr */ +{ /* ARM_tADR (4386) - ARM_INS_ADR - adr{$p} $Rd, $addr */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */ diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index abaa210d67..453b230977 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -565,6 +565,20 @@ static void ARM_add_not_defined_ops(MCInst *MI) } break; } + case ARM_RFEDA_UPD: + case ARM_RFEDB_UPD: + case ARM_RFEIA_UPD: + case ARM_RFEIB_UPD: + get_detail(MI)->writeback = true; + // fallthrough + case ARM_RFEDA: + case ARM_RFEDB: + case ARM_RFEIA: + case ARM_RFEIB: { + arm_reg base_reg = ARM_get_detail_op(MI, -1)->reg; + ARM_get_detail_op(MI, -1)->type = ARM_OP_MEM; + ARM_get_detail_op(MI, -1)->mem.base = base_reg; + } } } @@ -627,6 +641,26 @@ static void ARM_post_index_detection(MCInst *MI) ARM_dec_op_count(MI); } +void ARM_check_mem_access_validity(MCInst *MI) +{ +#ifndef CAPSTONE_DIET + if (!detail_is_set(MI)) + return; + const arm_suppl_info *suppl = map_get_suppl_info(MI, arm_insns); + CS_ASSERT_RET(suppl); + if (suppl->mem_acc == CS_AC_INVALID) { + return; + } + cs_detail *detail = get_detail(MI); + for (int i = 0; i < detail->arm.op_count; ++i) { + if (detail->arm.operands[i].type == ARM_OP_MEM && detail->arm.operands[i].access != suppl->mem_acc) { + detail->arm.operands[i].access = suppl->mem_acc; + return; + } + } +#endif // CAPSTONE_DIET +} + /// Decodes the asm string for a given instruction /// and fills the detail information about the instruction and its operands. void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) @@ -639,6 +673,7 @@ void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) map_set_alias_id(MI, O, insn_alias_mnem_map, ARR_SIZE(insn_alias_mnem_map) - 1); ARM_add_not_defined_ops(MI); ARM_post_index_detection(MI); + ARM_check_mem_access_validity(MI); ARM_add_cs_groups(MI); int syntax_opt = MI->csh->syntax; if (syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS) @@ -767,32 +802,12 @@ void ARM_check_updates_flags(MCInst *MI) #endif // CAPSTONE_DIET } -void ARM_check_mem_access_validity(MCInst *MI) -{ -#ifndef CAPSTONE_DIET - if (!detail_is_set(MI)) - return; - const arm_suppl_info *suppl = map_get_suppl_info(MI, arm_insns); - if (suppl->mem_acc == CS_AC_INVALID) { - return; - } - cs_detail *detail = get_detail(MI); - for (int i = 0; i < detail->arm.op_count; ++i) { - if (detail->arm.operands[i].type == ARM_OP_MEM && detail->arm.operands[i].access != suppl->mem_acc) { - detail->arm.operands[i].access = suppl->mem_acc; - return; - } - } -#endif // CAPSTONE_DIET -} - void ARM_set_instr_map_data(MCInst *MI) { map_cs_id(MI, arm_insns, ARR_SIZE(arm_insns)); map_implicit_reads(MI, arm_insns); map_implicit_writes(MI, arm_insns); ARM_check_updates_flags(MI); - ARM_check_mem_access_validity(MI); map_groups(MI, arm_insns); } @@ -1848,8 +1863,10 @@ static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group, case ARM_OP_GROUP_AddrMode5FP16Operand_0: { bool AlwaysPrintImm0 = temp_arg_0; - if (AlwaysPrintImm0) + if (AlwaysPrintImm0) { + get_detail(MI)->writeback = true; map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum)); + } ARM_check_safe_inc(MI); cs_arm_op *Op = ARM_get_detail_op(MI, 0); diff --git a/arch/ARM/ARMMappingInsn.inc b/arch/ARM/ARMMappingInsn.inc deleted file mode 100644 index 59b6b9f64b..0000000000 --- a/arch/ARM/ARMMappingInsn.inc +++ /dev/null @@ -1,20189 +0,0 @@ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -{ ARM_ASRi, ARM_INS_ASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, - - { ARM_ASRr, ARM_INS_ASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_ITasm, ARM_INS_IT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_LDRBT_POST, ARM_INS_LDRBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_LDRConstPool, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRT_POST, ARM_INS_LDRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_LSLi, ARM_INS_LSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_LSLr, ARM_INS_LSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_LSRi, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_LSRr, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_RORi, ARM_INS_ROR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_RORr, ARM_INS_ROR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_RRXi, ARM_INS_RRX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_STRBT_POST, ARM_INS_STRBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_STRT_POST, ARM_INS_STRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD1LNdAsm_16, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdAsm_32, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdAsm_8, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdWB_fixed_Asm_16, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdWB_fixed_Asm_32, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdWB_fixed_Asm_8, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdWB_register_Asm_16, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdWB_register_Asm_32, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNdWB_register_Asm_8, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdAsm_16, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdAsm_32, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdAsm_8, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdWB_fixed_Asm_16, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdWB_fixed_Asm_32, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdWB_fixed_Asm_8, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdWB_register_Asm_16, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdWB_register_Asm_32, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNdWB_register_Asm_8, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNqAsm_16, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNqAsm_32, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNqWB_fixed_Asm_16, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNqWB_fixed_Asm_32, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNqWB_register_Asm_16, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNqWB_register_Asm_32, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdAsm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdAsm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdAsm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdWB_fixed_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdWB_fixed_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdWB_fixed_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdWB_register_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdWB_register_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPdWB_register_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqAsm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqAsm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqAsm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqWB_fixed_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqWB_fixed_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqWB_fixed_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqWB_register_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqWB_register_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPqWB_register_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdAsm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdAsm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdAsm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdWB_fixed_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdWB_fixed_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdWB_fixed_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdWB_register_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdWB_register_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNdWB_register_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNqAsm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNqAsm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNqWB_fixed_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNqWB_fixed_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNqWB_register_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNqWB_register_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3dAsm_16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD3dAsm_32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD3dAsm_8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD3dWB_fixed_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3dWB_fixed_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3dWB_fixed_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3dWB_register_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3dWB_register_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3dWB_register_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3qAsm_16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD3qAsm_32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD3qAsm_8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD3qWB_fixed_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3qWB_fixed_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3qWB_fixed_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3qWB_register_Asm_16, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3qWB_register_Asm_32, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3qWB_register_Asm_8, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdAsm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdAsm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdAsm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdWB_fixed_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdWB_fixed_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdWB_fixed_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdWB_register_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdWB_register_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPdWB_register_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqAsm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqAsm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqAsm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqWB_fixed_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqWB_fixed_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqWB_fixed_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqWB_register_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqWB_register_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPqWB_register_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdAsm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdAsm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdAsm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdWB_fixed_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdWB_fixed_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdWB_fixed_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdWB_register_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdWB_register_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNdWB_register_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNqAsm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNqAsm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNqWB_fixed_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNqWB_fixed_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNqWB_register_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNqWB_register_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4dAsm_16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD4dAsm_32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD4dAsm_8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD4dWB_fixed_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4dWB_fixed_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4dWB_fixed_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4dWB_register_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4dWB_register_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4dWB_register_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4qAsm_16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD4qAsm_32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD4qAsm_8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD4qWB_fixed_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4qWB_fixed_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4qWB_fixed_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4qWB_register_Asm_16, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4qWB_register_Asm_32, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4qWB_register_Asm_8, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdAsm_16, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdAsm_32, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdAsm_8, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdWB_fixed_Asm_16, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdWB_fixed_Asm_32, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdWB_fixed_Asm_8, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdWB_register_Asm_16, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdWB_register_Asm_32, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNdWB_register_Asm_8, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdAsm_16, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdAsm_32, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdAsm_8, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdWB_fixed_Asm_16, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdWB_fixed_Asm_32, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdWB_fixed_Asm_8, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdWB_register_Asm_16, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdWB_register_Asm_32, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNdWB_register_Asm_8, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNqAsm_16, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNqAsm_32, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNqWB_fixed_Asm_16, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNqWB_fixed_Asm_32, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNqWB_register_Asm_16, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNqWB_register_Asm_32, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdAsm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdAsm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdAsm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdWB_fixed_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdWB_fixed_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdWB_fixed_Asm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdWB_register_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdWB_register_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNdWB_register_Asm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNqAsm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNqAsm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNqWB_fixed_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNqWB_fixed_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNqWB_register_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNqWB_register_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3dAsm_16, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST3dAsm_32, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST3dAsm_8, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST3dWB_fixed_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3dWB_fixed_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3dWB_fixed_Asm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3dWB_register_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3dWB_register_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3dWB_register_Asm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3qAsm_16, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST3qAsm_32, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST3qAsm_8, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST3qWB_fixed_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3qWB_fixed_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3qWB_fixed_Asm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3qWB_register_Asm_16, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3qWB_register_Asm_32, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3qWB_register_Asm_8, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdAsm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdAsm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdAsm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdWB_fixed_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdWB_fixed_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdWB_fixed_Asm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdWB_register_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdWB_register_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNdWB_register_Asm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNqAsm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNqAsm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNqWB_fixed_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNqWB_fixed_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNqWB_register_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNqWB_register_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4dAsm_16, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST4dAsm_32, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST4dAsm_8, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST4dWB_fixed_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4dWB_fixed_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4dWB_fixed_Asm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4dWB_register_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4dWB_register_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4dWB_register_Asm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4qAsm_16, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST4qAsm_32, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST4qAsm_8, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VST4qWB_fixed_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4qWB_fixed_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4qWB_fixed_Asm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4qWB_register_Asm_16, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4qWB_register_Asm_32, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4qWB_register_Asm_8, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDRBpcrel, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRConstPool, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDRHpcrel, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSBpcrel, - ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDRSHpcrel, - ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDRpcrel, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVSsi, ARM_INS_MOVS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVSsr, ARM_INS_MOVS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVsi, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVsr, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_tLDRConstPool, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_ADCri, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADCrr, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADCrsi, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADCrsr, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADDri, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADDrr, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADDrsi, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADDrsr, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ADR, ARM_INS_ADR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_AESD, ARM_INS_AESD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_AESE, ARM_INS_AESE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_AESIMC, ARM_INS_AESIMC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_AESMC, ARM_INS_AESMC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_ANDri, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ANDrr, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ANDrsi, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ANDrsr, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_BFC, ARM_INS_BFC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_BFI, ARM_INS_BFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_BICri, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_BICrr, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_BICrsi, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_BICrsr, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_BKPT, ARM_INS_BKPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_BL, - ARM_INS_BL, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, - 1, - 0 -#endif - }, - - { ARM_BLX, - ARM_INS_BLX, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, - 0, - 1 -#endif - }, - - { ARM_BLX_pred, - ARM_INS_BLX, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, - 0, - 1 -#endif - }, - - { ARM_BLXi, - ARM_INS_BLX, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, - 0 }, - 1, - 0 -#endif - }, - - { ARM_BL_pred, - ARM_INS_BL, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, - 1, - 0 -#endif - }, - - { ARM_BX, ARM_INS_BX, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 -#endif - }, - - { ARM_BXJ, ARM_INS_BXJ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1 -#endif - }, - - { ARM_BX_RET, ARM_INS_BX, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 -#endif - }, - - { ARM_BX_pred, ARM_INS_BX, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 -#endif - }, - - { ARM_Bcc, - ARM_INS_B, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_PC, 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, - 1, - 0 -#endif - }, - - { ARM_CDP, ARM_INS_CDP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_CDP2, ARM_INS_CDP2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_CLREX, ARM_INS_CLREX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_CLZ, ARM_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 -#endif - }, - - { ARM_CMNri, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMNzrr, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMNzrsi, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMNzrsr, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMPri, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMPrr, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMPrsi, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CMPrsr, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CPS1p, ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CPS2p, ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CPS3p, ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_CRC32B, - ARM_INS_CRC32B, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_CRC32CB, - ARM_INS_CRC32CB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_CRC32CH, - ARM_INS_CRC32CH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_CRC32CW, - ARM_INS_CRC32CW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_CRC32H, - ARM_INS_CRC32H, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_CRC32W, - ARM_INS_CRC32W, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_DBG, ARM_INS_DBG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_DMB, ARM_INS_DMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 -#endif - }, - - { ARM_DSB, ARM_INS_DSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 -#endif - }, - - { ARM_EORri, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_EORrr, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_EORrsi, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_EORrsr, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ERET, - ARM_INS_ERET, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_PC, 0 }, - { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, - 0, - 0 -#endif - }, - - { ARM_FCONSTD, ARM_INS_FCONSTD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_FCONSTH, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_FCONSTS, ARM_INS_FCONSTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 -#endif - }, - - { ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_FLDMXIA, ARM_INS_FLDMIAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_FMSTAT, - ARM_INS_FMSTAT, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_FSTMXIA, ARM_INS_FSTMIAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_HINT, ARM_INS_HINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_HLT, ARM_INS_HLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_HVC, ARM_INS_HVC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 -#endif - }, - - { ARM_ISB, ARM_INS_ISB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 -#endif - }, - - { ARM_LDA, ARM_INS_LDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDAB, ARM_INS_LDAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDAEX, ARM_INS_LDAEX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDAEXB, ARM_INS_LDAEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDAEXD, ARM_INS_LDAEXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDAEXH, ARM_INS_LDAEXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDAH, ARM_INS_LDAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_LDC2L_OFFSET, - ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDC2L_OPTION, - ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDC2L_POST, ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_LDC2L_PRE, ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_LDC2_OFFSET, ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_LDC2_OPTION, ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_LDC2_POST, ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_LDC2_PRE, ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_LDCL_OFFSET, ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDCL_OPTION, ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDCL_POST, ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDCL_PRE, ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDC_OFFSET, ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDC_OPTION, ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDC_POST, ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDC_PRE, ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMDA, ARM_INS_LDMDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMDA_UPD, ARM_INS_LDMDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMDB, ARM_INS_LDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMDB_UPD, ARM_INS_LDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMIA, ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMIA_UPD, ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMIB, ARM_INS_LDMIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDMIB_UPD, ARM_INS_LDMIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRBT_POST_IMM, - ARM_INS_LDRBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRBT_POST_REG, - ARM_INS_LDRBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRB_POST_IMM, - ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRB_POST_REG, - ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRB_PRE_IMM, - ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRB_PRE_REG, - ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRBi12, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRBrs, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRD, ARM_INS_LDRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_LDRD_POST, ARM_INS_LDRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRD_PRE, ARM_INS_LDRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDREX, ARM_INS_LDREX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDREXB, ARM_INS_LDREXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDREXD, ARM_INS_LDREXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDREXH, ARM_INS_LDREXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRH, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRHTi, ARM_INS_LDRHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRHTr, ARM_INS_LDRHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRH_POST, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRH_PRE, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSB, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSBTi, ARM_INS_LDRSBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSBTr, ARM_INS_LDRSBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSB_POST, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSB_PRE, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSH, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSHTi, ARM_INS_LDRSHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSHTr, ARM_INS_LDRSHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSH_POST, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRSH_PRE, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRT_POST_IMM, - ARM_INS_LDRT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDRT_POST_REG, - ARM_INS_LDRT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDR_POST_IMM, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDR_POST_REG, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_LDR_PRE_IMM, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDR_PRE_REG, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRcp, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRi12, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_LDRrs, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MCR, ARM_INS_MCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MCR2, ARM_INS_MCR2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_MCRR, ARM_INS_MCRR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MCRR2, ARM_INS_MCRR2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, - 0 -#endif - }, - - { ARM_MLA, - ARM_INS_MLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_MLS, - ARM_INS_MLS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_MOVPCLR, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MOVTi16, ARM_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_MOVi, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MOVi16, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_MOVr, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MOVr_TC, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MOVsi, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MOVsr, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MRC, ARM_INS_MRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MRC2, ARM_INS_MRC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_MRRC, ARM_INS_MRRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MRRC2, ARM_INS_MRRC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_MRS, ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MRSbanked, - ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, - 0, - 0 -#endif - }, - - { ARM_MRSsys, ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MSR, ARM_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MSRbanked, - ARM_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, - 0, - 0 -#endif - }, - - { ARM_MSRi, ARM_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MUL, ARM_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_MVNi, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MVNr, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MVNsi, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_MVNsr, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ORRri, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ORRrr, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ORRrsi, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_ORRrsr, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_PKHBT, ARM_INS_PKHBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_PKHTB, ARM_INS_PKHTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_PLDWi12, - ARM_INS_PLDW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, - 0, - 0 -#endif - }, - - { ARM_PLDWrs, - ARM_INS_PLDW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, - 0, - 0 -#endif - }, - - { ARM_PLDi12, ARM_INS_PLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_PLDrs, ARM_INS_PLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_PLIi12, ARM_INS_PLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_PLIrs, ARM_INS_PLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_QADD, ARM_INS_QADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QADD16, ARM_INS_QADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QADD8, ARM_INS_QADD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QASX, ARM_INS_QASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QDADD, ARM_INS_QDADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QDSUB, ARM_INS_QDSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QSAX, ARM_INS_QSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QSUB, ARM_INS_QSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QSUB16, ARM_INS_QSUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_QSUB8, ARM_INS_QSUB8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RBIT, ARM_INS_RBIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_REV, ARM_INS_REV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_REV16, ARM_INS_REV16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_REVSH, ARM_INS_REVSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_RFEDA, ARM_INS_RFEDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEDA_UPD, ARM_INS_RFEDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEDB, ARM_INS_RFEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEDB_UPD, ARM_INS_RFEDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEIA, ARM_INS_RFEIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEIA_UPD, ARM_INS_RFEIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEIB, ARM_INS_RFEIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RFEIB_UPD, ARM_INS_RFEIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSBri, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSBrr, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSBrsi, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSBrsr, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSCri, ARM_INS_RSC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSCrr, ARM_INS_RSC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSCrsi, ARM_INS_RSC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_RSCrsr, ARM_INS_RSC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SADD16, ARM_INS_SADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SADD8, ARM_INS_SADD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SASX, ARM_INS_SASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SBCri, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SBCrr, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SBCrsi, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SBCrsr, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SBFX, ARM_INS_SBFX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_SDIV, ARM_INS_SDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SEL, ARM_INS_SEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SETEND, ARM_INS_SETEND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SETPAN, ARM_INS_SETPAN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_SHA1C, ARM_INS_SHA1C, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA1H, ARM_INS_SHA1H, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA1M, ARM_INS_SHA1M, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA1P, ARM_INS_SHA1P, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA1SU0, ARM_INS_SHA1SU0, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA1SU1, ARM_INS_SHA1SU1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA256H, ARM_INS_SHA256H, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_SHA256H2, - ARM_INS_SHA256H2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, - 0, - 0 -#endif - }, - - { ARM_SHA256SU0, - ARM_INS_SHA256SU0, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, - 0, - 0 -#endif - }, - - { ARM_SHA256SU1, - ARM_INS_SHA256SU1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, - 0, - 0 -#endif - }, - - { ARM_SHADD16, ARM_INS_SHADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SHADD8, ARM_INS_SHADD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SHASX, ARM_INS_SHASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SHSAX, ARM_INS_SHSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SHSUB16, ARM_INS_SHSUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SHSUB8, ARM_INS_SHSUB8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SMC, - ARM_INS_SMC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLABB, - ARM_INS_SMLABB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLABT, - ARM_INS_SMLABT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLAD, ARM_INS_SMLAD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLADX, ARM_INS_SMLADX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLAL, ARM_INS_SMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLALBB, ARM_INS_SMLALBB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMLALBT, ARM_INS_SMLALBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMLALD, ARM_INS_SMLALD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLALDX, ARM_INS_SMLALDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLALTB, ARM_INS_SMLALTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMLALTT, ARM_INS_SMLALTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMLATB, - ARM_INS_SMLATB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLATT, - ARM_INS_SMLATT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLAWB, - ARM_INS_SMLAWB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLAWT, - ARM_INS_SMLAWT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMLSD, ARM_INS_SMLSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLSDX, ARM_INS_SMLSDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLSLD, ARM_INS_SMLSLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMLSLDX, ARM_INS_SMLSLDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMMLA, - ARM_INS_SMMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMMLAR, ARM_INS_SMMLAR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMMLS, - ARM_INS_SMMLS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_SMMLSR, ARM_INS_SMMLSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMMUL, ARM_INS_SMMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMMULR, ARM_INS_SMMULR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMUAD, ARM_INS_SMUAD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMUADX, ARM_INS_SMUADX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMULBB, ARM_INS_SMULBB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMULBT, ARM_INS_SMULBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMULL, ARM_INS_SMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMULTB, ARM_INS_SMULTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMULTT, ARM_INS_SMULTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMULWB, ARM_INS_SMULWB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMULWT, ARM_INS_SMULWT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_SMUSD, ARM_INS_SMUSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SMUSDX, ARM_INS_SMUSDX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SRSDA, ARM_INS_SRSDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSDA_UPD, ARM_INS_SRSDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSDB, ARM_INS_SRSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSDB_UPD, ARM_INS_SRSDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSIA, ARM_INS_SRSIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSIA_UPD, ARM_INS_SRSIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSIB, ARM_INS_SRSIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SRSIB_UPD, ARM_INS_SRSIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SSAT, ARM_INS_SSAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SSAT16, ARM_INS_SSAT16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SSAX, ARM_INS_SSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SSUB16, ARM_INS_SSUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SSUB8, ARM_INS_SSUB8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STC2L_OFFSET, - ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_STC2L_OPTION, - ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_STC2L_POST, ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_STC2L_PRE, ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_STC2_OFFSET, ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_STC2_OPTION, ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_STC2_POST, ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_STC2_PRE, ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_STCL_OFFSET, ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STCL_OPTION, ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STCL_POST, ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STCL_PRE, ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STC_OFFSET, ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STC_OPTION, ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STC_POST, ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STC_PRE, ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STL, ARM_INS_STL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STLB, ARM_INS_STLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STLEX, ARM_INS_STLEX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STLEXB, ARM_INS_STLEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STLEXD, ARM_INS_STLEXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STLEXH, ARM_INS_STLEXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STLH, ARM_INS_STLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_STMDA, ARM_INS_STMDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMDA_UPD, ARM_INS_STMDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMDB, ARM_INS_STMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMDB_UPD, ARM_INS_STMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMIA, ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMIA_UPD, ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMIB, ARM_INS_STMIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STMIB_UPD, ARM_INS_STMIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRBT_POST_IMM, - ARM_INS_STRBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRBT_POST_REG, - ARM_INS_STRBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRB_POST_IMM, - ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRB_POST_REG, - ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRB_PRE_IMM, - ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRB_PRE_REG, - ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRBi12, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRBrs, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRD, ARM_INS_STRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 -#endif - }, - - { ARM_STRD_POST, ARM_INS_STRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRD_PRE, ARM_INS_STRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STREX, ARM_INS_STREX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STREXB, ARM_INS_STREXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STREXD, ARM_INS_STREXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STREXH, ARM_INS_STREXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRH, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRHTi, ARM_INS_STRHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRHTr, ARM_INS_STRHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRH_POST, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRH_PRE, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRT_POST_IMM, - ARM_INS_STRT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STRT_POST_REG, - ARM_INS_STRT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STR_POST_IMM, - ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STR_POST_REG, - ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_STR_PRE_IMM, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STR_PRE_REG, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRi12, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_STRrs, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SUBri, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SUBrr, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SUBrsi, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SUBrsr, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_SVC, - ARM_INS_SVC, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, 0 }, - { ARM_GRP_ARM, ARM_GRP_INT, 0 }, - 0, - 0 -#endif - }, - - { ARM_SWP, ARM_INS_SWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_SWPB, ARM_INS_SWPB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_SXTAB, ARM_INS_SXTAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SXTAB16, ARM_INS_SXTAB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SXTAH, ARM_INS_SXTAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SXTB, ARM_INS_SXTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SXTB16, ARM_INS_SXTB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_SXTH, ARM_INS_SXTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_TEQri, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TEQrr, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TEQrsi, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TEQrsr, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TRAP, ARM_INS_TRAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TRAPNaCl, ARM_INS_TRAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TSB, ARM_INS_TSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_TSTri, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TSTrr, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TSTrsi, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_TSTrsr, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UADD16, ARM_INS_UADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UADD8, ARM_INS_UADD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UASX, ARM_INS_UASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UBFX, ARM_INS_UBFX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 -#endif - }, - - { ARM_UDF, ARM_INS_UDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UDIV, ARM_INS_UDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UHADD16, ARM_INS_UHADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UHADD8, ARM_INS_UHADD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UHASX, ARM_INS_UHASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UHSAX, ARM_INS_UHSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UHSUB16, ARM_INS_UHSUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UHSUB8, ARM_INS_UHSUB8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UMAAL, ARM_INS_UMAAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UMLAL, ARM_INS_UMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UMULL, ARM_INS_UMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UQADD16, ARM_INS_UQADD16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UQADD8, ARM_INS_UQADD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UQASX, ARM_INS_UQASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UQSAX, ARM_INS_UQSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UQSUB16, ARM_INS_UQSUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UQSUB8, ARM_INS_UQSUB8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_USAD8, ARM_INS_USAD8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_USADA8, ARM_INS_USADA8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_USAT, ARM_INS_USAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_USAT16, ARM_INS_USAT16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_USAX, ARM_INS_USAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_USUB16, ARM_INS_USUB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_USUB8, ARM_INS_USUB8, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_UXTAB, ARM_INS_UXTAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UXTAB16, ARM_INS_UXTAB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UXTAH, ARM_INS_UXTAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UXTB, ARM_INS_UXTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UXTB16, ARM_INS_UXTB16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_UXTH, ARM_INS_UXTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 -#endif - }, - - { ARM_VABALsv2i64, ARM_INS_VABAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABALsv4i32, ARM_INS_VABAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABALsv8i16, ARM_INS_VABAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABALuv2i64, ARM_INS_VABAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABALuv4i32, ARM_INS_VABAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABALuv8i16, ARM_INS_VABAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAsv16i8, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAsv2i32, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAsv4i16, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAsv4i32, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAsv8i16, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAsv8i8, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAuv16i8, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAuv2i32, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAuv4i16, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAuv4i32, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAuv8i16, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABAuv8i8, ARM_INS_VABA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDLsv2i64, ARM_INS_VABDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDLsv4i32, ARM_INS_VABDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDLsv8i16, ARM_INS_VABDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDLuv2i64, ARM_INS_VABDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDLuv4i32, ARM_INS_VABDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDLuv8i16, ARM_INS_VABDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDfd, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDfq, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDhd, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VABDhq, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VABDsv16i8, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDsv2i32, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDsv4i16, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDsv4i32, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDsv8i16, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDsv8i8, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDuv16i8, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDuv2i32, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDuv4i16, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDuv4i32, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDuv8i16, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABDuv8i8, ARM_INS_VABD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSD, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VABSH, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VABSS, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VABSfd, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSfq, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABShd, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VABShq, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VABSv16i8, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSv2i32, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSv4i16, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSv4i32, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSv8i16, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VABSv8i8, ARM_INS_VABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VACGEfd, ARM_INS_VACGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGEfq, ARM_INS_VACGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGEhd, ARM_INS_VACGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGEhq, ARM_INS_VACGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGTfd, ARM_INS_VACGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGTfq, ARM_INS_VACGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGThd, ARM_INS_VACGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VACGThq, ARM_INS_VACGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VADDD, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VADDH, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VADDHNv2i32, ARM_INS_VADDHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDHNv4i16, ARM_INS_VADDHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDHNv8i8, ARM_INS_VADDHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDLsv2i64, ARM_INS_VADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDLsv4i32, ARM_INS_VADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDLsv8i16, ARM_INS_VADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDLuv2i64, ARM_INS_VADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDLuv4i32, ARM_INS_VADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDLuv8i16, ARM_INS_VADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDS, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VADDWsv2i64, ARM_INS_VADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDWsv4i32, ARM_INS_VADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDWsv8i16, ARM_INS_VADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDWuv2i64, ARM_INS_VADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDWuv4i32, ARM_INS_VADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDWuv8i16, ARM_INS_VADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDfd, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDfq, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDhd, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VADDhq, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VADDv16i8, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv1i64, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv2i32, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv2i64, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv4i16, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv4i32, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv8i16, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VADDv8i8, ARM_INS_VADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VANDd, ARM_INS_VAND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VANDq, ARM_INS_VAND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBICd, ARM_INS_VBIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBICiv2i32, ARM_INS_VBIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBICiv4i16, ARM_INS_VBIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBICiv4i32, ARM_INS_VBIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBICiv8i16, ARM_INS_VBIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBICq, ARM_INS_VBIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBIFd, ARM_INS_VBIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBIFq, ARM_INS_VBIF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBITd, ARM_INS_VBIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBITq, ARM_INS_VBIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBSLd, ARM_INS_VBSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VBSLq, ARM_INS_VBSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCADDv2f32, ARM_INS_VCADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCADDv4f16, ARM_INS_VCADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCADDv4f32, ARM_INS_VCADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCADDv8f16, ARM_INS_VCADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCEQfd, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQfq, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQhd, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCEQhq, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCEQv16i8, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQv2i32, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQv4i16, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQv4i32, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQv8i16, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQv8i8, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv16i8, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv2f32, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv2i32, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv4f16, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv4f32, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv4i16, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv4i32, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv8f16, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv8i16, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCEQzv8i8, ARM_INS_VCEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEfd, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEfq, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEhd, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGEhq, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGEsv16i8, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEsv2i32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEsv4i16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEsv4i32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEsv8i16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEsv8i8, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEuv16i8, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEuv2i32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEuv4i16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEuv4i32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEuv8i16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEuv8i8, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv16i8, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv2f32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv2i32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv4f16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv4f32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv4i16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv4i32, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv8f16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv8i16, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGEzv8i8, ARM_INS_VCGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTfd, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTfq, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGThd, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGThq, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGTsv16i8, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTsv2i32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTsv4i16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTsv4i32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTsv8i16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTsv8i8, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTuv16i8, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTuv2i32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTuv4i16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTuv4i32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTuv8i16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTuv8i8, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv16i8, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv2f32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv2i32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv4f16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv4f32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv4i16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv4i32, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv8f16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv8i16, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCGTzv8i8, ARM_INS_VCGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv16i8, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv2f32, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv2i32, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv4f16, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv4f32, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv4i16, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv4i32, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv8f16, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv8i16, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLEzv8i8, ARM_INS_VCLE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLSv16i8, ARM_INS_VCLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLSv2i32, ARM_INS_VCLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLSv4i16, ARM_INS_VCLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLSv4i32, ARM_INS_VCLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLSv8i16, ARM_INS_VCLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLSv8i8, ARM_INS_VCLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv16i8, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv2f32, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv2i32, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv4f16, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv4f32, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv4i16, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv4i32, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv8f16, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv8i16, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLTzv8i8, ARM_INS_VCLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLZv16i8, ARM_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLZv2i32, ARM_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLZv4i16, ARM_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLZv4i32, ARM_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLZv8i16, ARM_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCLZv8i8, ARM_INS_VCLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCMLAv2f32, ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMLAv2f32_indexed, - ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMLAv4f16, ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMLAv4f16_indexed, - ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMLAv4f32, ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMLAv4f32_indexed, - ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMLAv8f16, ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMLAv8f16_indexed, - ARM_INS_VCMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPD, - ARM_INS_VCMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPED, - ARM_INS_VCMPE, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPEH, ARM_INS_VCMPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMPES, - ARM_INS_VCMPE, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPEZD, - ARM_INS_VCMPE, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPEZH, ARM_INS_VCMPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMPEZS, - ARM_INS_VCMPE, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPH, ARM_INS_VCMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMPS, - ARM_INS_VCMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPZD, - ARM_INS_VCMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCMPZH, ARM_INS_VCMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCMPZS, - ARM_INS_VCMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR_NZCV, 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCNTd, ARM_INS_VCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCNTq, ARM_INS_VCNT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANSDf, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANSDh, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANSQf, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANSQh, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANUDf, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANUDh, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANUQf, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTANUQh, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTASD, - ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTASH, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTASS, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTAUD, - ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTAUH, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTAUS, ARM_INS_VCVTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTBDH, - ARM_INS_VCVTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTBHD, - ARM_INS_VCVTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTBHS, ARM_INS_VCVTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTBSH, ARM_INS_VCVTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTDS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNSDf, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNSDh, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNSQf, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNSQh, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNUDf, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNUDh, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNUQf, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMNUQh, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMSD, - ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTMSH, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMSS, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMUD, - ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTMUH, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTMUS, ARM_INS_VCVTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNSDf, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNSDh, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNSQf, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNSQh, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNUDf, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNUDh, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNUQf, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNNUQh, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNSD, - ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTNSH, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNSS, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNUD, - ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTNUH, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTNUS, ARM_INS_VCVTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNSDf, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNSDh, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNSQf, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNSQh, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNUDf, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNUDh, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNUQf, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPNUQh, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPSD, - ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTPSH, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPSS, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPUD, - ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTPUH, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTPUS, ARM_INS_VCVTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTSD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTTDH, - ARM_INS_VCVTT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTTHD, - ARM_INS_VCVTT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VCVTTHS, ARM_INS_VCVTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTTSH, ARM_INS_VCVTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2h, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2sd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2sq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2ud, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2uq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2xsd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2xsq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2xud, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTf2xuq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2f, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2sd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2sq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2ud, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2uq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2xsd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2xsq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2xud, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTh2xuq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTs2fd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTs2fq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTs2hd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTs2hq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTu2fd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTu2fq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTu2hd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTu2hq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxs2fd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxs2fq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxs2hd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxs2hq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxu2fd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxu2fq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxu2hd, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VCVTxu2hq, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VDIVD, ARM_INS_VDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VDIVH, ARM_INS_VDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VDIVS, ARM_INS_VDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VDUP16d, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUP16q, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUP32d, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUP32q, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUP8d, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUP8q, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUPLN16d, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUPLN16q, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUPLN32d, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUPLN32q, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUPLN8d, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VDUPLN8q, ARM_INS_VDUP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEORd, ARM_INS_VEOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEORq, ARM_INS_VEOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTd16, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTd32, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTd8, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTq16, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTq32, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTq64, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VEXTq8, ARM_INS_VEXT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VFMAD, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VFMAH, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFMAS, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFMAfd, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFMAfq, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFMAhd, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFMAhq, ARM_INS_VFMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFMSD, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VFMSH, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFMSS, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFMSfd, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFMSfq, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFMShd, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFMShq, ARM_INS_VFMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFNMAD, ARM_INS_VFNMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VFNMAH, ARM_INS_VFNMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFNMAS, ARM_INS_VFNMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VFNMSD, ARM_INS_VFNMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VFNMSH, ARM_INS_VFNMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VFNMSS, ARM_INS_VFNMS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 -#endif - }, - - { ARM_VGETLNi32, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VGETLNs16, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VGETLNs8, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VGETLNu16, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VGETLNu8, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDsv16i8, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDsv2i32, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDsv4i16, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDsv4i32, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDsv8i16, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDsv8i8, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDuv16i8, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDuv2i32, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDuv4i16, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDuv4i32, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDuv8i16, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHADDuv8i8, ARM_INS_VHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBsv16i8, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBsv2i32, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBsv4i16, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBsv4i32, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBsv8i16, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBsv8i8, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBuv16i8, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBuv2i32, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBuv4i16, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBuv4i32, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBuv8i16, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VHSUBuv8i8, ARM_INS_VHSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VINSH, ARM_INS_VINS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VJCVT, ARM_INS_VJCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPd16, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPd16wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPd16wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPd32, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPd32wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPd32wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPd8, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPd8wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPd8wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPq16, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPq16wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPq16wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPq32, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPq32wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPq32wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPq8, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1DUPq8wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1DUPq8wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNd16, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1LNd16_UPD, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNd32, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1LNd32_UPD, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1LNd8, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1LNd8_UPD, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d16, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d16Q, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d16Qwb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d16Qwb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d16T, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d16Twb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d16Twb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d16wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d16wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d32, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d32Q, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d32Qwb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d32Qwb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d32T, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d32Twb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d32Twb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d32wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d32wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d64, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d64Q, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d64Qwb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d64Qwb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d64T, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d64Twb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d64Twb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d64wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d64wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d8, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d8Q, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d8Qwb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d8Qwb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d8T, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1d8Twb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d8Twb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d8wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1d8wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q16, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1q16wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q16wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q32, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1q32wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q32wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q64, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1q64wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q64wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q8, ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD1q8wb_fixed, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD1q8wb_register, - ARM_INS_VLD1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd16, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2DUPd16wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd16wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd16x2, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd16x2wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd16x2wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd32, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2DUPd32wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd32wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd32x2, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd32x2wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd32x2wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd8, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2DUPd8wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd8wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd8x2, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2DUPd8x2wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2DUPd8x2wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNd16, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2LNd16_UPD, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNd32, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2LNd32_UPD, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNd8, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2LNd8_UPD, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNq16, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2LNq16_UPD, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2LNq32, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2LNq32_UPD, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2b16, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2b16wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2b16wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2b32, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2b32wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2b32wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2b8, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2b8wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2b8wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2d16, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2d16wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2d16wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2d32, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2d32wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2d32wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2d8, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2d8wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2d8wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2q16, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2q16wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2q16wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2q32, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2q32wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2q32wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2q8, ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD2q8wb_fixed, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD2q8wb_register, - ARM_INS_VLD2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPd16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3DUPd16_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPd32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3DUPd32_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPd8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3DUPd8_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPq16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3DUPq16_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPq32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3DUPq32_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3DUPq8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3DUPq8_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNd16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3LNd16_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNd32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3LNd32_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNd8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3LNd8_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNq16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3LNq16_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3LNq32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3LNq32_UPD, - ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD3d16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3d16_UPD, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3d32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3d32_UPD, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3d8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3d8_UPD, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3q16, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3q16_UPD, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3q32, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3q32_UPD, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3q8, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD3q8_UPD, ARM_INS_VLD3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPd16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPd16_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPd32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPd32_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPd8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPd8_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPq16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPq16_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPq32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPq32_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4DUPq8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4DUPq8_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNd16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4LNd16_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNd32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4LNd32_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNd8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4LNd8_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNq16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4LNq16_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4LNq32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4LNq32_UPD, - ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VLD4d16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4d16_UPD, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4d32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4d32_UPD, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4d8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4d8_UPD, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4q16, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4q16_UPD, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4q32, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4q32_UPD, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4q8, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLD4q8_UPD, ARM_INS_VLD4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDMDIA, ARM_INS_VLDMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDMSIA, ARM_INS_VLDMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDRD, ARM_INS_VLDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLDRH, ARM_INS_VLDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLDRS, ARM_INS_VLDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VLLDM, ARM_INS_VLLDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VLSTM, ARM_INS_VLSTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXNMD, - ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMAXNMH, ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXNMNDf, ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXNMNDh, ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXNMNQf, ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXNMNQh, ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXNMS, ARM_INS_VMAXNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXfd, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXfq, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXhd, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXhq, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMAXsv16i8, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXsv2i32, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXsv4i16, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXsv4i32, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXsv8i16, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXsv8i8, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXuv16i8, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXuv2i32, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXuv4i16, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXuv4i32, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXuv8i16, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMAXuv8i8, ARM_INS_VMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINNMD, - ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMINNMH, ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINNMNDf, ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINNMNDh, ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINNMNQf, ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINNMNQh, ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINNMS, ARM_INS_VMINNM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VMINfd, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINfq, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINhd, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINhq, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMINsv16i8, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINsv2i32, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINsv4i16, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINsv4i32, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINsv8i16, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINsv8i8, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINuv16i8, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINuv2i32, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINuv4i16, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINuv4i32, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINuv8i16, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMINuv8i8, ARM_INS_VMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAD, - ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLAH, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLALslsv2i32, - ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLALslsv4i16, - ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLALsluv2i32, - ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLALsluv4i16, - ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLALsv2i64, ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLALsv4i32, ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLALsv8i16, ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLALuv2i64, ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLALuv4i32, ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLALuv8i16, ARM_INS_VMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAS, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAfd, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAfq, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAhd, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLAhq, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslfd, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslfq, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslhd, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslhq, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslv2i32, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslv4i16, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslv4i32, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAslv8i16, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAv16i8, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAv2i32, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAv4i16, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAv4i32, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAv8i16, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLAv8i8, ARM_INS_VMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSD, - ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLSH, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLSLslsv2i32, - ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLSLslsv4i16, - ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLSLsluv2i32, - ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLSLsluv4i16, - ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMLSLsv2i64, ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSLsv4i32, ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSLsv8i16, ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSLuv2i64, ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSLuv4i32, ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSLuv8i16, ARM_INS_VMLSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSS, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSfd, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSfq, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLShd, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLShq, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslfd, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslfq, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslhd, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslhq, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslv2i32, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslv4i16, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslv4i32, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSslv8i16, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSv16i8, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSv2i32, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSv4i16, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSv4i32, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSv8i16, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMLSv8i8, ARM_INS_VMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVD, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVDRR, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVH, ARM_INS_VMOVX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMOVHR, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMOVLsv2i64, ARM_INS_VMOVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVLsv4i32, ARM_INS_VMOVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVLsv8i16, ARM_INS_VMOVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVLuv2i64, ARM_INS_VMOVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVLuv4i32, ARM_INS_VMOVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVLuv8i16, ARM_INS_VMOVL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVNv2i32, ARM_INS_VMOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVNv4i16, ARM_INS_VMOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVNv8i8, ARM_INS_VMOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVRH, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMOVRRD, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVRRS, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVRS, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVS, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVSR, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVSRR, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv16i8, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv1i64, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv2f32, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv2i32, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv2i64, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv4f32, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv4i16, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv4i32, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv8i16, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMOVv8i8, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS, - ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, - { 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMRS_FPEXC, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS_FPINST, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS_FPINST2, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS_FPSID, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS_MVFR0, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS_MVFR1, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMRS_MVFR2, ARM_INS_VMRS, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VMSR, ARM_INS_VMSR, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMSR_FPEXC, ARM_INS_VMSR, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMSR_FPINST, ARM_INS_VMSR, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMSR_FPINST2, - ARM_INS_VMSR, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_FPSCR, 0 }, - { ARM_GRP_VFP2, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMSR_FPSID, ARM_INS_VMSR, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMULD, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VMULH, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMULLp64, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLp8, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLslsv2i32, - ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMULLslsv4i16, - ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMULLsluv2i32, - ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMULLsluv4i16, - ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VMULLsv2i64, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLsv4i32, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLsv8i16, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLuv2i64, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLuv4i32, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULLuv8i16, ARM_INS_VMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULS, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VMULfd, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULfq, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULhd, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMULhq, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMULpd, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULpq, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULslfd, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULslfq, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULslhd, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMULslhq, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VMULslv2i32, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULslv4i16, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULslv4i32, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULslv8i16, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULv16i8, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULv2i32, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULv4i16, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULv4i32, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULv8i16, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMULv8i8, ARM_INS_VMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMVNd, ARM_INS_VMVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMVNq, ARM_INS_VMVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMVNv2i32, ARM_INS_VMVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMVNv4i16, ARM_INS_VMVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMVNv4i32, ARM_INS_VMVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VMVNv8i16, ARM_INS_VMVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGD, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGH, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VNEGS, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGf32q, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGfd, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGhd, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VNEGhq, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VNEGs16d, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGs16q, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGs32d, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGs32q, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGs8d, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNEGs8q, ARM_INS_VNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VNMLAD, - ARM_INS_VNMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, - 0, - 0 -#endif - }, - - { ARM_VNMLAH, ARM_INS_VNMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VNMLAS, ARM_INS_VNMLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VNMLSD, - ARM_INS_VNMLS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, - 0, - 0 -#endif - }, - - { ARM_VNMLSH, ARM_INS_VNMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VNMLSS, ARM_INS_VNMLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 -#endif - }, - - { ARM_VNMULD, ARM_INS_VNMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VNMULH, ARM_INS_VNMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VNMULS, ARM_INS_VNMUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VORNd, ARM_INS_VORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORNq, ARM_INS_VORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORRd, ARM_INS_VORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORRiv2i32, ARM_INS_VORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORRiv4i16, ARM_INS_VORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORRiv4i32, ARM_INS_VORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORRiv8i16, ARM_INS_VORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VORRq, ARM_INS_VORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADALsv16i8, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALsv2i32, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALsv4i16, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALsv4i32, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALsv8i16, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALsv8i8, ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADALuv16i8, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALuv2i32, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALuv4i16, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALuv4i32, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALuv8i16, - ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADALuv8i8, ARM_INS_VPADAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADDLsv16i8, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLsv2i32, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLsv4i16, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLsv4i32, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLsv8i16, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLsv8i8, ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADDLuv16i8, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLuv2i32, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLuv4i16, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLuv4i32, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLuv8i16, - ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VPADDLuv8i8, ARM_INS_VPADDL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADDf, ARM_INS_VPADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADDh, ARM_INS_VPADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VPADDi16, ARM_INS_VPADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADDi32, ARM_INS_VPADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPADDi8, ARM_INS_VPADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXf, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXh, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXs16, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXs32, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXs8, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXu16, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXu32, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMAXu8, ARM_INS_VPMAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINf, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINh, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VPMINs16, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINs32, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINs8, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINu16, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINu32, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VPMINu8, ARM_INS_VPMIN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQABSv16i8, ARM_INS_VQABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQABSv2i32, ARM_INS_VQABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQABSv4i16, ARM_INS_VQABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQABSv4i32, ARM_INS_VQABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQABSv8i16, ARM_INS_VQABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQABSv8i8, ARM_INS_VQABS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv16i8, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv1i64, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv2i32, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv2i64, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv4i16, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv4i32, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv8i16, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDsv8i8, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv16i8, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv1i64, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv2i32, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv2i64, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv4i16, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv4i32, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv8i16, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQADDuv8i8, ARM_INS_VQADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQDMLALslv2i32, - ARM_INS_VQDMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLALslv4i16, - ARM_INS_VQDMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLALv2i64, - ARM_INS_VQDMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLALv4i32, - ARM_INS_VQDMLAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLSLslv2i32, - ARM_INS_VQDMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLSLslv4i16, - ARM_INS_VQDMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLSLv2i64, - ARM_INS_VQDMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMLSLv4i32, - ARM_INS_VQDMLSL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHslv2i32, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHslv4i16, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHslv4i32, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHslv8i16, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHv2i32, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHv4i16, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHv4i32, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULHv8i16, - ARM_INS_VQDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULLslv2i32, - ARM_INS_VQDMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULLslv4i16, - ARM_INS_VQDMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULLv2i64, - ARM_INS_VQDMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQDMULLv4i32, - ARM_INS_VQDMULL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNsuv2i32, - ARM_INS_VQMOVUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNsuv4i16, - ARM_INS_VQMOVUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNsuv8i8, - ARM_INS_VQMOVUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNsv2i32, - ARM_INS_VQMOVN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNsv4i16, - ARM_INS_VQMOVN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQMOVNuv2i32, - ARM_INS_VQMOVN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNuv4i16, - ARM_INS_VQMOVN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQNEGv16i8, ARM_INS_VQNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQNEGv2i32, ARM_INS_VQNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQNEGv4i16, ARM_INS_VQNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQNEGv4i32, ARM_INS_VQNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQNEGv8i16, ARM_INS_VQNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQNEGv8i8, ARM_INS_VQNEG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQRDMLAHslv2i32, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHslv4i16, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHslv4i32, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHslv8i16, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHv2i32, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHv4i16, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHv4i32, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLAHv8i16, - ARM_INS_VQRDMLAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHslv2i32, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHslv4i16, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHslv4i32, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHslv8i16, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHv2i32, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHv4i16, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHv4i32, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMLSHv8i16, - ARM_INS_VQRDMLSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHslv2i32, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHslv4i16, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHslv4i32, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHslv8i16, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHv2i32, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHv4i16, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHv4i32, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRDMULHv8i16, - ARM_INS_VQRDMULH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv16i8, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv1i64, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv2i32, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv2i64, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv4i16, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv4i32, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv8i16, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQRSHLuv16i8, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv1i64, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv2i32, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv2i64, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv4i16, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv4i32, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv8i16, - ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQRSHRNsv2i32, - ARM_INS_VQRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRNsv4i16, - ARM_INS_VQRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRNsv8i8, - ARM_INS_VQRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRNuv2i32, - ARM_INS_VQRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRNuv4i16, - ARM_INS_VQRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRNuv8i8, - ARM_INS_VQRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRUNv2i32, - ARM_INS_VQRSHRUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRUNv4i16, - ARM_INS_VQRSHRUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQRSHRUNv8i8, - ARM_INS_VQRSHRUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv16i8, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv1i64, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv2i32, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv2i64, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv4i16, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv4i32, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv8i16, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsiv8i8, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsuv16i8, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv1i64, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv2i32, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv2i64, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv4i16, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv4i32, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv8i16, - ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv16i8, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv1i64, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv2i32, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv2i64, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv4i16, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv4i32, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv8i16, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLsv8i8, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuiv16i8, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv1i64, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv2i32, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv2i64, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv4i16, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv4i32, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv8i16, - ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHLuiv8i8, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv16i8, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv1i64, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv2i32, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv2i64, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv4i16, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv4i32, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv8i16, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHLuv8i8, ARM_INS_VQSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHRNsv2i32, - ARM_INS_VQSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHRNsv4i16, - ARM_INS_VQSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHRNuv2i32, - ARM_INS_VQSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHRNuv4i16, - ARM_INS_VQSHRN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSHRUNv2i32, - ARM_INS_VQSHRUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHRUNv4i16, - ARM_INS_VQSHRUN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv16i8, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv1i64, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv2i32, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv2i64, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv4i16, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv4i32, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv8i16, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBsv8i8, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv16i8, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv1i64, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv2i32, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv2i64, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv4i16, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv4i32, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv8i16, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VQSUBuv8i8, ARM_INS_VQSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRADDHNv2i32, - ARM_INS_VRADDHN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRADDHNv4i16, - ARM_INS_VRADDHN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRADDHNv8i8, ARM_INS_VRADDHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPEd, ARM_INS_VRECPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPEfd, ARM_INS_VRECPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPEfq, ARM_INS_VRECPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPEhd, ARM_INS_VRECPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRECPEhq, ARM_INS_VRECPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRECPEq, ARM_INS_VRECPE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPSfd, ARM_INS_VRECPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPSfq, ARM_INS_VRECPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRECPShd, ARM_INS_VRECPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRECPShq, ARM_INS_VRECPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VREV16d8, ARM_INS_VREV16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV16q8, ARM_INS_VREV16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV32d16, ARM_INS_VREV32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV32d8, ARM_INS_VREV32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV32q16, ARM_INS_VREV32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV32q8, ARM_INS_VREV32, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV64d16, ARM_INS_VREV64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV64d32, ARM_INS_VREV64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV64d8, ARM_INS_VREV64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV64q16, ARM_INS_VREV64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV64q32, ARM_INS_VREV64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VREV64q8, ARM_INS_VREV64, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRHADDsv16i8, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDsv2i32, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDsv4i16, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDsv4i32, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDsv8i16, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDsv8i8, ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRHADDuv16i8, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDuv2i32, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDuv4i16, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDuv4i32, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDuv8i16, - ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRHADDuv8i8, ARM_INS_VRHADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTAD, - ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTAH, ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTANDf, ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTANDh, ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTANQf, ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTANQh, ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTAS, ARM_INS_VRINTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTMD, - ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTMH, ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTMNDf, ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTMNDh, ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTMNQf, ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTMNQh, ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTMS, ARM_INS_VRINTM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTND, - ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTNH, ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTNNDf, ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTNNDh, ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTNNQf, ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTNNQh, ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTNS, ARM_INS_VRINTN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTPD, - ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTPH, ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTPNDf, ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTPNDh, ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTPNQf, ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTPNQh, ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTPS, ARM_INS_VRINTP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTRD, - ARM_INS_VRINTR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTRH, ARM_INS_VRINTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTRS, ARM_INS_VRINTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTXD, - ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTXH, ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTXNDf, ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTXNDh, ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTXNQf, ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTXNQh, ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTXS, ARM_INS_VRINTX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRINTZD, - ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRINTZH, ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTZNDf, ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTZNDh, ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTZNQf, ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTZNQh, ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRINTZS, ARM_INS_VRINTZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv16i8, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv1i64, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv2i32, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv2i64, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv4i16, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv4i32, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv8i16, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLsv8i8, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv16i8, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv1i64, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv2i32, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv2i64, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv4i16, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv4i32, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv8i16, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHLuv8i8, ARM_INS_VRSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRNv2i32, ARM_INS_VRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRNv4i16, ARM_INS_VRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRNv8i8, ARM_INS_VRSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv16i8, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv1i64, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv2i32, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv2i64, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv4i16, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv4i32, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv8i16, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRsv8i8, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv16i8, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv1i64, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv2i32, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv2i64, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv4i16, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv4i32, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv8i16, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSHRuv8i8, ARM_INS_VRSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTEd, ARM_INS_VRSQRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTEfd, ARM_INS_VRSQRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTEfq, ARM_INS_VRSQRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTEhd, ARM_INS_VRSQRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTEhq, ARM_INS_VRSQRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTEq, ARM_INS_VRSQRTE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTSfd, ARM_INS_VRSQRTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTSfq, ARM_INS_VRSQRTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTShd, ARM_INS_VRSQRTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRSQRTShq, ARM_INS_VRSQRTS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv16i8, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv1i64, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv2i32, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv2i64, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv4i16, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv4i32, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv8i16, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAsv8i8, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv16i8, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv1i64, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv2i32, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv2i64, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv4i16, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv4i32, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv8i16, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSRAuv8i8, ARM_INS_VRSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VRSUBHNv2i32, - ARM_INS_VRSUBHN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRSUBHNv4i16, - ARM_INS_VRSUBHN, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSDOTD, ARM_INS_VSDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSDOTDI, ARM_INS_VSDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSDOTQ, ARM_INS_VSDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSDOTQI, ARM_INS_VSDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSELEQD, - ARM_INS_VSELEQ, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VSELEQH, ARM_INS_VSELEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSELEQS, ARM_INS_VSELEQ, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VSELGED, - ARM_INS_VSELGE, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VSELGEH, ARM_INS_VSELGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSELGES, ARM_INS_VSELGE, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VSELGTD, - ARM_INS_VSELGT, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VSELGTH, ARM_INS_VSELGT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSELGTS, ARM_INS_VSELGT, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VSELVSD, - ARM_INS_VSELVS, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, - { 0 }, - { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VSELVSH, ARM_INS_VSELVS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSELVSS, ARM_INS_VSELVS, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 -#endif - }, - - { ARM_VSETLNi16, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSETLNi32, ARM_INS_FMDHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSETLNi8, ARM_INS_VMOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLi16, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLi32, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLi8, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLsv2i64, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLsv4i32, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLsv8i16, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLuv2i64, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLuv4i32, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLLuv8i16, ARM_INS_VSHLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv16i8, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv1i64, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv2i32, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv2i64, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv4i16, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv4i32, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv8i16, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLiv8i8, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv16i8, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv1i64, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv2i32, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv2i64, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv4i16, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv4i32, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv8i16, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLsv8i8, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv16i8, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv1i64, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv2i32, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv2i64, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv4i16, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv4i32, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv8i16, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHLuv8i8, ARM_INS_VSHL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRNv2i32, ARM_INS_VSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRNv4i16, ARM_INS_VSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRNv8i8, ARM_INS_VSHRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv16i8, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv1i64, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv2i32, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv2i64, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv4i16, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv4i32, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv8i16, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRsv8i8, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv16i8, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv1i64, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv2i32, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv2i64, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv4i16, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv4i32, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv8i16, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHRuv8i8, ARM_INS_VSHR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSHTOD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VSHTOH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSHTOS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSITOD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VSITOH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSITOS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv16i8, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv1i64, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv2i32, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv2i64, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv4i16, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv4i32, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv8i16, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLIv8i8, ARM_INS_VSLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSLTOD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VSLTOH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSLTOS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSQRTD, ARM_INS_VSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VSQRTH, ARM_INS_VSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSQRTS, ARM_INS_VSQRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv16i8, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv1i64, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv2i32, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv2i64, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv4i16, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv4i32, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv8i16, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAsv8i8, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv16i8, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv1i64, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv2i32, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv2i64, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv4i16, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv4i32, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv8i16, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRAuv8i8, ARM_INS_VSRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv16i8, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv1i64, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv2i32, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv2i64, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv4i16, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv4i32, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv8i16, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSRIv8i8, ARM_INS_VSRI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1LNd16, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1LNd16_UPD, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNd32, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1LNd32_UPD, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1LNd8, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1LNd8_UPD, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d16, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d16Q, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d16Qwb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d16Qwb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d16T, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d16Twb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d16Twb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d16wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d16wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d32, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d32Q, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d32Qwb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d32Qwb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d32T, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d32Twb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d32Twb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d32wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d32wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d64, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d64Q, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d64Qwb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d64Qwb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d64T, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d64Twb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d64Twb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d64wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d64wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d8, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d8Q, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d8Qwb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d8Qwb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d8T, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1d8Twb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d8Twb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d8wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1d8wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q16, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1q16wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q16wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q32, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1q32wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q32wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q64, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1q64wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q64wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q8, ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST1q8wb_fixed, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST1q8wb_register, - ARM_INS_VST1, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNd16, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2LNd16_UPD, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNd32, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2LNd32_UPD, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNd8, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2LNd8_UPD, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNq16, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2LNq16_UPD, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2LNq32, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2LNq32_UPD, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2b16, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2b16wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2b16wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2b32, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2b32wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2b32wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2b8, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2b8wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2b8wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2d16, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2d16wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2d16wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2d32, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2d32wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2d32wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2d8, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2d8wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2d8wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2q16, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2q16wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2q16wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2q32, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2q32wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2q32wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2q8, ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST2q8wb_fixed, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST2q8wb_register, - ARM_INS_VST2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNd16, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3LNd16_UPD, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNd32, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3LNd32_UPD, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNd8, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3LNd8_UPD, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNq16, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3LNq16_UPD, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3LNq32, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3LNq32_UPD, - ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST3d16, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3d16_UPD, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3d32, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3d32_UPD, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3d8, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3d8_UPD, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3q16, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3q16_UPD, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3q32, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3q32_UPD, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3q8, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST3q8_UPD, ARM_INS_VST3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4LNd16, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4LNd16_UPD, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNd32, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4LNd32_UPD, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNd8, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4LNd8_UPD, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNq16, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4LNq16_UPD, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4LNq32, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4LNq32_UPD, - ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_NEON, 0 }, - 0, - 0 -#endif - }, - - { ARM_VST4d16, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4d16_UPD, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4d32, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4d32_UPD, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4d8, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4d8_UPD, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4q16, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4q16_UPD, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4q32, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4q32_UPD, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4q8, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VST4q8_UPD, ARM_INS_VST4, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTMDIA, ARM_INS_VSTMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTMSIA, ARM_INS_VSTMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTRD, ARM_INS_VSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSTRH, ARM_INS_VSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSTRS, ARM_INS_VSTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBD, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBH, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSUBHNv2i32, ARM_INS_VSUBHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBHNv4i16, ARM_INS_VSUBHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBHNv8i8, ARM_INS_VSUBHN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBLsv2i64, ARM_INS_VSUBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBLsv4i32, ARM_INS_VSUBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBLsv8i16, ARM_INS_VSUBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBLuv2i64, ARM_INS_VSUBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBLuv4i32, ARM_INS_VSUBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBLuv8i16, ARM_INS_VSUBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBS, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBWsv2i64, ARM_INS_VSUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBWsv4i32, ARM_INS_VSUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBWsv8i16, ARM_INS_VSUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBWuv2i64, ARM_INS_VSUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBWuv4i32, ARM_INS_VSUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBWuv8i16, ARM_INS_VSUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBfd, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBfq, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBhd, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSUBhq, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv16i8, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv1i64, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv2i32, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv2i64, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv4i16, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv4i32, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv8i16, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSUBv8i8, ARM_INS_VSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSWPd, ARM_INS_VSWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VSWPq, ARM_INS_VSWP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBL1, ARM_INS_VTBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBL2, ARM_INS_VTBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBL3, ARM_INS_VTBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBL4, ARM_INS_VTBL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBX1, ARM_INS_VTBX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBX2, ARM_INS_VTBX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBX3, ARM_INS_VTBX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTBX4, ARM_INS_VTBX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSHD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSHH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOSHS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSIRD, - ARM_INS_VCVTR, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, - { 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VTOSIRH, ARM_INS_VCVTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOSIRS, ARM_INS_VCVTR, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSIZD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSIZH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOSIZS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSLD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VTOSLH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOSLS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOUHD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VTOUHH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOUHS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOUIRD, - ARM_INS_VCVTR, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, - { 0 }, - { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, - 0, - 0 -#endif - }, - - { ARM_VTOUIRH, ARM_INS_VCVTR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOUIRS, ARM_INS_VCVTR, -#ifndef CAPSTONE_DIET - { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOUIZD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VTOUIZH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOUIZS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTOULD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VTOULH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VTOULS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VTRNd16, ARM_INS_VTRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTRNd32, ARM_INS_VTRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTRNd8, ARM_INS_VTRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTRNq16, ARM_INS_VTRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTRNq32, ARM_INS_VTRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTRNq8, ARM_INS_VTRN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTSTv16i8, ARM_INS_VTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTSTv2i32, ARM_INS_VTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTSTv4i16, ARM_INS_VTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTSTv4i32, ARM_INS_VTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTSTv8i16, ARM_INS_VTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VTSTv8i8, ARM_INS_VTST, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VUDOTD, ARM_INS_VUDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VUDOTDI, ARM_INS_VUDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VUDOTQ, ARM_INS_VUDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VUDOTQI, ARM_INS_VUDOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VUHTOD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VUHTOH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VUHTOS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VUITOD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VUITOH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VUITOS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VULTOD, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 -#endif - }, - - { ARM_VULTOH, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_VULTOS, ARM_INS_VCVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 -#endif - }, - - { ARM_VUZPd16, ARM_INS_VUZP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VUZPd8, ARM_INS_VUZP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VUZPq16, ARM_INS_VUZP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VUZPq32, ARM_INS_VUZP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VUZPq8, ARM_INS_VUZP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VZIPd16, ARM_INS_VZIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VZIPd8, ARM_INS_VZIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VZIPq16, ARM_INS_VZIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VZIPq32, ARM_INS_VZIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_VZIPq8, ARM_INS_VZIP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 -#endif - }, - - { ARM_sysLDMDA, ARM_INS_LDMDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysLDMDA_UPD, - ARM_INS_LDMDA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysLDMDB, ARM_INS_LDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysLDMDB_UPD, - ARM_INS_LDMDB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysLDMIA, ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysLDMIA_UPD, - ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysLDMIB, ARM_INS_LDMIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysLDMIB_UPD, - ARM_INS_LDMIB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysSTMDA, ARM_INS_STMDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysSTMDA_UPD, - ARM_INS_STMDA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysSTMDB, ARM_INS_STMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysSTMDB_UPD, - ARM_INS_STMDB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysSTMIA, ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysSTMIA_UPD, - ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_sysSTMIB, ARM_INS_STMIB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 -#endif - }, - - { ARM_sysSTMIB_UPD, - ARM_INS_STMIB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_ARM, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2ADCri, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADCrr, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADCrs, ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADDri, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADDri12, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADDrr, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADDrs, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ADR, ARM_INS_ADR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ANDri, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ANDrr, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ANDrs, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ASRri, ARM_INS_ASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ASRrr, ARM_INS_ASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2B, ARM_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, - 1, 0 -#endif - }, - - { ARM_t2BFC, ARM_INS_BFC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2BFI, ARM_INS_BFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2BICri, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2BICrr, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2BICrs, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2BXJ, - ARM_INS_BXJ, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, - 0, - 1 -#endif - }, - - { ARM_t2Bcc, ARM_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, - 1, 0 -#endif - }, - - { ARM_t2CDP, - ARM_INS_CDP, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CDP2, - ARM_INS_CDP2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CLREX, ARM_INS_CLREX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_t2CLZ, ARM_INS_CLZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CMNri, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CMNzrr, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CMNzrs, ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CMPri, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CMPrr, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CMPrs, ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2CPS1p, - ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CPS2p, - ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CPS3p, - ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CRC32B, - ARM_INS_CRC32B, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CRC32CB, - ARM_INS_CRC32CB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CRC32CH, - ARM_INS_CRC32CH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CRC32CW, - ARM_INS_CRC32CW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CRC32H, - ARM_INS_CRC32H, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2CRC32W, - ARM_INS_CRC32W, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2DBG, ARM_INS_DBG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2DCPS1, ARM_INS_DCPS1, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2DCPS2, ARM_INS_DCPS2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2DCPS3, ARM_INS_DCPS3, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2DMB, ARM_INS_DMB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, - 0 -#endif - }, - - { ARM_t2DSB, ARM_INS_DSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, - 0 -#endif - }, - - { ARM_t2EORri, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2EORrr, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2EORrs, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2HINT, ARM_INS_HINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2HVC, - ARM_INS_HVC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2ISB, ARM_INS_ISB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, - 0 -#endif - }, - - { ARM_t2IT, - ARM_INS_IT, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_ITSTATE, 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDA, ARM_INS_LDA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDAB, ARM_INS_LDAB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDAEX, ARM_INS_LDAEX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDAEXB, ARM_INS_LDAEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDAEXD, ARM_INS_LDAEXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDAEXH, ARM_INS_LDAEXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDAH, ARM_INS_LDAH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDC2L_OFFSET, - ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2L_OPTION, - ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2L_POST, - ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2L_PRE, - ARM_INS_LDC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2_OFFSET, - ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2_OPTION, - ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2_POST, - ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC2_PRE, - ARM_INS_LDC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDCL_OFFSET, - ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDCL_OPTION, - ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDCL_POST, ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDCL_PRE, ARM_INS_LDCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDC_OFFSET, - ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC_OPTION, - ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDC_POST, ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDC_PRE, ARM_INS_LDC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDMDB, ARM_INS_LDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDMDB_UPD, ARM_INS_LDMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDMIA, ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDMIA_UPD, ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRBT, ARM_INS_LDRBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRB_POST, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRB_PRE, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRBi12, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRBi8, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRBpci, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRBs, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRD_POST, ARM_INS_LDRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRD_PRE, ARM_INS_LDRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRDi8, ARM_INS_LDRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDREX, ARM_INS_LDREX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDREXB, ARM_INS_LDREXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDREXD, - ARM_INS_LDREXD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDREXH, ARM_INS_LDREXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRHT, ARM_INS_LDRHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRH_POST, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRH_PRE, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRHi12, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRHi8, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRHpci, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRHs, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSBT, ARM_INS_LDRSBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSB_POST, - ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDRSB_PRE, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSBi12, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSBi8, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSBpci, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSBs, ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSHT, ARM_INS_LDRSHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSH_POST, - ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2LDRSH_PRE, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSHi12, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSHi8, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSHpci, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRSHs, ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRT, ARM_INS_LDRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDR_POST, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDR_PRE, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRi12, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRi8, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRpci, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LDRs, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LSLri, ARM_INS_LSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LSLrr, ARM_INS_LSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LSRri, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2LSRrr, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MCR, ARM_INS_MCR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MCR2, - ARM_INS_MCR2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MCRR, ARM_INS_MCRR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, - 0 -#endif - }, - - { ARM_t2MCRR2, - ARM_INS_MCRR2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MLA, ARM_INS_MLA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 -#endif - }, - - { ARM_t2MLS, ARM_INS_MLS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVTi16, ARM_INS_MOVT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVi, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVi16, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVr, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MOVsra_flag, - ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MOVsrl_flag, - ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MRC, ARM_INS_MRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MRC2, - ARM_INS_MRC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MRRC, ARM_INS_MRRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MRRC2, ARM_INS_MRRC2, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 -#endif - }, - - { ARM_t2MRS_AR, - ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MRS_M, ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 -#endif - }, - - { ARM_t2MRSbanked, - ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MRSsys_AR, - ARM_INS_MRS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MSR_AR, - ARM_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MSR_M, ARM_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 -#endif - }, - - { ARM_t2MSRbanked, - ARM_INS_MSR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2MUL, ARM_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MVNi, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MVNr, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2MVNs, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ORNri, ARM_INS_ORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ORNrr, ARM_INS_ORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ORNrs, ARM_INS_ORN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ORRri, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ORRrr, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2ORRrs, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2PKHBT, - ARM_INS_PKHBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2PKHTB, - ARM_INS_PKHTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2PLDWi12, - ARM_INS_PLDW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2PLDWi8, - ARM_INS_PLDW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2PLDWs, - ARM_INS_PLDW, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2PLDi12, ARM_INS_PLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLDi8, ARM_INS_PLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLDpci, ARM_INS_PLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLDs, ARM_INS_PLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLIi12, ARM_INS_PLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLIi8, ARM_INS_PLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLIpci, ARM_INS_PLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_t2PLIs, ARM_INS_PLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 -#endif - }, - - { ARM_t2QADD, ARM_INS_QADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2QADD16, - ARM_INS_QADD16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2QADD8, - ARM_INS_QADD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2QASX, ARM_INS_QASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2QDADD, - ARM_INS_QDADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2QDSUB, - ARM_INS_QDSUB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2QSAX, ARM_INS_QSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2QSUB, ARM_INS_QSUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2QSUB16, - ARM_INS_QSUB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2QSUB8, - ARM_INS_QSUB8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2RBIT, ARM_INS_RBIT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2REV, ARM_INS_REV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2REV16, ARM_INS_REV16, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2REVSH, ARM_INS_REVSH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2RFEDB, - ARM_INS_RFEDB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2RFEDBW, - ARM_INS_RFEDB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2RFEIA, - ARM_INS_RFEIA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2RFEIAW, - ARM_INS_RFEIA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2RORri, ARM_INS_ROR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2RORrr, ARM_INS_ROR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2RRX, ARM_INS_RRX, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2RSBri, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2RSBrr, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2RSBrs, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SADD16, - ARM_INS_SADD16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SADD8, - ARM_INS_SADD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SASX, ARM_INS_SASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2SBCri, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SBCrr, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SBCrs, ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SBFX, ARM_INS_SBFX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SDIV, ARM_INS_SDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SEL, ARM_INS_SEL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 -#endif - }, - - { ARM_t2SETPAN, ARM_INS_SETPAN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2SG, ARM_INS_SG, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2SHADD16, - ARM_INS_SHADD16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SHADD8, - ARM_INS_SHADD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SHASX, - ARM_INS_SHASX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SHSAX, - ARM_INS_SHSAX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SHSUB16, - ARM_INS_SHSUB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SHSUB8, - ARM_INS_SHSUB8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMC, - ARM_INS_SMC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLABB, - ARM_INS_SMLABB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLABT, - ARM_INS_SMLABT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLAD, - ARM_INS_SMLAD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLADX, - ARM_INS_SMLADX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLAL, ARM_INS_SMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SMLALBB, - ARM_INS_SMLALBB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLALBT, - ARM_INS_SMLALBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLALD, - ARM_INS_SMLALD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLALDX, - ARM_INS_SMLALDX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLALTB, - ARM_INS_SMLALTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLALTT, - ARM_INS_SMLALTT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLATB, - ARM_INS_SMLATB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLATT, - ARM_INS_SMLATT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLAWB, - ARM_INS_SMLAWB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLAWT, - ARM_INS_SMLAWT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLSD, - ARM_INS_SMLSD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLSDX, - ARM_INS_SMLSDX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLSLD, - ARM_INS_SMLSLD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMLSLDX, - ARM_INS_SMLSLDX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMMLA, - ARM_INS_SMMLA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMMLAR, - ARM_INS_SMMLAR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMMLS, - ARM_INS_SMMLS, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMMLSR, - ARM_INS_SMMLSR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMMUL, - ARM_INS_SMMUL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMMULR, - ARM_INS_SMMULR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMUAD, - ARM_INS_SMUAD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMUADX, - ARM_INS_SMUADX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMULBB, - ARM_INS_SMULBB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMULBT, - ARM_INS_SMULBT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMULL, ARM_INS_SMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SMULTB, - ARM_INS_SMULTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMULTT, - ARM_INS_SMULTT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMULWB, - ARM_INS_SMULWB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMULWT, - ARM_INS_SMULWT, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMUSD, - ARM_INS_SMUSD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SMUSDX, - ARM_INS_SMUSDX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SRSDB, - ARM_INS_SRSDB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SRSDB_UPD, - ARM_INS_SRSDB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SRSIA, - ARM_INS_SRSIA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SRSIA_UPD, - ARM_INS_SRSIA, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SSAT, ARM_INS_SSAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SSAT16, - ARM_INS_SSAT16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SSAX, ARM_INS_SSAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2SSUB16, - ARM_INS_SSUB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SSUB8, - ARM_INS_SSUB8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2L_OFFSET, - ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2L_OPTION, - ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2L_POST, - ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2L_PRE, - ARM_INS_STC2L, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2_OFFSET, - ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2_OPTION, - ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2_POST, - ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC2_PRE, - ARM_INS_STC2, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STCL_OFFSET, - ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STCL_OPTION, - ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STCL_POST, ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STCL_PRE, ARM_INS_STCL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STC_OFFSET, - ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC_OPTION, - ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STC_POST, ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STC_PRE, ARM_INS_STC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STL, ARM_INS_STL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STLB, ARM_INS_STLB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STLEX, ARM_INS_STLEX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STLEXB, ARM_INS_STLEXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STLEXD, ARM_INS_STLEXD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STLEXH, ARM_INS_STLEXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STLH, ARM_INS_STLH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_t2STMDB, ARM_INS_STMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STMDB_UPD, ARM_INS_STMDB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STMIA, ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STMIA_UPD, ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRBT, ARM_INS_STRBT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRB_POST, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRB_PRE, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRBi12, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRBi8, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRBs, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRD_POST, ARM_INS_STRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRD_PRE, ARM_INS_STRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRDi8, ARM_INS_STRD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STREX, ARM_INS_STREX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STREXB, ARM_INS_STREXB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STREXD, - ARM_INS_STREXD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2STREXH, ARM_INS_STREXH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRHT, ARM_INS_STRHT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRH_POST, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRH_PRE, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRHi12, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRHi8, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRHs, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRT, ARM_INS_STRT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STR_POST, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STR_PRE, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRi12, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRi8, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2STRs, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SUBS_PC_LR, - ARM_INS_SUBS, -#ifndef CAPSTONE_DIET - { ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_REG_CPSR, ARM_REG_PC, 0 }, - { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SUBri, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SUBri12, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SUBrr, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SUBrs, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SXTAB, - ARM_INS_SXTAB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SXTAB16, - ARM_INS_SXTAB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SXTAH, - ARM_INS_SXTAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SXTB, ARM_INS_SXTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2SXTB16, - ARM_INS_SXTB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2SXTH, ARM_INS_SXTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TBB, ARM_INS_TBB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 -#endif - }, - - { ARM_t2TBH, ARM_INS_TBH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 -#endif - }, - - { ARM_t2TEQri, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TEQrr, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TEQrs, ARM_INS_TEQ, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TSB, ARM_INS_TSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2TSTri, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TSTrr, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TSTrs, ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2TT, ARM_INS_TT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2TTA, ARM_INS_TTA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2TTAT, ARM_INS_TTAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2TTT, ARM_INS_TTT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_t2UADD16, - ARM_INS_UADD16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UADD8, - ARM_INS_UADD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UASX, ARM_INS_UASX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2UBFX, ARM_INS_UBFX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2UDF, ARM_INS_UDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2UDIV, ARM_INS_UDIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2UHADD16, - ARM_INS_UHADD16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UHADD8, - ARM_INS_UHADD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UHASX, - ARM_INS_UHASX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UHSAX, - ARM_INS_UHSAX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UHSUB16, - ARM_INS_UHSUB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UHSUB8, - ARM_INS_UHSUB8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UMAAL, - ARM_INS_UMAAL, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UMLAL, ARM_INS_UMLAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2UMULL, ARM_INS_UMULL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2UQADD16, - ARM_INS_UQADD16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UQADD8, - ARM_INS_UQADD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UQASX, - ARM_INS_UQASX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UQSAX, - ARM_INS_UQSAX, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UQSUB16, - ARM_INS_UQSUB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UQSUB8, - ARM_INS_UQSUB8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2USAD8, - ARM_INS_USAD8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2USADA8, - ARM_INS_USADA8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2USAT, ARM_INS_USAT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2USAT16, - ARM_INS_USAT16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2USAX, ARM_INS_USAX, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, - 0 -#endif - }, - - { ARM_t2USUB16, - ARM_INS_USUB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2USUB8, - ARM_INS_USUB8, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UXTAB, - ARM_INS_UXTAB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UXTAB16, - ARM_INS_UXTAB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UXTAH, - ARM_INS_UXTAH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UXTB, ARM_INS_UXTB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_t2UXTB16, - ARM_INS_UXTB16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, - 0, - 0 -#endif - }, - - { ARM_t2UXTH, ARM_INS_UXTH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 -#endif - }, - - { ARM_tADC, - ARM_INS_ADC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tADDhirr, - ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tADDi3, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tADDi8, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tADDrSP, - ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tADDrSPi, - ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tADDrr, ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tADDspi, - ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tADDspr, - ARM_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tADR, ARM_INS_ADR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tAND, ARM_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tASRri, ARM_INS_ASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tASRrr, ARM_INS_ASR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tB, - ARM_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 1, - 0 -#endif - }, - - { ARM_tBIC, ARM_INS_BIC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tBKPT, ARM_INS_BKPT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tBL, - ARM_INS_BL, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, - 1, - 0 -#endif - }, - - { ARM_tBLXNSr, ARM_INS_BLXNS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_tBLXi, - ARM_INS_BLX, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, - ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, - 1, - 0 -#endif - }, - - { ARM_tBLXr, - ARM_INS_BLX, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, ARM_REG_PC, 0 }, - { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, - 0, - 1 -#endif - }, - - { ARM_tBX, ARM_INS_BX, -#ifndef CAPSTONE_DIET - { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 -#endif - }, - - { ARM_tBXNS, ARM_INS_BXNS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif - }, - - { ARM_tBcc, - ARM_INS_B, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_PC, 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 1, - 0 -#endif - }, - - { ARM_tCBNZ, - ARM_INS_CBNZ, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, - 1, - 0 -#endif - }, - - { ARM_tCBZ, - ARM_INS_CBZ, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, - 1, - 0 -#endif - }, - - { ARM_tCMNz, - ARM_INS_CMN, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tCMPhir, - ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tCMPi8, - ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tCMPr, - ARM_INS_CMP, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tCPS, ARM_INS_CPS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tEOR, ARM_INS_EOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tHINT, ARM_INS_HINT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 -#endif - }, - - { ARM_tHLT, ARM_INS_HLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 -#endif - }, - - { ARM_tLDMIA, ARM_INS_LDM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLDRBi, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLDRBr, ARM_INS_LDRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLDRHi, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLDRHr, ARM_INS_LDRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLDRSB, - ARM_INS_LDRSB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tLDRSH, - ARM_INS_LDRSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tLDRi, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tLDRpci, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tLDRr, ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tLDRspi, - ARM_INS_LDR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tLSLri, ARM_INS_LSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLSLrr, ARM_INS_LSL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLSRri, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tLSRrr, ARM_INS_LSR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tMOVSr, - ARM_INS_MOVS, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tMOVi8, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tMOVr, ARM_INS_MOV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tMUL, ARM_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tMVN, ARM_INS_MVN, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tORR, ARM_INS_ORR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tPOP, - ARM_INS_POP, -#ifndef CAPSTONE_DIET - { ARM_REG_SP, 0 }, - { ARM_REG_SP, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tPUSH, - ARM_INS_PUSH, -#ifndef CAPSTONE_DIET - { ARM_REG_SP, 0 }, - { ARM_REG_SP, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tREV, - ARM_INS_REV, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, - - { ARM_tREV16, - ARM_INS_REV16, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, - - { ARM_tREVSH, - ARM_INS_REVSH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, - - { ARM_tROR, ARM_INS_ROR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tRSB, ARM_INS_RSB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tSBC, - ARM_INS_SBC, -#ifndef CAPSTONE_DIET - { ARM_REG_CPSR, 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSETEND, - ARM_INS_SETEND, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSTMIA_UPD, - ARM_INS_STM, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSTRBi, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSTRBr, ARM_INS_STRB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSTRHi, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSTRHr, ARM_INS_STRH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSTRi, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tSTRr, ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 -#endif - }, - - { ARM_tSTRspi, - ARM_INS_STR, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSUBi3, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSUBi8, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSUBrr, ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, - 0 -#endif - }, - - { ARM_tSUBspi, - ARM_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSVC, - ARM_INS_SVC, -#ifndef CAPSTONE_DIET - { ARM_REG_PC, 0 }, - { ARM_REG_LR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSXTB, - ARM_INS_SXTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, - - { ARM_tSXTH, - ARM_INS_SXTH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, - - { ARM_tTRAP, ARM_INS_TRAP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 -#endif - }, - - { ARM_tTST, - ARM_INS_TST, -#ifndef CAPSTONE_DIET - { 0 }, - { ARM_REG_CPSR, 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, - 0, - 0 -#endif - }, - - { ARM_tUDF, ARM_INS_UDF, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 -#endif - }, - - { ARM_tUXTB, - ARM_INS_UXTB, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, - - { ARM_tUXTH, - ARM_INS_UXTH, -#ifndef CAPSTONE_DIET - { 0 }, - { 0 }, - { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, - 0, - 0 -#endif - }, diff --git a/arch/ARM/ARMMappingInsnName.inc b/arch/ARM/ARMMappingInsnName.inc deleted file mode 100644 index f7c81e45e9..0000000000 --- a/arch/ARM/ARMMappingInsnName.inc +++ /dev/null @@ -1,475 +0,0 @@ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -"adc", // ARM_INS_ADC, - "add", // ARM_INS_ADD, - "addw", // ARM_INS_ADDW, - "adr", // ARM_INS_ADR, - "aesd", // ARM_INS_AESD, - "aese", // ARM_INS_AESE, - "aesimc", // ARM_INS_AESIMC, - "aesmc", // ARM_INS_AESMC, - "and", // ARM_INS_AND, - "asr", // ARM_INS_ASR, - "b", // ARM_INS_B, - "bfc", // ARM_INS_BFC, - "bfi", // ARM_INS_BFI, - "bic", // ARM_INS_BIC, - "bkpt", // ARM_INS_BKPT, - "bl", // ARM_INS_BL, - "blx", // ARM_INS_BLX, - "blxns", // ARM_INS_BLXNS, - "bx", // ARM_INS_BX, - "bxj", // ARM_INS_BXJ, - "bxns", // ARM_INS_BXNS, - "cbnz", // ARM_INS_CBNZ, - "cbz", // ARM_INS_CBZ, - "cdp", // ARM_INS_CDP, - "cdp2", // ARM_INS_CDP2, - "clrex", // ARM_INS_CLREX, - "clz", // ARM_INS_CLZ, - "cmn", // ARM_INS_CMN, - "cmp", // ARM_INS_CMP, - "cps", // ARM_INS_CPS, - "crc32b", // ARM_INS_CRC32B, - "crc32cb", // ARM_INS_CRC32CB, - "crc32ch", // ARM_INS_CRC32CH, - "crc32cw", // ARM_INS_CRC32CW, - "crc32h", // ARM_INS_CRC32H, - "crc32w", // ARM_INS_CRC32W, - "csdb", // ARM_INS_CSDB, - "dbg", // ARM_INS_DBG, - "dcps1", // ARM_INS_DCPS1, - "dcps2", // ARM_INS_DCPS2, - "dcps3", // ARM_INS_DCPS3, - "dfb", // ARM_INS_DFB, - "dmb", // ARM_INS_DMB, - "dsb", // ARM_INS_DSB, - "eor", // ARM_INS_EOR, - "eret", // ARM_INS_ERET, - "esb", // ARM_INS_ESB, - "faddd", // ARM_INS_FADDD, - "fadds", // ARM_INS_FADDS, - "fcmpzd", // ARM_INS_FCMPZD, - "fcmpzs", // ARM_INS_FCMPZS, - "fconstd", // ARM_INS_FCONSTD, - "fconsts", // ARM_INS_FCONSTS, - "fldmdbx", // ARM_INS_FLDMDBX, - "fldmiax", // ARM_INS_FLDMIAX, - "fmdhr", // ARM_INS_FMDHR, - "fmdlr", // ARM_INS_FMDLR, - "fmstat", // ARM_INS_FMSTAT, - "fstmdbx", // ARM_INS_FSTMDBX, - "fstmiax", // ARM_INS_FSTMIAX, - "fsubd", // ARM_INS_FSUBD, - "fsubs", // ARM_INS_FSUBS, - "hint", // ARM_INS_HINT, - "hlt", // ARM_INS_HLT, - "hvc", // ARM_INS_HVC, - "isb", // ARM_INS_ISB, - "it", // ARM_INS_IT, - "lda", // ARM_INS_LDA, - "ldab", // ARM_INS_LDAB, - "ldaex", // ARM_INS_LDAEX, - "ldaexb", // ARM_INS_LDAEXB, - "ldaexd", // ARM_INS_LDAEXD, - "ldaexh", // ARM_INS_LDAEXH, - "ldah", // ARM_INS_LDAH, - "ldc", // ARM_INS_LDC, - "ldc2", // ARM_INS_LDC2, - "ldc2l", // ARM_INS_LDC2L, - "ldcl", // ARM_INS_LDCL, - "ldm", // ARM_INS_LDM, - "ldmda", // ARM_INS_LDMDA, - "ldmdb", // ARM_INS_LDMDB, - "ldmib", // ARM_INS_LDMIB, - "ldr", // ARM_INS_LDR, - "ldrb", // ARM_INS_LDRB, - "ldrbt", // ARM_INS_LDRBT, - "ldrd", // ARM_INS_LDRD, - "ldrex", // ARM_INS_LDREX, - "ldrexb", // ARM_INS_LDREXB, - "ldrexd", // ARM_INS_LDREXD, - "ldrexh", // ARM_INS_LDREXH, - "ldrh", // ARM_INS_LDRH, - "ldrht", // ARM_INS_LDRHT, - "ldrsb", // ARM_INS_LDRSB, - "ldrsbt", // ARM_INS_LDRSBT, - "ldrsh", // ARM_INS_LDRSH, - "ldrsht", // ARM_INS_LDRSHT, - "ldrt", // ARM_INS_LDRT, - "lsl", // ARM_INS_LSL, - "lsr", // ARM_INS_LSR, - "mcr", // ARM_INS_MCR, - "mcr2", // ARM_INS_MCR2, - "mcrr", // ARM_INS_MCRR, - "mcrr2", // ARM_INS_MCRR2, - "mla", // ARM_INS_MLA, - "mls", // ARM_INS_MLS, - "mov", // ARM_INS_MOV, - "movs", // ARM_INS_MOVS, - "movt", // ARM_INS_MOVT, - "movw", // ARM_INS_MOVW, - "mrc", // ARM_INS_MRC, - "mrc2", // ARM_INS_MRC2, - "mrrc", // ARM_INS_MRRC, - "mrrc2", // ARM_INS_MRRC2, - "mrs", // ARM_INS_MRS, - "msr", // ARM_INS_MSR, - "mul", // ARM_INS_MUL, - "mvn", // ARM_INS_MVN, - "neg", // ARM_INS_NEG, - "nop", // ARM_INS_NOP, - "orn", // ARM_INS_ORN, - "orr", // ARM_INS_ORR, - "pkhbt", // ARM_INS_PKHBT, - "pkhtb", // ARM_INS_PKHTB, - "pld", // ARM_INS_PLD, - "pldw", // ARM_INS_PLDW, - "pli", // ARM_INS_PLI, - "pop", // ARM_INS_POP, - "push", // ARM_INS_PUSH, - "qadd", // ARM_INS_QADD, - "qadd16", // ARM_INS_QADD16, - "qadd8", // ARM_INS_QADD8, - "qasx", // ARM_INS_QASX, - "qdadd", // ARM_INS_QDADD, - "qdsub", // ARM_INS_QDSUB, - "qsax", // ARM_INS_QSAX, - "qsub", // ARM_INS_QSUB, - "qsub16", // ARM_INS_QSUB16, - "qsub8", // ARM_INS_QSUB8, - "rbit", // ARM_INS_RBIT, - "rev", // ARM_INS_REV, - "rev16", // ARM_INS_REV16, - "revsh", // ARM_INS_REVSH, - "rfeda", // ARM_INS_RFEDA, - "rfedb", // ARM_INS_RFEDB, - "rfeia", // ARM_INS_RFEIA, - "rfeib", // ARM_INS_RFEIB, - "ror", // ARM_INS_ROR, - "rrx", // ARM_INS_RRX, - "rsb", // ARM_INS_RSB, - "rsc", // ARM_INS_RSC, - "sadd16", // ARM_INS_SADD16, - "sadd8", // ARM_INS_SADD8, - "sasx", // ARM_INS_SASX, - "sbc", // ARM_INS_SBC, - "sbfx", // ARM_INS_SBFX, - "sdiv", // ARM_INS_SDIV, - "sel", // ARM_INS_SEL, - "setend", // ARM_INS_SETEND, - "setpan", // ARM_INS_SETPAN, - "sev", // ARM_INS_SEV, - "sevl", // ARM_INS_SEVL, - "sg", // ARM_INS_SG, - "sha1c", // ARM_INS_SHA1C, - "sha1h", // ARM_INS_SHA1H, - "sha1m", // ARM_INS_SHA1M, - "sha1p", // ARM_INS_SHA1P, - "sha1su0", // ARM_INS_SHA1SU0, - "sha1su1", // ARM_INS_SHA1SU1, - "sha256h", // ARM_INS_SHA256H, - "sha256h2", // ARM_INS_SHA256H2, - "sha256su0", // ARM_INS_SHA256SU0, - "sha256su1", // ARM_INS_SHA256SU1, - "shadd16", // ARM_INS_SHADD16, - "shadd8", // ARM_INS_SHADD8, - "shasx", // ARM_INS_SHASX, - "shsax", // ARM_INS_SHSAX, - "shsub16", // ARM_INS_SHSUB16, - "shsub8", // ARM_INS_SHSUB8, - "smc", // ARM_INS_SMC, - "smlabb", // ARM_INS_SMLABB, - "smlabt", // ARM_INS_SMLABT, - "smlad", // ARM_INS_SMLAD, - "smladx", // ARM_INS_SMLADX, - "smlal", // ARM_INS_SMLAL, - "smlalbb", // ARM_INS_SMLALBB, - "smlalbt", // ARM_INS_SMLALBT, - "smlald", // ARM_INS_SMLALD, - "smlaldx", // ARM_INS_SMLALDX, - "smlaltb", // ARM_INS_SMLALTB, - "smlaltt", // ARM_INS_SMLALTT, - "smlatb", // ARM_INS_SMLATB, - "smlatt", // ARM_INS_SMLATT, - "smlawb", // ARM_INS_SMLAWB, - "smlawt", // ARM_INS_SMLAWT, - "smlsd", // ARM_INS_SMLSD, - "smlsdx", // ARM_INS_SMLSDX, - "smlsld", // ARM_INS_SMLSLD, - "smlsldx", // ARM_INS_SMLSLDX, - "smmla", // ARM_INS_SMMLA, - "smmlar", // ARM_INS_SMMLAR, - "smmls", // ARM_INS_SMMLS, - "smmlsr", // ARM_INS_SMMLSR, - "smmul", // ARM_INS_SMMUL, - "smmulr", // ARM_INS_SMMULR, - "smuad", // ARM_INS_SMUAD, - "smuadx", // ARM_INS_SMUADX, - "smulbb", // ARM_INS_SMULBB, - "smulbt", // ARM_INS_SMULBT, - "smull", // ARM_INS_SMULL, - "smultb", // ARM_INS_SMULTB, - "smultt", // ARM_INS_SMULTT, - "smulwb", // ARM_INS_SMULWB, - "smulwt", // ARM_INS_SMULWT, - "smusd", // ARM_INS_SMUSD, - "smusdx", // ARM_INS_SMUSDX, - "srsda", // ARM_INS_SRSDA, - "srsdb", // ARM_INS_SRSDB, - "srsia", // ARM_INS_SRSIA, - "srsib", // ARM_INS_SRSIB, - "ssat", // ARM_INS_SSAT, - "ssat16", // ARM_INS_SSAT16, - "ssax", // ARM_INS_SSAX, - "ssub16", // ARM_INS_SSUB16, - "ssub8", // ARM_INS_SSUB8, - "stc", // ARM_INS_STC, - "stc2", // ARM_INS_STC2, - "stc2l", // ARM_INS_STC2L, - "stcl", // ARM_INS_STCL, - "stl", // ARM_INS_STL, - "stlb", // ARM_INS_STLB, - "stlex", // ARM_INS_STLEX, - "stlexb", // ARM_INS_STLEXB, - "stlexd", // ARM_INS_STLEXD, - "stlexh", // ARM_INS_STLEXH, - "stlh", // ARM_INS_STLH, - "stm", // ARM_INS_STM, - "stmda", // ARM_INS_STMDA, - "stmdb", // ARM_INS_STMDB, - "stmib", // ARM_INS_STMIB, - "str", // ARM_INS_STR, - "strb", // ARM_INS_STRB, - "strbt", // ARM_INS_STRBT, - "strd", // ARM_INS_STRD, - "strex", // ARM_INS_STREX, - "strexb", // ARM_INS_STREXB, - "strexd", // ARM_INS_STREXD, - "strexh", // ARM_INS_STREXH, - "strh", // ARM_INS_STRH, - "strht", // ARM_INS_STRHT, - "strt", // ARM_INS_STRT, - "sub", // ARM_INS_SUB, - "subs", // ARM_INS_SUBS, - "subw", // ARM_INS_SUBW, - "svc", // ARM_INS_SVC, - "swp", // ARM_INS_SWP, - "swpb", // ARM_INS_SWPB, - "sxtab", // ARM_INS_SXTAB, - "sxtab16", // ARM_INS_SXTAB16, - "sxtah", // ARM_INS_SXTAH, - "sxtb", // ARM_INS_SXTB, - "sxtb16", // ARM_INS_SXTB16, - "sxth", // ARM_INS_SXTH, - "tbb", // ARM_INS_TBB, - "tbh", // ARM_INS_TBH, - "teq", // ARM_INS_TEQ, - "trap", // ARM_INS_TRAP, - "tsb", // ARM_INS_TSB, - "tst", // ARM_INS_TST, - "tt", // ARM_INS_TT, - "tta", // ARM_INS_TTA, - "ttat", // ARM_INS_TTAT, - "ttt", // ARM_INS_TTT, - "uadd16", // ARM_INS_UADD16, - "uadd8", // ARM_INS_UADD8, - "uasx", // ARM_INS_UASX, - "ubfx", // ARM_INS_UBFX, - "udf", // ARM_INS_UDF, - "udiv", // ARM_INS_UDIV, - "uhadd16", // ARM_INS_UHADD16, - "uhadd8", // ARM_INS_UHADD8, - "uhasx", // ARM_INS_UHASX, - "uhsax", // ARM_INS_UHSAX, - "uhsub16", // ARM_INS_UHSUB16, - "uhsub8", // ARM_INS_UHSUB8, - "umaal", // ARM_INS_UMAAL, - "umlal", // ARM_INS_UMLAL, - "umull", // ARM_INS_UMULL, - "uqadd16", // ARM_INS_UQADD16, - "uqadd8", // ARM_INS_UQADD8, - "uqasx", // ARM_INS_UQASX, - "uqsax", // ARM_INS_UQSAX, - "uqsub16", // ARM_INS_UQSUB16, - "uqsub8", // ARM_INS_UQSUB8, - "usad8", // ARM_INS_USAD8, - "usada8", // ARM_INS_USADA8, - "usat", // ARM_INS_USAT, - "usat16", // ARM_INS_USAT16, - "usax", // ARM_INS_USAX, - "usub16", // ARM_INS_USUB16, - "usub8", // ARM_INS_USUB8, - "uxtab", // ARM_INS_UXTAB, - "uxtab16", // ARM_INS_UXTAB16, - "uxtah", // ARM_INS_UXTAH, - "uxtb", // ARM_INS_UXTB, - "uxtb16", // ARM_INS_UXTB16, - "uxth", // ARM_INS_UXTH, - "vaba", // ARM_INS_VABA, - "vabal", // ARM_INS_VABAL, - "vabd", // ARM_INS_VABD, - "vabdl", // ARM_INS_VABDL, - "vabs", // ARM_INS_VABS, - "vacge", // ARM_INS_VACGE, - "vacgt", // ARM_INS_VACGT, - "vacle", // ARM_INS_VACLE, - "vaclt", // ARM_INS_VACLT, - "vadd", // ARM_INS_VADD, - "vaddhn", // ARM_INS_VADDHN, - "vaddl", // ARM_INS_VADDL, - "vaddw", // ARM_INS_VADDW, - "vand", // ARM_INS_VAND, - "vbic", // ARM_INS_VBIC, - "vbif", // ARM_INS_VBIF, - "vbit", // ARM_INS_VBIT, - "vbsl", // ARM_INS_VBSL, - "vcadd", // ARM_INS_VCADD, - "vceq", // ARM_INS_VCEQ, - "vcge", // ARM_INS_VCGE, - "vcgt", // ARM_INS_VCGT, - "vcle", // ARM_INS_VCLE, - "vcls", // ARM_INS_VCLS, - "vclt", // ARM_INS_VCLT, - "vclz", // ARM_INS_VCLZ, - "vcmla", // ARM_INS_VCMLA, - "vcmp", // ARM_INS_VCMP, - "vcmpe", // ARM_INS_VCMPE, - "vcnt", // ARM_INS_VCNT, - "vcvt", // ARM_INS_VCVT, - "vcvta", // ARM_INS_VCVTA, - "vcvtb", // ARM_INS_VCVTB, - "vcvtm", // ARM_INS_VCVTM, - "vcvtn", // ARM_INS_VCVTN, - "vcvtp", // ARM_INS_VCVTP, - "vcvtr", // ARM_INS_VCVTR, - "vcvtt", // ARM_INS_VCVTT, - "vdiv", // ARM_INS_VDIV, - "vdup", // ARM_INS_VDUP, - "veor", // ARM_INS_VEOR, - "vext", // ARM_INS_VEXT, - "vfma", // ARM_INS_VFMA, - "vfms", // ARM_INS_VFMS, - "vfnma", // ARM_INS_VFNMA, - "vfnms", // ARM_INS_VFNMS, - "vhadd", // ARM_INS_VHADD, - "vhsub", // ARM_INS_VHSUB, - "vins", // ARM_INS_VINS, - "vjcvt", // ARM_INS_VJCVT, - "vld1", // ARM_INS_VLD1, - "vld2", // ARM_INS_VLD2, - "vld3", // ARM_INS_VLD3, - "vld4", // ARM_INS_VLD4, - "vldmdb", // ARM_INS_VLDMDB, - "vldmia", // ARM_INS_VLDMIA, - "vldr", // ARM_INS_VLDR, - "vlldm", // ARM_INS_VLLDM, - "vlstm", // ARM_INS_VLSTM, - "vmax", // ARM_INS_VMAX, - "vmaxnm", // ARM_INS_VMAXNM, - "vmin", // ARM_INS_VMIN, - "vminnm", // ARM_INS_VMINNM, - "vmla", // ARM_INS_VMLA, - "vmlal", // ARM_INS_VMLAL, - "vmls", // ARM_INS_VMLS, - "vmlsl", // ARM_INS_VMLSL, - "vmov", // ARM_INS_VMOV, - "vmovl", // ARM_INS_VMOVL, - "vmovn", // ARM_INS_VMOVN, - "vmovx", // ARM_INS_VMOVX, - "vmrs", // ARM_INS_VMRS, - "vmsr", // ARM_INS_VMSR, - "vmul", // ARM_INS_VMUL, - "vmull", // ARM_INS_VMULL, - "vmvn", // ARM_INS_VMVN, - "vneg", // ARM_INS_VNEG, - "vnmla", // ARM_INS_VNMLA, - "vnmls", // ARM_INS_VNMLS, - "vnmul", // ARM_INS_VNMUL, - "vorn", // ARM_INS_VORN, - "vorr", // ARM_INS_VORR, - "vpadal", // ARM_INS_VPADAL, - "vpadd", // ARM_INS_VPADD, - "vpaddl", // ARM_INS_VPADDL, - "vpmax", // ARM_INS_VPMAX, - "vpmin", // ARM_INS_VPMIN, - "vpop", // ARM_INS_VPOP, - "vpush", // ARM_INS_VPUSH, - "vqabs", // ARM_INS_VQABS, - "vqadd", // ARM_INS_VQADD, - "vqdmlal", // ARM_INS_VQDMLAL, - "vqdmlsl", // ARM_INS_VQDMLSL, - "vqdmulh", // ARM_INS_VQDMULH, - "vqdmull", // ARM_INS_VQDMULL, - "vqmovn", // ARM_INS_VQMOVN, - "vqmovun", // ARM_INS_VQMOVUN, - "vqneg", // ARM_INS_VQNEG, - "vqrdmlah", // ARM_INS_VQRDMLAH, - "vqrdmlsh", // ARM_INS_VQRDMLSH, - "vqrdmulh", // ARM_INS_VQRDMULH, - "vqrshl", // ARM_INS_VQRSHL, - "vqrshrn", // ARM_INS_VQRSHRN, - "vqrshrun", // ARM_INS_VQRSHRUN, - "vqshl", // ARM_INS_VQSHL, - "vqshlu", // ARM_INS_VQSHLU, - "vqshrn", // ARM_INS_VQSHRN, - "vqshrun", // ARM_INS_VQSHRUN, - "vqsub", // ARM_INS_VQSUB, - "vraddhn", // ARM_INS_VRADDHN, - "vrecpe", // ARM_INS_VRECPE, - "vrecps", // ARM_INS_VRECPS, - "vrev16", // ARM_INS_VREV16, - "vrev32", // ARM_INS_VREV32, - "vrev64", // ARM_INS_VREV64, - "vrhadd", // ARM_INS_VRHADD, - "vrinta", // ARM_INS_VRINTA, - "vrintm", // ARM_INS_VRINTM, - "vrintn", // ARM_INS_VRINTN, - "vrintp", // ARM_INS_VRINTP, - "vrintr", // ARM_INS_VRINTR, - "vrintx", // ARM_INS_VRINTX, - "vrintz", // ARM_INS_VRINTZ, - "vrshl", // ARM_INS_VRSHL, - "vrshr", // ARM_INS_VRSHR, - "vrshrn", // ARM_INS_VRSHRN, - "vrsqrte", // ARM_INS_VRSQRTE, - "vrsqrts", // ARM_INS_VRSQRTS, - "vrsra", // ARM_INS_VRSRA, - "vrsubhn", // ARM_INS_VRSUBHN, - "vsdot", // ARM_INS_VSDOT, - "vseleq", // ARM_INS_VSELEQ, - "vselge", // ARM_INS_VSELGE, - "vselgt", // ARM_INS_VSELGT, - "vselvs", // ARM_INS_VSELVS, - "vshl", // ARM_INS_VSHL, - "vshll", // ARM_INS_VSHLL, - "vshr", // ARM_INS_VSHR, - "vshrn", // ARM_INS_VSHRN, - "vsli", // ARM_INS_VSLI, - "vsqrt", // ARM_INS_VSQRT, - "vsra", // ARM_INS_VSRA, - "vsri", // ARM_INS_VSRI, - "vst1", // ARM_INS_VST1, - "vst2", // ARM_INS_VST2, - "vst3", // ARM_INS_VST3, - "vst4", // ARM_INS_VST4, - "vstmdb", // ARM_INS_VSTMDB, - "vstmia", // ARM_INS_VSTMIA, - "vstr", // ARM_INS_VSTR, - "vsub", // ARM_INS_VSUB, - "vsubhn", // ARM_INS_VSUBHN, - "vsubl", // ARM_INS_VSUBL, - "vsubw", // ARM_INS_VSUBW, - "vswp", // ARM_INS_VSWP, - "vtbl", // ARM_INS_VTBL, - "vtbx", // ARM_INS_VTBX, - "vtrn", // ARM_INS_VTRN, - "vtst", // ARM_INS_VTST, - "vudot", // ARM_INS_VUDOT, - "vuzp", // ARM_INS_VUZP, - "vzip", // ARM_INS_VZIP, - "wfe", // ARM_INS_WFE, - "wfi", // ARM_INS_WFI, - "yield", // ARM_INS_YIELD, diff --git a/arch/ARM/ARMMappingInsnOp.inc b/arch/ARM/ARMMappingInsnOp.inc deleted file mode 100644 index 8daecd42e5..0000000000 --- a/arch/ARM/ARMMappingInsnOp.inc +++ /dev/null @@ -1,10739 +0,0 @@ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ -/* By Nguyen Anh Quynh , 2013-2019 */ - -{ /* ARM_ASRi, ARM_INS_ASR: asr */ - { 0 } -}, - - { /* ARM_ASRr, ARM_INS_ASR: asr */ - { 0 } - }, - - { /* ARM_ITasm, ARM_INS_IT: it */ - { 0 } - }, - - { /* ARM_LDRBT_POST, ARM_INS_LDRBT: ldrbt */ - { 0 } - }, - - { /* ARM_LDRConstPool, ARM_INS_LDR: ldr */ - { 0 } - }, - - { /* ARM_LDRT_POST, ARM_INS_LDRT: ldrt */ - { 0 } - }, - - { /* ARM_LSLi, ARM_INS_LSL: lsl */ - { 0 } - }, - - { /* ARM_LSLr, ARM_INS_LSL: lsl */ - { 0 } - }, - - { /* ARM_LSRi, ARM_INS_LSR: lsr */ - { 0 } - }, - - { /* ARM_LSRr, ARM_INS_LSR: lsr */ - { 0 } - }, - - { /* ARM_RORi, ARM_INS_ROR: ror */ - { 0 } - }, - - { /* ARM_RORr, ARM_INS_ROR: ror */ - { 0 } - }, - - { /* ARM_RRXi, ARM_INS_RRX: rrx */ - { 0 } - }, - - { /* ARM_STRBT_POST, ARM_INS_STRBT: strbt */ - { 0 } - }, - - { /* ARM_STRT_POST, ARM_INS_STRT: strt */ - { 0 } - }, - - { /* ARM_VLD1LNdAsm_16, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdAsm_32, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdAsm_8, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1: vld1 */ - { 0 } - }, - - { /* ARM_VLD2LNdAsm_16, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdAsm_32, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdAsm_8, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNqAsm_16, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNqAsm_32, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2: vld2 */ - { 0 } - }, - - { /* ARM_VLD3DUPdAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNqAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNqAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qAsm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qAsm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qAsm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3: vld3 */ - { 0 } - }, - - { /* ARM_VLD4DUPdAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNqAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNqAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qAsm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qAsm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qAsm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4: vld4 */ - { 0 } - }, - - { /* ARM_VST1LNdAsm_16, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdAsm_32, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdAsm_8, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1: vst1 */ - { 0 } - }, - - { /* ARM_VST2LNdAsm_16, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdAsm_32, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdAsm_8, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNqAsm_16, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNqAsm_32, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2: vst2 */ - { 0 } - }, - - { /* ARM_VST3LNdAsm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdAsm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdAsm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNqAsm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNqAsm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dAsm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dAsm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dAsm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3dWB_register_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qAsm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qAsm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qAsm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qWB_register_Asm_16, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qWB_register_Asm_32, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST3qWB_register_Asm_8, ARM_INS_VST3: vst3 */ - { 0 } - }, - - { /* ARM_VST4LNdAsm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdAsm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdAsm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNqAsm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNqAsm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dAsm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dAsm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dAsm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4dWB_register_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qAsm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qAsm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qAsm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qWB_register_Asm_16, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qWB_register_Asm_32, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_VST4qWB_register_Asm_8, ARM_INS_VST4: vst4 */ - { 0 } - }, - - { /* ARM_t2LDRBpcrel, ARM_INS_LDRB: ldrb */ - { 0 } - }, - - { /* ARM_t2LDRConstPool, ARM_INS_LDR: ldr */ - { 0 } - }, - - { /* ARM_t2LDRHpcrel, ARM_INS_LDRH: ldrh */ - { 0 } - }, - - { /* ARM_t2LDRSBpcrel, ARM_INS_LDRSB: ldrsb */ - { 0 } - }, - - { /* ARM_t2LDRSHpcrel, ARM_INS_LDRSH: ldrsh */ - { 0 } - }, - - { /* ARM_t2LDRpcrel, ARM_INS_LDR: ldr */ - { 0 } - }, - - { /* ARM_t2MOVSsi, ARM_INS_MOVS: movs */ - { 0 } - }, - - { /* ARM_t2MOVSsr, ARM_INS_MOVS: movs */ - { 0 } - }, - - { /* ARM_t2MOVsi, ARM_INS_MOV: mov */ - { 0 } - }, - - { /* ARM_t2MOVsr, ARM_INS_MOV: mov */ - { 0 } - }, - - { /* ARM_tLDRConstPool, ARM_INS_LDR: ldr */ - { 0 } - }, - - { /* ARM_ADCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ADCrr, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ADCrsi, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ADCrsr, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ADDri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ADDrr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ADDrsi, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ADDrsr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ADR, ARM_INS_ADR: adr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_AESD, ARM_INS_AESD: aesd */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_AESE, ARM_INS_AESE: aese */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_AESIMC, ARM_INS_AESIMC: aesimc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_AESMC, ARM_INS_AESMC: aesmc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ANDri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ANDrr, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ANDrsi, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ANDrsr, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_BFC, ARM_INS_BFC: bfc */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_BFI, ARM_INS_BFI: bfi */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_BICri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_BICrr, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_BICrsi, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_BICrsr, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_BKPT, ARM_INS_BKPT: bkpt */ - { 0 } - }, - - { /* ARM_BL, ARM_INS_BL: bl */ - { 0 } - }, - - { /* ARM_BLX, ARM_INS_BLX: blx */ - { CS_AC_READ, 0 } - }, - - { /* ARM_BLX_pred, ARM_INS_BLX: blx */ - { CS_AC_READ, 0 } - }, - - { /* ARM_BLXi, ARM_INS_BLX: blx */ - { 0 } - }, - - { /* ARM_BL_pred, ARM_INS_BL: bl */ - { 0 } - }, - - { /* ARM_BX, ARM_INS_BX: bx */ - { CS_AC_READ, 0 } - }, - - { /* ARM_BXJ, ARM_INS_BXJ: bxj */ - { CS_AC_READ, 0 } - }, - - { /* ARM_BX_RET, ARM_INS_BX: bx */ - { 0 } - }, - - { /* ARM_BX_pred, ARM_INS_BX: bx */ - { CS_AC_READ, 0 } - }, - - { /* ARM_Bcc, ARM_INS_B: b */ - { 0 } - }, - - { /* ARM_CDP, ARM_INS_CDP: cdp */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_CDP2, ARM_INS_CDP2: cdp2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_CLREX, ARM_INS_CLREX: clrex */ - { 0 } - }, - - { /* ARM_CLZ, ARM_INS_CLZ: clz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_CMNri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } - }, - - { /* ARM_CMNzrr, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CMNzrsi, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } - }, - - { /* ARM_CMNzrsr, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CMPri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } - }, - - { /* ARM_CMPrr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CMPrsi, ARM_INS_CMP: cmp */ - { CS_AC_READ, 0 } - }, - - { /* ARM_CMPrsr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CPS1p, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_CPS2p, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_CPS3p, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_CRC32B, ARM_INS_CRC32B: crc32b */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CRC32H, ARM_INS_CRC32H: crc32h */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_CRC32W, ARM_INS_CRC32W: crc32w */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_DBG, ARM_INS_DBG: dbg */ - { 0 } - }, - - { /* ARM_DMB, ARM_INS_DMB: dmb */ - { 0 } - }, - - { /* ARM_DSB, ARM_INS_DFB: dfb */ - { 0 } - }, - - { /* ARM_EORri, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_EORrr, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_EORrsi, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_EORrsr, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ERET, ARM_INS_ERET: eret */ - { 0 } - }, - - { /* ARM_FCONSTD, ARM_INS_FCONSTD: fconstd */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_FCONSTH, ARM_INS_VMOV: vmov */ - { 0 } - }, - - { /* ARM_FCONSTS, ARM_INS_FCONSTS: fconsts */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax */ - { CS_AC_READ, 0 } - }, - - { /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_FMSTAT, ARM_INS_FMSTAT: fmstat */ - { 0 } - }, - - { /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax */ - { CS_AC_READ, 0 } - }, - - { /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_HINT, ARM_INS_CSDB: csdb */ - { 0 } - }, - - { /* ARM_HLT, ARM_INS_HLT: hlt */ - { 0 } - }, - - { /* ARM_HVC, ARM_INS_HVC: hvc */ - { 0 } - }, - - { /* ARM_ISB, ARM_INS_ISB: isb */ - { 0 } - }, - - { /* ARM_LDA, ARM_INS_LDA: lda */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDAB, ARM_INS_LDAB: ldab */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDAEX, ARM_INS_LDAEX: ldaex */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDAH, ARM_INS_LDAH: ldah */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC_OPTION, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC_POST, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDC_PRE, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDMDA, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMIA, ARM_INS_LDM: ldm */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMIB, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRBi12, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRBrs, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRD, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_LDREX, ARM_INS_LDREX: ldrex */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRH, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRi12, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_LDRrs, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_MCR, ARM_INS_MCR: mcr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_MCR2, ARM_INS_MCR2: mcr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_MCRR, ARM_INS_MCRR: mcrr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MLA, ARM_INS_MLA: mla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MLS, ARM_INS_MLS: mls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MOVPCLR, ARM_INS_MOV: mov */ - { 0 } - }, - - { /* ARM_MOVTi16, ARM_INS_MOVT: movt */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_MOVi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MOVi16, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MOVr, ARM_INS_MOV: mov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_MOVr_TC, ARM_INS_MOV: mov */ - { 0 } - }, - - { /* ARM_MOVsi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MOVsr, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MRC, ARM_INS_MRC: mrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_MRC2, ARM_INS_MRC2: mrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_MRRC, ARM_INS_MRRC: mrrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MRS, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MRSbanked, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MRSsys, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MSR, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_MSRbanked, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_MSRi, ARM_INS_MSR: msr */ - { 0 } - }, - - { /* ARM_MUL, ARM_INS_MUL: mul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_MVNi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MVNr, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_MVNsi, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_MVNsr, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ORRri, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ORRrr, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_ORRrsi, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_ORRrsr, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_PLDWi12, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } - }, - - { /* ARM_PLDWrs, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } - }, - - { /* ARM_PLDi12, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } - }, - - { /* ARM_PLDrs, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } - }, - - { /* ARM_PLIi12, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } - }, - - { /* ARM_PLIrs, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } - }, - - { /* ARM_QADD, ARM_INS_QADD: qadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QADD16, ARM_INS_QADD16: qadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QADD8, ARM_INS_QADD8: qadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QASX, ARM_INS_QASX: qasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QDADD, ARM_INS_QDADD: qdadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QSAX, ARM_INS_QSAX: qsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QSUB, ARM_INS_QSUB: qsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QSUB16, ARM_INS_QSUB16: qsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_RBIT, ARM_INS_RBIT: rbit */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_REV, ARM_INS_REV: rev */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_REV16, ARM_INS_REV16: rev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_REVSH, ARM_INS_REVSH: revsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_RFEDA, ARM_INS_RFEDA: rfeda */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEDB, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEIA, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEIB, ARM_INS_RFEIB: rfeib */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib */ - { CS_AC_READ, 0 } - }, - - { /* ARM_RSBri, ARM_INS_NEG: neg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_RSBrr, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_RSBrsi, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_RSBrsr, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_RSCri, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_RSCrr, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_RSCrsi, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_RSCrsr, ARM_INS_RSC: rsc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SADD16, ARM_INS_SADD16: sadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SADD8, ARM_INS_SADD8: sadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SASX, ARM_INS_SASX: sasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SBCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SBCrr, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SBCrsi, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SBCrsr, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SBFX, ARM_INS_SBFX: sbfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SDIV, ARM_INS_SDIV: sdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SEL, ARM_INS_SEL: sel */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SETEND, ARM_INS_SETEND: setend */ - { 0 } - }, - - { /* ARM_SETPAN, ARM_INS_SETPAN: setpan */ - { 0 } - }, - - { /* ARM_SHA1C, ARM_INS_SHA1C: sha1c */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHA1H, ARM_INS_SHA1H: sha1h */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SHA1M, ARM_INS_SHA1M: sha1m */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHA1P, ARM_INS_SHA1P: sha1p */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SHA256H, ARM_INS_SHA256H: sha256h */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHADD16, ARM_INS_SHADD16: shadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHASX, ARM_INS_SHASX: shasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHSAX, ARM_INS_SHSAX: shsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMC, ARM_INS_SMC: smc */ - { 0 } - }, - - { /* ARM_SMLABB, ARM_INS_SMLABB: smlabb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLABT, ARM_INS_SMLABT: smlabt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLAD, ARM_INS_SMLAD: smlad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLADX, ARM_INS_SMLADX: smladx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLAL, ARM_INS_SMLAL: smlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLALD, ARM_INS_SMLALD: smlald */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLATB, ARM_INS_SMLATB: smlatb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLATT, ARM_INS_SMLATT: smlatt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLSD, ARM_INS_SMLSD: smlsd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMMLA, ARM_INS_SMMLA: smmla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMMLS, ARM_INS_SMMLS: smmls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMMUL, ARM_INS_SMMUL: smmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMMULR, ARM_INS_SMMULR: smmulr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMUAD, ARM_INS_SMUAD: smuad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMUADX, ARM_INS_SMUADX: smuadx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULBB, ARM_INS_SMULBB: smulbb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULBT, ARM_INS_SMULBT: smulbt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULL, ARM_INS_SMULL: smull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULTB, ARM_INS_SMULTB: smultb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULTT, ARM_INS_SMULTT: smultt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULWB, ARM_INS_SMULWB: smulwb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMULWT, ARM_INS_SMULWT: smulwt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMUSD, ARM_INS_SMUSD: smusd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SRSDA, ARM_INS_SRSDA: srsda */ - { 0 } - }, - - { /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda */ - { 0 } - }, - - { /* ARM_SRSDB, ARM_INS_SRSDB: srsdb */ - { 0 } - }, - - { /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb */ - { 0 } - }, - - { /* ARM_SRSIA, ARM_INS_SRSIA: srsia */ - { 0 } - }, - - { /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia */ - { 0 } - }, - - { /* ARM_SRSIB, ARM_INS_SRSIB: srsib */ - { 0 } - }, - - { /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib */ - { 0 } - }, - - { /* ARM_SSAT, ARM_INS_SSAT: ssat */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_SSAT16, ARM_INS_SSAT16: ssat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_SSAX, ARM_INS_SSAX: ssax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SSUB16, ARM_INS_SSUB16: ssub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2_POST, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC2_PRE, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STCL_POST, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STCL_PRE, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC_OFFSET, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC_OPTION, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC_POST, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STC_PRE, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STL, ARM_INS_STL: stl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STLB, ARM_INS_STLB: stlb */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STLEX, ARM_INS_STLEX: stlex */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STLEXD, ARM_INS_STLEXD: stlexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STLH, ARM_INS_STLH: stlh */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STMDA, ARM_INS_STMDA: stmda */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_STMDB, ARM_INS_STMDB: stmdb */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STMDB_UPD, ARM_INS_PUSH: push */ - { CS_AC_READ, 0 } - }, - - { /* ARM_STMIA, ARM_INS_STM: stm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_STMIB, ARM_INS_STMIB: stmib */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRB_POST_REG, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRBi12, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRBrs, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRD, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRD_POST, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRD_PRE, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STREX, ARM_INS_STREX: strex */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STREXB, ARM_INS_STREXB: strexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STREXD, ARM_INS_STREXD: strexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STREXH, ARM_INS_STREXH: strexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRH, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRHTi, ARM_INS_STRHT: strht */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRHTr, ARM_INS_STRHT: strht */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRH_POST, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_STRH_PRE, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRT_POST_REG, ARM_INS_STRT: strt */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STR_POST_IMM, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STR_POST_REG, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STR_PRE_IMM, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STR_PRE_REG, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRi12, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_STRrs, ARM_INS_STR: str */ - { CS_AC_READ, 0 } - }, - - { /* ARM_SUBri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SUBrr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SUBrsi, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SUBrsr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SVC, ARM_INS_SVC: svc */ - { 0 } - }, - - { /* ARM_SWP, ARM_INS_SWP: swp */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SWPB, ARM_INS_SWPB: swpb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_SXTAB, ARM_INS_SXTAB: sxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SXTAH, ARM_INS_SXTAH: sxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SXTB, ARM_INS_SXTB: sxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_SXTH, ARM_INS_SXTH: sxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_TEQri, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } - }, - - { /* ARM_TEQrr, ARM_INS_TEQ: teq */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_TEQrsi, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } - }, - - { /* ARM_TEQrsr, ARM_INS_TEQ: teq */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_TRAP, ARM_INS_TRAP: trap */ - { 0 } - }, - - { /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ - { 0 } - }, - - { /* ARM_TSB, ARM_INS_TSB: tsb */ - { 0 } - }, - - { /* ARM_TSTri, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } - }, - - { /* ARM_TSTrr, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_TSTrsi, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } - }, - - { /* ARM_TSTrsr, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UADD16, ARM_INS_UADD16: uadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UADD8, ARM_INS_UADD8: uadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UASX, ARM_INS_UASX: uasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UBFX, ARM_INS_UBFX: ubfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_UDF, ARM_INS_UDF: udf */ - { 0 } - }, - - { /* ARM_UDIV, ARM_INS_UDIV: udiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UHASX, ARM_INS_UHASX: uhasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UHSAX, ARM_INS_UHSAX: uhsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UMAAL, ARM_INS_UMAAL: umaal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UMLAL, ARM_INS_UMLAL: umlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UMULL, ARM_INS_UMULL: umull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UQASX, ARM_INS_UQASX: uqasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UQSAX, ARM_INS_UQSAX: uqsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_USAD8, ARM_INS_USAD8: usad8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_USADA8, ARM_INS_USADA8: usada8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_USAT, ARM_INS_USAT: usat */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_USAT16, ARM_INS_USAT16: usat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_USAX, ARM_INS_USAX: usax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_USUB16, ARM_INS_USUB16: usub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_USUB8, ARM_INS_USUB8: usub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_UXTAB, ARM_INS_UXTAB: uxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_UXTAH, ARM_INS_UXTAH: uxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_UXTB, ARM_INS_UXTB: uxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_UXTH, ARM_INS_UXTH: uxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAsv16i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAsv2i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAsv4i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAsv4i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAsv8i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAsv8i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAuv16i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAuv2i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAuv4i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAuv4i32, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAuv8i16, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABAuv8i8, ARM_INS_VABA: vaba */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDfd, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDfq, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDhd, ARM_INS_VABD: vabd */ - { 0 } - }, - - { /* ARM_VABDhq, ARM_INS_VABD: vabd */ - { 0 } - }, - - { /* ARM_VABDsv16i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDsv2i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDsv4i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDsv4i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDsv8i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDsv8i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDuv16i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDuv2i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDuv4i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDuv4i32, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDuv8i16, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABDuv8i8, ARM_INS_VABD: vabd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VABSD, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSH, ARM_INS_VABS: vabs */ - { 0 } - }, - - { /* ARM_VABSS, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSfd, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSfq, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABShd, ARM_INS_VABS: vabs */ - { 0 } - }, - - { /* ARM_VABShq, ARM_INS_VABS: vabs */ - { 0 } - }, - - { /* ARM_VABSv16i8, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSv2i32, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSv4i16, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSv4i32, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSv8i16, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VABSv8i8, ARM_INS_VABS: vabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VACGEfd, ARM_INS_VACGE: vacge */ - { 0 } - }, - - { /* ARM_VACGEfq, ARM_INS_VACGE: vacge */ - { 0 } - }, - - { /* ARM_VACGEhd, ARM_INS_VACGE: vacge */ - { 0 } - }, - - { /* ARM_VACGEhq, ARM_INS_VACGE: vacge */ - { 0 } - }, - - { /* ARM_VACGTfd, ARM_INS_VACGT: vacgt */ - { 0 } - }, - - { /* ARM_VACGTfq, ARM_INS_VACGT: vacgt */ - { 0 } - }, - - { /* ARM_VACGThd, ARM_INS_VACGT: vacgt */ - { 0 } - }, - - { /* ARM_VACGThq, ARM_INS_VACGT: vacgt */ - { 0 } - }, - - { /* ARM_VADDD, ARM_INS_FADDD: faddd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDH, ARM_INS_VADD: vadd */ - { 0 } - }, - - { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDS, ARM_INS_FADDS: fadds */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDfd, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDfq, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDhd, ARM_INS_VADD: vadd */ - { 0 } - }, - - { /* ARM_VADDhq, ARM_INS_VADD: vadd */ - { 0 } - }, - - { /* ARM_VADDv16i8, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv1i64, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv2i32, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv2i64, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv4i16, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv4i32, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv8i16, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VADDv8i8, ARM_INS_VADD: vadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VANDd, ARM_INS_VAND: vand */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VANDq, ARM_INS_VAND: vand */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBICd, ARM_INS_VBIC: vbic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBICiv2i32, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VBICiv4i16, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VBICiv4i32, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VBICiv8i16, ARM_INS_VAND: vand */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VBICq, ARM_INS_VBIC: vbic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBIFd, ARM_INS_VBIF: vbif */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBIFq, ARM_INS_VBIF: vbif */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBITd, ARM_INS_VBIT: vbit */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBITq, ARM_INS_VBIT: vbit */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBSLd, ARM_INS_VBSL: vbsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VBSLq, ARM_INS_VBSL: vbsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCADDv2f32, ARM_INS_VCADD: vcadd */ - { 0 } - }, - - { /* ARM_VCADDv4f16, ARM_INS_VCADD: vcadd */ - { 0 } - }, - - { /* ARM_VCADDv4f32, ARM_INS_VCADD: vcadd */ - { 0 } - }, - - { /* ARM_VCADDv8f16, ARM_INS_VCADD: vcadd */ - { 0 } - }, - - { /* ARM_VCEQfd, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQfq, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQhd, ARM_INS_VCEQ: vceq */ - { 0 } - }, - - { /* ARM_VCEQhq, ARM_INS_VCEQ: vceq */ - { 0 } - }, - - { /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv4f16, ARM_INS_VCEQ: vceq */ - { 0 } - }, - - { /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv8f16, ARM_INS_VCEQ: vceq */ - { 0 } - }, - - { /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEfd, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEfq, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEhd, ARM_INS_VCGE: vcge */ - { 0 } - }, - - { /* ARM_VCGEhq, ARM_INS_VCGE: vcge */ - { 0 } - }, - - { /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv4f16, ARM_INS_VCGE: vcge */ - { 0 } - }, - - { /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv8f16, ARM_INS_VCGE: vcge */ - { 0 } - }, - - { /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTfd, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTfq, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGThd, ARM_INS_VCGT: vcgt */ - { 0 } - }, - - { /* ARM_VCGThq, ARM_INS_VCGT: vcgt */ - { 0 } - }, - - { /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv4f16, ARM_INS_VCGT: vcgt */ - { 0 } - }, - - { /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv8f16, ARM_INS_VCGT: vcgt */ - { 0 } - }, - - { /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv4f16, ARM_INS_VCLE: vcle */ - { 0 } - }, - - { /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv8f16, ARM_INS_VCLE: vcle */ - { 0 } - }, - - { /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv4f16, ARM_INS_VCLT: vclt */ - { 0 } - }, - - { /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv8f16, ARM_INS_VCLT: vclt */ - { 0 } - }, - - { /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCMLAv2f32, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv4f16, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv4f32, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv8f16, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA: vcmla */ - { 0 } - }, - - { /* ARM_VCMPD, ARM_INS_VCMP: vcmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCMPEH, ARM_INS_VCMPE: vcmpe */ - { 0 } - }, - - { /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VCMPEZH, ARM_INS_VCMPE: vcmpe */ - { 0 } - }, - - { /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VCMPH, ARM_INS_VCMP: vcmp */ - { 0 } - }, - - { /* ARM_VCMPS, ARM_INS_VCMP: vcmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VCMPZD, ARM_INS_FCMPZD: fcmpzd */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VCMPZH, ARM_INS_VCMP: vcmp */ - { 0 } - }, - - { /* ARM_VCMPZS, ARM_INS_FCMPZS: fcmpzs */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VCNTd, ARM_INS_VCNT: vcnt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCNTq, ARM_INS_VCNT: vcnt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTANSDf, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANSDh, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANSQf, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANSQh, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANUDf, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANUDh, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANUQf, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTANUQh, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTASH, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTAUH, ARM_INS_VCVTA: vcvta */ - { 0 } - }, - - { /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTDS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTMNSDf, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNSDh, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNSQf, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNSQh, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNUDf, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNUDh, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNUQf, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMNUQh, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTMSH, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTMUH, ARM_INS_VCVTM: vcvtm */ - { 0 } - }, - - { /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTNNSDf, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNSDh, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNSQf, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNSQh, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNUDf, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNUDh, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNUQf, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNNUQh, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTNSH, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTNUH, ARM_INS_VCVTN: vcvtn */ - { 0 } - }, - - { /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTPNSDf, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNSDh, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNSQf, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNSQh, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNUDf, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNUDh, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNUQf, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPNUQh, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTPSH, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTPUH, ARM_INS_VCVTP: vcvtp */ - { 0 } - }, - - { /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTSD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTh2sd, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2sq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2ud, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2uq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2xsd, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2xsq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2xud, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTh2xuq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTs2hd, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTs2hq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTu2hd, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTu2hq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTxs2hd, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTxs2hq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VCVTxu2hd, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VCVTxu2hq, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VDIVD, ARM_INS_VDIV: vdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VDIVH, ARM_INS_VDIV: vdiv */ - { 0 } - }, - - { /* ARM_VDIVS, ARM_INS_VDIV: vdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VDUP16d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUP16q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUP32d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUP32q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUP8d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUP8q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VEORd, ARM_INS_VEOR: veor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEORq, ARM_INS_VEOR: veor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTd16, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTd32, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTd8, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTq16, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTq32, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTq64, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VEXTq8, ARM_INS_VEXT: vext */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMAD, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMAH, ARM_INS_VFMA: vfma */ - { 0 } - }, - - { /* ARM_VFMAS, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMAfd, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMAfq, ARM_INS_VFMA: vfma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMAhd, ARM_INS_VFMA: vfma */ - { 0 } - }, - - { /* ARM_VFMAhq, ARM_INS_VFMA: vfma */ - { 0 } - }, - - { /* ARM_VFMSD, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMSH, ARM_INS_VFMS: vfms */ - { 0 } - }, - - { /* ARM_VFMSS, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMSfd, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMSfq, ARM_INS_VFMS: vfms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFMShd, ARM_INS_VFMS: vfms */ - { 0 } - }, - - { /* ARM_VFMShq, ARM_INS_VFMS: vfms */ - { 0 } - }, - - { /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFNMAH, ARM_INS_VFNMA: vfnma */ - { 0 } - }, - - { /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VFNMSH, ARM_INS_VFNMS: vfnms */ - { 0 } - }, - - { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VGETLNi32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VGETLNs16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VGETLNs8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VGETLNu16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VGETLNu8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VINSH, ARM_INS_VINS: vins */ - { 0 } - }, - - { /* ARM_VJCVT, ARM_INS_VJCVT: vjcvt */ - { 0 } - }, - - { /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1 */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1 */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD1d16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8T, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q16, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q32, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q64, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q8, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD2b16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q16, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q32, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q8, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3d16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3d32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3d8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3q16, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3q32, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD3q8, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4d16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4d32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4d8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4q16, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4q32, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLD4q8, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VLDRD, ARM_INS_VLDR: vldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VLDRH, ARM_INS_VLDR: vldr */ - { 0 } - }, - - { /* ARM_VLDRS, ARM_INS_VLDR: vldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VLLDM, ARM_INS_VLLDM: vlldm */ - { 0 } - }, - - { /* ARM_VLSTM, ARM_INS_VLSTM: vlstm */ - { 0 } - }, - - { /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXNMH, ARM_INS_VMAXNM: vmaxnm */ - { 0 } - }, - - { /* ARM_VMAXNMNDf, ARM_INS_VMAXNM: vmaxnm */ - { 0 } - }, - - { /* ARM_VMAXNMNDh, ARM_INS_VMAXNM: vmaxnm */ - { 0 } - }, - - { /* ARM_VMAXNMNQf, ARM_INS_VMAXNM: vmaxnm */ - { 0 } - }, - - { /* ARM_VMAXNMNQh, ARM_INS_VMAXNM: vmaxnm */ - { 0 } - }, - - { /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXfd, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXfq, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXhd, ARM_INS_VMAX: vmax */ - { 0 } - }, - - { /* ARM_VMAXhq, ARM_INS_VMAX: vmax */ - { 0 } - }, - - { /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINNMH, ARM_INS_VMINNM: vminnm */ - { 0 } - }, - - { /* ARM_VMINNMNDf, ARM_INS_VMINNM: vminnm */ - { 0 } - }, - - { /* ARM_VMINNMNDh, ARM_INS_VMINNM: vminnm */ - { 0 } - }, - - { /* ARM_VMINNMNQf, ARM_INS_VMINNM: vminnm */ - { 0 } - }, - - { /* ARM_VMINNMNQh, ARM_INS_VMINNM: vminnm */ - { 0 } - }, - - { /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINfd, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINfq, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINhd, ARM_INS_VMIN: vmin */ - { 0 } - }, - - { /* ARM_VMINhq, ARM_INS_VMIN: vmin */ - { 0 } - }, - - { /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAD, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAH, ARM_INS_VMLA: vmla */ - { 0 } - }, - - { /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAS, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAfd, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAfq, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAhd, ARM_INS_VMLA: vmla */ - { 0 } - }, - - { /* ARM_VMLAhq, ARM_INS_VMLA: vmla */ - { 0 } - }, - - { /* ARM_VMLAslfd, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAslfq, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAslhd, ARM_INS_VMLA: vmla */ - { 0 } - }, - - { /* ARM_VMLAslhq, ARM_INS_VMLA: vmla */ - { 0 } - }, - - { /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSD, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSH, ARM_INS_VMLS: vmls */ - { 0 } - }, - - { /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSS, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSfd, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSfq, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLShd, ARM_INS_VMLS: vmls */ - { 0 } - }, - - { /* ARM_VMLShq, ARM_INS_VMLS: vmls */ - { 0 } - }, - - { /* ARM_VMLSslfd, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSslfq, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSslhd, ARM_INS_VMLS: vmls */ - { 0 } - }, - - { /* ARM_VMLSslhq, ARM_INS_VMLS: vmls */ - { 0 } - }, - - { /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVD, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVDRR, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVH, ARM_INS_VMOVX: vmovx */ - { 0 } - }, - - { /* ARM_VMOVHR, ARM_INS_VMOV: vmov */ - { 0 } - }, - - { /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVRH, ARM_INS_VMOV: vmov */ - { 0 } - }, - - { /* ARM_VMOVRRD, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVRRS, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVRS, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVS, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVSR, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVSRR, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMSR, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr */ - { CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULD, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULH, ARM_INS_VMUL: vmul */ - { 0 } - }, - - { /* ARM_VMULLp64, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLp8, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULS, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULfd, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULfq, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULhd, ARM_INS_VMUL: vmul */ - { 0 } - }, - - { /* ARM_VMULhq, ARM_INS_VMUL: vmul */ - { 0 } - }, - - { /* ARM_VMULpd, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULpq, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULslfd, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULslfq, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULslhd, ARM_INS_VMUL: vmul */ - { 0 } - }, - - { /* ARM_VMULslhq, ARM_INS_VMUL: vmul */ - { 0 } - }, - - { /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMULv16i8, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULv2i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULv4i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULv4i32, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULv8i16, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMULv8i8, ARM_INS_VMUL: vmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VMVNd, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMVNq, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VMVNv2i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMVNv4i32, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_VNEGD, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGH, ARM_INS_VNEG: vneg */ - { 0 } - }, - - { /* ARM_VNEGS, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGf32q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGfd, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGhd, ARM_INS_VNEG: vneg */ - { 0 } - }, - - { /* ARM_VNEGhq, ARM_INS_VNEG: vneg */ - { 0 } - }, - - { /* ARM_VNEGs16d, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGs16q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGs32d, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGs32q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGs8d, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNEGs8q, ARM_INS_VNEG: vneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VNMLAH, ARM_INS_VNMLA: vnmla */ - { 0 } - }, - - { /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VNMLSH, ARM_INS_VNMLS: vnmls */ - { 0 } - }, - - { /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VNMULD, ARM_INS_VNMUL: vnmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VNMULH, ARM_INS_VNMUL: vnmul */ - { 0 } - }, - - { /* ARM_VNMULS, ARM_INS_VNMUL: vnmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VORNd, ARM_INS_VORN: vorn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VORNq, ARM_INS_VORN: vorn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VORRd, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VORRiv2i32, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VORRiv4i16, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VORRiv4i32, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VORRiv8i16, ARM_INS_VORR: vorr */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VORRq, ARM_INS_VMOV: vmov */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDf, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDh, ARM_INS_VPADD: vpadd */ - { 0 } - }, - - { /* ARM_VPADDi16, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDi32, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPADDi8, ARM_INS_VPADD: vpadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXh, ARM_INS_VPMAX: vpmax */ - { 0 } - }, - - { /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINf, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINh, ARM_INS_VPMIN: vpmin */ - { 0 } - }, - - { /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ - { 0 } - }, - - { /* ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ - { 0 } - }, - - { /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPEhd, ARM_INS_VRECPE: vrecpe */ - { 0 } - }, - - { /* ARM_VRECPEhq, ARM_INS_VRECPE: vrecpe */ - { 0 } - }, - - { /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRECPShd, ARM_INS_VRECPS: vrecps */ - { 0 } - }, - - { /* ARM_VRECPShq, ARM_INS_VRECPS: vrecps */ - { 0 } - }, - - { /* ARM_VREV16d8, ARM_INS_VREV16: vrev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV16q8, ARM_INS_VREV16: vrev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV32d16, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV32d8, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV32q16, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV32q8, ARM_INS_VREV32: vrev32 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV64d16, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV64d32, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV64d8, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV64q16, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV64q32, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VREV64q8, ARM_INS_VREV64: vrev64 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTAH, ARM_INS_VRINTA: vrinta */ - { 0 } - }, - - { /* ARM_VRINTANDf, ARM_INS_VRINTA: vrinta */ - { 0 } - }, - - { /* ARM_VRINTANDh, ARM_INS_VRINTA: vrinta */ - { 0 } - }, - - { /* ARM_VRINTANQf, ARM_INS_VRINTA: vrinta */ - { 0 } - }, - - { /* ARM_VRINTANQh, ARM_INS_VRINTA: vrinta */ - { 0 } - }, - - { /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTMH, ARM_INS_VRINTM: vrintm */ - { 0 } - }, - - { /* ARM_VRINTMNDf, ARM_INS_VRINTM: vrintm */ - { 0 } - }, - - { /* ARM_VRINTMNDh, ARM_INS_VRINTM: vrintm */ - { 0 } - }, - - { /* ARM_VRINTMNQf, ARM_INS_VRINTM: vrintm */ - { 0 } - }, - - { /* ARM_VRINTMNQh, ARM_INS_VRINTM: vrintm */ - { 0 } - }, - - { /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTND, ARM_INS_VRINTN: vrintn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTNH, ARM_INS_VRINTN: vrintn */ - { 0 } - }, - - { /* ARM_VRINTNNDf, ARM_INS_VRINTN: vrintn */ - { 0 } - }, - - { /* ARM_VRINTNNDh, ARM_INS_VRINTN: vrintn */ - { 0 } - }, - - { /* ARM_VRINTNNQf, ARM_INS_VRINTN: vrintn */ - { 0 } - }, - - { /* ARM_VRINTNNQh, ARM_INS_VRINTN: vrintn */ - { 0 } - }, - - { /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTPH, ARM_INS_VRINTP: vrintp */ - { 0 } - }, - - { /* ARM_VRINTPNDf, ARM_INS_VRINTP: vrintp */ - { 0 } - }, - - { /* ARM_VRINTPNDh, ARM_INS_VRINTP: vrintp */ - { 0 } - }, - - { /* ARM_VRINTPNQf, ARM_INS_VRINTP: vrintp */ - { 0 } - }, - - { /* ARM_VRINTPNQh, ARM_INS_VRINTP: vrintp */ - { 0 } - }, - - { /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTRH, ARM_INS_VRINTR: vrintr */ - { 0 } - }, - - { /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTXH, ARM_INS_VRINTX: vrintx */ - { 0 } - }, - - { /* ARM_VRINTXNDf, ARM_INS_VRINTX: vrintx */ - { 0 } - }, - - { /* ARM_VRINTXNDh, ARM_INS_VRINTX: vrintx */ - { 0 } - }, - - { /* ARM_VRINTXNQf, ARM_INS_VRINTX: vrintx */ - { 0 } - }, - - { /* ARM_VRINTXNQh, ARM_INS_VRINTX: vrintx */ - { 0 } - }, - - { /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRINTZH, ARM_INS_VRINTZ: vrintz */ - { 0 } - }, - - { /* ARM_VRINTZNDf, ARM_INS_VRINTZ: vrintz */ - { 0 } - }, - - { /* ARM_VRINTZNDh, ARM_INS_VRINTZ: vrintz */ - { 0 } - }, - - { /* ARM_VRINTZNQf, ARM_INS_VRINTZ: vrintz */ - { 0 } - }, - - { /* ARM_VRINTZNQh, ARM_INS_VRINTZ: vrintz */ - { 0 } - }, - - { /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTEhd, ARM_INS_VRSQRTE: vrsqrte */ - { 0 } - }, - - { /* ARM_VRSQRTEhq, ARM_INS_VRSQRTE: vrsqrte */ - { 0 } - }, - - { /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSQRTShd, ARM_INS_VRSQRTS: vrsqrts */ - { 0 } - }, - - { /* ARM_VRSQRTShq, ARM_INS_VRSQRTS: vrsqrts */ - { 0 } - }, - - { /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSDOTD, ARM_INS_VSDOT: vsdot */ - { 0 } - }, - - { /* ARM_VSDOTDI, ARM_INS_VSDOT: vsdot */ - { 0 } - }, - - { /* ARM_VSDOTQ, ARM_INS_VSDOT: vsdot */ - { 0 } - }, - - { /* ARM_VSDOTQI, ARM_INS_VSDOT: vsdot */ - { 0 } - }, - - { /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELEQH, ARM_INS_VSELEQ: vseleq */ - { 0 } - }, - - { /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELGED, ARM_INS_VSELGE: vselge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELGEH, ARM_INS_VSELGE: vselge */ - { 0 } - }, - - { /* ARM_VSELGES, ARM_INS_VSELGE: vselge */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELGTH, ARM_INS_VSELGT: vselgt */ - { 0 } - }, - - { /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSELVSH, ARM_INS_VSELVS: vselvs */ - { 0 } - }, - - { /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSETLNi16, ARM_INS_VMOV: vmov */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSETLNi32, ARM_INS_FMDHR: fmdhr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSETLNi8, ARM_INS_VMOV: vmov */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSHTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSHTOH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VSHTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSITOD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSITOH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VSITOS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSLTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSLTOH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VSLTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSQRTH, ARM_INS_VSQRT: vsqrt */ - { 0 } - }, - - { /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VST1LNd16, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VST1LNd32, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VST1LNd8, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1 */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8Q, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8T, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q16, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q32, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q64, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q8, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b16, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b32, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b8, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d16, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d32, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d8, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q16, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q32, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q8, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3d16, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3d32, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3d8, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3q16, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3q32, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3q8, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4d16, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4d32, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4d8, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4q16, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4q32, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4q8, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSTMDDB_UPD, ARM_INS_VPUSH: vpush */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSTMSDB_UPD, ARM_INS_VPUSH: vpush */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VSTRD, ARM_INS_VSTR: vstr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VSTRH, ARM_INS_VSTR: vstr */ - { 0 } - }, - - { /* ARM_VSTRS, ARM_INS_VSTR: vstr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_VSUBD, ARM_INS_FSUBD: fsubd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBH, ARM_INS_VSUB: vsub */ - { 0 } - }, - - { /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBS, ARM_INS_FSUBS: fsubs */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBfd, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBfq, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBhd, ARM_INS_VSUB: vsub */ - { 0 } - }, - - { /* ARM_VSUBhq, ARM_INS_VSUB: vsub */ - { 0 } - }, - - { /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VSWPd, ARM_INS_VSWP: vswp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VSWPq, ARM_INS_VSWP: vswp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTBL1, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBL2, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBL3, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBL4, ARM_INS_VTBL: vtbl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBX1, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBX2, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBX3, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTBX4, ARM_INS_VTBX: vtbx */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTOSHD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOSHH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VTOSHS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOSIRH, ARM_INS_VCVTR: vcvtr */ - { 0 } - }, - - { /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOSIZH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOSLD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOSLH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VTOSLS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOUHD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOUHH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VTOUHS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOUIRH, ARM_INS_VCVTR: vcvtr */ - { 0 } - }, - - { /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOUIZH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VTOULD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTOULH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VTOULS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VTRNd16, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTRNd32, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTRNd8, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTRNq16, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTRNq32, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTRNq8, ARM_INS_VTRN: vtrn */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VTSTv16i8, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTSTv2i32, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTSTv4i16, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTSTv4i32, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTSTv8i16, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VTSTv8i8, ARM_INS_VTST: vtst */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_VUDOTD, ARM_INS_VUDOT: vudot */ - { 0 } - }, - - { /* ARM_VUDOTDI, ARM_INS_VUDOT: vudot */ - { 0 } - }, - - { /* ARM_VUDOTQ, ARM_INS_VUDOT: vudot */ - { 0 } - }, - - { /* ARM_VUDOTQI, ARM_INS_VUDOT: vudot */ - { 0 } - }, - - { /* ARM_VUHTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VUHTOH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VUHTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VUITOD, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VUITOH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VUITOS, ARM_INS_VCVT: vcvt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_VULTOD, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VULTOH, ARM_INS_VCVT: vcvt */ - { 0 } - }, - - { /* ARM_VULTOS, ARM_INS_VCVT: vcvt */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_VUZPd16, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VUZPd8, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VUZPq16, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VUZPq32, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VUZPq8, ARM_INS_VUZP: vuzp */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VZIPd16, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VZIPd8, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VZIPq16, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VZIPq32, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_VZIPq8, ARM_INS_VZIP: vzip */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMIA, ARM_INS_LDM: ldm */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_sysSTMDA, ARM_INS_STMDA: stmda */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMIA, ARM_INS_STM: stm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMIB, ARM_INS_STMIB: stmib */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADCrr, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADCrs, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADDri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADDri12, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADDrr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADDrs, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ADR, ARM_INS_ADD: add */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2ANDri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ANDrr, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2ANDrs, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ASRri, ARM_INS_ASR: asr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ASRrr, ARM_INS_ASR: asr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2B, ARM_INS_B: b */ - { 0 } - }, - - { /* ARM_t2BFC, ARM_INS_BFC: bfc */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_t2BFI, ARM_INS_BFI: bfi */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2BICri, ARM_INS_AND: and */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2BICrr, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2BICrs, ARM_INS_BIC: bic */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2BXJ, ARM_INS_BXJ: bxj */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2Bcc, ARM_INS_B: b */ - { 0 } - }, - - { /* ARM_t2CDP, ARM_INS_CDP: cdp */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_t2CLREX, ARM_INS_CLREX: clrex */ - { 0 } - }, - - { /* ARM_t2CLZ, ARM_INS_CLZ: clz */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2CMNri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2CMNzrr, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CMNzrs, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2CMPri, ARM_INS_CMN: cmn */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2CMPrr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CMPrs, ARM_INS_CMP: cmp */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2CPS1p, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_t2CPS2p, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_t2CPS3p, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2DBG, ARM_INS_DBG: dbg */ - { 0 } - }, - - { /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1 */ - { 0 } - }, - - { /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2 */ - { 0 } - }, - - { /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3 */ - { 0 } - }, - - { /* ARM_t2DMB, ARM_INS_DMB: dmb */ - { 0 } - }, - - { /* ARM_t2DSB, ARM_INS_DFB: dfb */ - { 0 } - }, - - { /* ARM_t2EORri, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2EORrr, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2EORrs, ARM_INS_EOR: eor */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2HINT, ARM_INS_CSDB: csdb */ - { 0 } - }, - - { /* ARM_t2HVC, ARM_INS_HVC: hvc */ - { 0 } - }, - - { /* ARM_t2ISB, ARM_INS_ISB: isb */ - { 0 } - }, - - { /* ARM_t2IT, ARM_INS_IT: it */ - { 0 } - }, - - { /* ARM_t2LDA, ARM_INS_LDA: lda */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDAB, ARM_INS_LDAB: ldab */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDAH, ARM_INS_LDAH: ldah */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC_POST, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDMIA, ARM_INS_LDM: ldm */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDREX, ARM_INS_LDREX: ldrex */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LDRT, ARM_INS_LDRT: ldrt */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDR_POST, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRi12, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRi8, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRpci, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2LDRs, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LSLri, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LSLrr, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2LSRri, ARM_INS_LSR: lsr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2LSRrr, ARM_INS_LSR: lsr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MCR, ARM_INS_MCR: mcr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_t2MCR2, ARM_INS_MCR2: mcr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_t2MCRR, ARM_INS_MCRR: mcrr */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MLA, ARM_INS_MLA: mla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MLS, ARM_INS_MLS: mls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MOVTi16, ARM_INS_MOVT: movt */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MOVi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MOVi16, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MOVr, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd $rm #1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd $rm #1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2MRC, ARM_INS_MRC: mrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_t2MRC2, ARM_INS_MRC2: mrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, - CS_AC_IGNORE, 0 } - }, - - { /* ARM_t2MRRC, ARM_INS_MRRC: mrrc */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MRS_AR, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MRS_M, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MRSbanked, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MSR_AR, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2MSR_M, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2MSRbanked, ARM_INS_MSR: msr */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2MUL, ARM_INS_MUL: mul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2MVNi, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2MVNr, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2MVNs, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2ORNri, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ORNrr, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2ORNrs, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ORRri, ARM_INS_ORN: orn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2ORRrr, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2ORRrs, ARM_INS_ORR: orr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDWs, ARM_INS_PLDW: pldw */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDi12, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDi8, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDpci, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLDs, ARM_INS_PLD: pld */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLIi12, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLIi8, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLIpci, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2PLIs, ARM_INS_PLI: pli */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2QADD, ARM_INS_QADD: qadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QADD16, ARM_INS_QADD16: qadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QADD8, ARM_INS_QADD8: qadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QASX, ARM_INS_QASX: qasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QDADD, ARM_INS_QDADD: qdadd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QSAX, ARM_INS_QSAX: qsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QSUB, ARM_INS_QSUB: qsub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2RBIT, ARM_INS_RBIT: rbit */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2REV, ARM_INS_REV: rev */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2REV16, ARM_INS_REV16: rev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2REVSH, ARM_INS_REVSH: revsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2RORri, ARM_INS_ROR: ror */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2RORrr, ARM_INS_ROR: ror */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2RRX, ARM_INS_RRX: rrx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2RSBri, ARM_INS_NEG: neg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2RSBrr, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2RSBrs, ARM_INS_RSB: rsb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SADD16, ARM_INS_SADD16: sadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SADD8, ARM_INS_SADD8: sadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SASX, ARM_INS_SASX: sasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SBCri, ARM_INS_ADC: adc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SBCrr, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SBCrs, ARM_INS_SBC: sbc */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SBFX, ARM_INS_SBFX: sbfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SDIV, ARM_INS_SDIV: sdiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SEL, ARM_INS_SEL: sel */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SETPAN, ARM_INS_SETPAN: setpan */ - { 0 } - }, - - { /* ARM_t2SG, ARM_INS_SG: sg */ - { 0 } - }, - - { /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SHASX, ARM_INS_SHASX: shasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMC, ARM_INS_SMC: smc */ - { 0 } - }, - - { /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULL, ARM_INS_SMULL: smull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb */ - { 0 } - }, - - { /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb */ - { 0 } - }, - - { /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia */ - { 0 } - }, - - { /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia */ - { 0 } - }, - - { /* ARM_t2SSAT, ARM_INS_SSAT: ssat */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SSAX, ARM_INS_SSAX: ssax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2_POST, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2 */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC_OFFSET, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC_OPTION, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC_POST, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STC_PRE, ARM_INS_STC: stc */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STL, ARM_INS_STL: stl */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STLB, ARM_INS_STLB: stlb */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STLEX, ARM_INS_STLEX: stlex */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STLH, ARM_INS_STLH: stlh */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STMDB, ARM_INS_STMDB: stmdb */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STMDB_UPD, ARM_INS_PUSH: push */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STMIA, ARM_INS_STM: stm */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2STRBT, ARM_INS_STRBT: strbt */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRB_POST, ARM_INS_STRB: strb */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2STRB_PRE, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRBi12, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRBi8, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRBs, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRD_POST, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STRD_PRE, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STRDi8, ARM_INS_STRD: strd */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STREX, ARM_INS_STREX: strex */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2STREXB, ARM_INS_STREXB: strexb */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STREXD, ARM_INS_STREXD: strexd */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STREXH, ARM_INS_STREXH: strexh */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2STRHT, ARM_INS_STRHT: strht */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRH_POST, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRH_PRE, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRHi12, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRHi8, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRHs, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRT, ARM_INS_STRT: strt */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STR_POST, ARM_INS_STR: str */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2STR_PRE, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRi12, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRi8, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2STRs, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_t2SUBS_PC_LR, ARM_INS_ERET: eret */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SUBri, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SUBri12, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SUBrr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2SUBrs, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SXTB, ARM_INS_SXTB: sxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2SXTH, ARM_INS_SXTH: sxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2TBB, ARM_INS_TBB: tbb */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2TBH, ARM_INS_TBH: tbh */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2TEQri, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2TEQrr, ARM_INS_TEQ: teq */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2TEQrs, ARM_INS_TEQ: teq */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2TSB, ARM_INS_TSB: tsb */ - { 0 } - }, - - { /* ARM_t2TSTri, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2TSTrr, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2TSTrs, ARM_INS_TST: tst */ - { CS_AC_READ, 0 } - }, - - { /* ARM_t2TT, ARM_INS_TT: tt */ - { 0 } - }, - - { /* ARM_t2TTA, ARM_INS_TTA: tta */ - { 0 } - }, - - { /* ARM_t2TTAT, ARM_INS_TTAT: ttat */ - { 0 } - }, - - { /* ARM_t2TTT, ARM_INS_TTT: ttt */ - { 0 } - }, - - { /* ARM_t2UADD16, ARM_INS_UADD16: uadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UADD8, ARM_INS_UADD8: uadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UASX, ARM_INS_UASX: uasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UBFX, ARM_INS_UBFX: ubfx */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2UDF, ARM_INS_UDF: udf */ - { 0 } - }, - - { /* ARM_t2UDIV, ARM_INS_UDIV: udiv */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UHASX, ARM_INS_UHASX: uhasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UMULL, ARM_INS_UMULL: umull */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UQASX, ARM_INS_UQASX: uqasx */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2USAD8, ARM_INS_USAD8: usad8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2USADA8, ARM_INS_USADA8: usada8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2USAT, ARM_INS_USAT: usat */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_t2USAT16, ARM_INS_USAT16: usat16 */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } - }, - - { /* ARM_t2USAX, ARM_INS_USAX: usax */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2USUB16, ARM_INS_USUB16: usub16 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2USUB8, ARM_INS_USUB8: usub8 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2UXTB, ARM_INS_UXTB: uxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_t2UXTH, ARM_INS_UXTH: uxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tADC, ARM_INS_ADC: adc */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tADDhirr, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tADDi3, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tADDi8, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_tADDrSP, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tADDrSPi, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tADDrr, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tADDspi, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_tADDspr, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tADR, ARM_INS_ADR: adr */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tAND, ARM_INS_AND: and */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tASRri, ARM_INS_ASR: asr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tASRrr, ARM_INS_ASR: asr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tB, ARM_INS_B: b */ - { 0 } - }, - - { /* ARM_tBIC, ARM_INS_BIC: bic */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tBKPT, ARM_INS_BKPT: bkpt */ - { 0 } - }, - - { /* ARM_tBL, ARM_INS_BL: bl */ - { 0 } - }, - - { /* ARM_tBLXNSr, ARM_INS_BLXNS: blxns */ - { 0 } - }, - - { /* ARM_tBLXi, ARM_INS_BLX: blx */ - { 0 } - }, - - { /* ARM_tBLXr, ARM_INS_BLX: blx */ - { CS_AC_READ, 0 } - }, - - { /* ARM_tBX, ARM_INS_BX: bx */ - { CS_AC_READ, 0 } - }, - - { /* ARM_tBXNS, ARM_INS_BXNS: bxns */ - { 0 } - }, - - { /* ARM_tBcc, ARM_INS_B: b */ - { 0 } - }, - - { /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz */ - { CS_AC_READ, 0 } - }, - - { /* ARM_tCBZ, ARM_INS_CBZ: cbz */ - { CS_AC_READ, 0 } - }, - - { /* ARM_tCMNz, ARM_INS_CMN: cmn */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tCMPhir, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tCMPi8, ARM_INS_CMP: cmp */ - { CS_AC_READ, 0 } - }, - - { /* ARM_tCMPr, ARM_INS_CMP: cmp */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tCPS, ARM_INS_CPS: cps */ - { 0 } - }, - - { /* ARM_tEOR, ARM_INS_EOR: eor */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tHINT, ARM_INS_HINT: hint */ - { 0 } - }, - - { /* ARM_tHLT, ARM_INS_HLT: hlt */ - { 0 } - }, - - { /* ARM_tLDMIA, ARM_INS_LDM: ldm */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRBi, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRBr, ARM_INS_LDRB: ldrb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRHi, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRHr, ARM_INS_LDRH: ldrh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tLDRi, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLDRpci, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLDRr, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLDRspi, ARM_INS_LDR: ldr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLSLri, ARM_INS_LSL: lsl */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLSLrr, ARM_INS_LSL: lsl */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLSRri, ARM_INS_LSR: lsr */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tLSRrr, ARM_INS_LSR: lsr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tMOVSr, ARM_INS_MOVS: movs */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tMOVi8, ARM_INS_MOV: mov */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tMOVr, ARM_INS_MOV: mov */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tMUL, ARM_INS_MUL: mul */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_tMVN, ARM_INS_MVN: mvn */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tORR, ARM_INS_ORR: orr */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tPOP, ARM_INS_POP: pop */ - { CS_AC_WRITE, 0 } - }, - - { /* ARM_tPUSH, ARM_INS_PUSH: push */ - { CS_AC_READ, 0 } - }, - - { /* ARM_tREV, ARM_INS_REV: rev */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tREV16, ARM_INS_REV16: rev16 */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tREVSH, ARM_INS_REVSH: revsh */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tROR, ARM_INS_ROR: ror */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tRSB, ARM_INS_NEG: neg */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tSBC, ARM_INS_SBC: sbc */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tSETEND, ARM_INS_SETEND: setend */ - { 0 } - }, - - { /* ARM_tSTMIA_UPD, ARM_INS_STM: stm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tSTRBi, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSTRBr, ARM_INS_STRB: strb */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSTRHi, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSTRHr, ARM_INS_STRH: strh */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSTRi, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSTRr, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSTRspi, ARM_INS_STR: str */ - { CS_AC_READ, CS_AC_WRITE, 0 } - }, - - { /* ARM_tSUBi3, ARM_INS_ADD: add */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tSUBi8, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_tSUBrr, ARM_INS_SUB: sub */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tSUBspi, ARM_INS_ADD: add */ - { CS_AC_READ | CS_AC_WRITE, 0 } - }, - - { /* ARM_tSVC, ARM_INS_SVC: svc */ - { 0 } - }, - - { /* ARM_tSXTB, ARM_INS_SXTB: sxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tSXTH, ARM_INS_SXTH: sxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tTRAP, ARM_INS_TRAP: trap */ - { 0 } - }, - - { /* ARM_tTST, ARM_INS_TST: tst */ - { CS_AC_READ, CS_AC_READ, 0 } - }, - - { /* ARM_tUDF, ARM_INS_UDF: udf */ - { 0 } - }, - - { /* ARM_tUXTB, ARM_INS_UXTB: uxtb */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, - - { /* ARM_tUXTH, ARM_INS_UXTH: uxth */ - { CS_AC_WRITE, CS_AC_READ, 0 } - }, diff --git a/include/capstone/arm.h b/include/capstone/arm.h index fd9b7fe98d..3bdcff31d5 100644 --- a/include/capstone/arm.h +++ b/include/capstone/arm.h @@ -1493,7 +1493,7 @@ typedef enum arm_insn { ARM_INS_VRSQRTS, ARM_INS_VRSRA, ARM_INS_VRSUBHN, - ARM_INS_VSCCLRM_, + ARM_INS_VSCCLRM, ARM_INS_VSDOT, ARM_INS_VSELEQ, ARM_INS_VSELGE, @@ -1524,7 +1524,6 @@ typedef enum arm_insn { ARM_INS_VUZP, ARM_INS_VZIP, ARM_INS_ADDW, - ARM_INS_ADR_, ARM_INS_AUT, ARM_INS_AUTG, ARM_INS_BFL, diff --git a/suite/auto-sync/inc_patches/ARM/01_LDM_reg_lists_write_attribute.patch b/suite/auto-sync/inc_patches/ARM/01_LDM_reg_lists_write_attribute.patch index 1c42104acf..25c50599e3 100644 --- a/suite/auto-sync/inc_patches/ARM/01_LDM_reg_lists_write_attribute.patch +++ b/suite/auto-sync/inc_patches/ARM/01_LDM_reg_lists_write_attribute.patch @@ -204,7 +204,7 @@ index cc10dad8..8a1ede35 100644 @@ -28522,21 +28522,21 @@ { 0 } }}, - { /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM_ - vscclrm{$p} $regs */ + { /* ARM_VSCCLRMD (3449) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */ { { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ @@ -213,7 +213,7 @@ index cc10dad8..8a1ede35 100644 { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /* */ { 0 } }}, - { /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM_ - vscclrm{$p} $regs */ + { /* ARM_VSCCLRMS (3450) - ARM_INS_VSCCLRM - vscclrm{$p} $regs */ { { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */ diff --git a/suite/auto-sync/src/autosync/IncGenerator.py b/suite/auto-sync/src/autosync/IncGenerator.py index a4cd316329..98943b2ab2 100644 --- a/suite/auto-sync/src/autosync/IncGenerator.py +++ b/suite/auto-sync/src/autosync/IncGenerator.py @@ -143,9 +143,10 @@ def apply_patches(self) -> None: for patch in patch_dir.iterdir(): try: subprocess.run( - ["git", "apply", "-C4", "--recount", str(patch)], + ["git", "apply", "-v", "--recount", str(patch)], check=True, ) log.info(f"Applied inc patch {patch.name}") except subprocess.CalledProcessError as e: log.warning(f".inc patch {patch.name} did not apply correctly!") + log.warning(f"Error:\n{e.output}") diff --git a/tests/details/arm.yaml b/tests/details/arm.yaml index f8029d4b8f..9247faa88b 100644 --- a/tests/details/arm.yaml +++ b/tests/details/arm.yaml @@ -24,7 +24,7 @@ test_cases: type: ARM_OP_MEM mem_base: r0 mem_index: r6 - access: CS_AC_READ_WRITE + access: CS_AC_READ post_indexed: 1 vector_size: 32 writeback: 1 @@ -54,7 +54,7 @@ test_cases: - type: ARM_OP_MEM mem_base: r2 - access: CS_AC_READ_WRITE + access: CS_AC_READ post_indexed: -1 vector_size: 16 writeback: 1 @@ -1787,7 +1787,7 @@ test_cases: - type: ARM_OP_MEM mem_base: r4 - access: CS_AC_READ_WRITE + access: CS_AC_READ writeback: 1 regs_read: [ r4 ] regs_write: [ r4, d0, d2, d4 ] @@ -2048,7 +2048,7 @@ test_cases: type: ARM_OP_MEM mem_base: r4 mem_align: 0x80 - access: CS_AC_READ_WRITE + access: CS_AC_READ writeback: 1 regs_read: [ d0, d2, d4, d6, r4 ] regs_write: [ r4, d0, d2, d4, d6 ] @@ -2754,3 +2754,74 @@ test_cases: access: CS_AC_READ shift_type: ARM_SFT_UXTW shift_value: 1 + - + input: + bytes: [ 0x2f, 0x6c, 0x64, 0x2d ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "stclhs p12, c6, [r4, #-0xbc]!" + details: + arm: + operands: + - + type: ARM_OP_PIMM + imm: 12 + access: CS_AC_READ + - + type: ARM_OP_CIMM + imm: 6 + access: CS_AC_READ + - + type: ARM_OP_MEM + mem_base: r4 + mem_disp: 0xbc + access: CS_AC_WRITE + subtracted: 1 + cc: ARMCC_HS + writeback: 1 + regs_read: [ cpsr, r4 ] + regs_write: [ r4 ] + - + input: + bytes: [ 0x00, 0x0a, 0x33, 0xf9 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "rfedb r3!" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r3 + access: CS_AC_READ + writeback: 1 + regs_read: [ r3 ] + regs_write: [ r3 ] + - + input: + bytes: [ 0x00, 0x0a, 0x13, 0xf9 ] + arch: "CS_ARCH_ARM" + options: [ CS_OPT_DETAIL ] + address: 0x0 + expected: + insns: + - + asm_text: "rfedb r3" + details: + arm: + operands: + - + type: ARM_OP_MEM + mem_base: r3 + access: CS_AC_READ + writeback: -1 + regs_read: [ r3 ] + regs_write: [ ]