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In the case of the decompose module being used in verify mode, in the current configuration the final buffer_en which is a valid signal for the output w1_o is asserted in the idle state (both fsms in idle) and the done signal is asserted when the fsms are in idle. So, inorder to trigger a next new operation the higher level module needs to send it two clk cycles post done of the current operation. This would be the case if the decompose module is used as a standalone block elsewhere.
The text was updated successfully, but these errors were encountered:
In the case of the decompose module being used in verify mode, in the current configuration the final buffer_en which is a valid signal for the output w1_o is asserted in the idle state (both fsms in idle) and the done signal is asserted when the fsms are in idle. So, inorder to trigger a next new operation the higher level module needs to send it two clk cycles post done of the current operation. This would be the case if the decompose module is used as a standalone block elsewhere.
The text was updated successfully, but these errors were encountered: