From e9917c5d0a336aa9e00d31e4fc83099dd13829ef Mon Sep 17 00:00:00 2001 From: Asuna Date: Tue, 3 Sep 2024 20:30:23 +0200 Subject: [PATCH] [binder] Fix outputs of tests --- .github/workflows/test.yml | 25 ++++- lit/tests/Converter/Module.sc | 92 +++---------------- lit/tests/Property/Good.sc | 2 +- lit/tests/SmokeTest.sc | 8 +- .../src/PanamaCIRCTConverter.scala | 2 +- tests.sc | 2 +- 6 files changed, 45 insertions(+), 86 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index bfdbbe8330b..7f55ba3dfce 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -112,10 +112,31 @@ jobs: with: version: ${{ steps.circt-version.outputs.version }} github-token: ${{ github.token }} + - name: Install Lit + run: pip install lit + - name: Set CIRCT Path Env + run: echo "CIRCT_INSTALL_PATH=$(pwd)/circt" >> $GITHUB_ENV - name: Compile Mill + run: ./mill __.compile + - name: Setup Scala-cli + uses: VirtusLab/scala-cli-setup@v1 + with: + jvm: adoptium:21 + - name: Override Scala-cli binary with CI artifact + run: | + curl -OL https://github.com/SpriteOvO/github-actions-test/raw/main/launchers/scala-cli + chmod +x ./scala-cli + mv ./scala-cli /home/runner/cs/bin/scala-cli + - name: Run Lit Tests + run: | + # https://github.com/VirtusLab/scala-cli/issues/3110 + rm -rf /home/runner/.cache/scalacli + ./mill -i lit[${{ inputs.scala }}].run + - name: Debug + if: always() run: | - export CIRCT_INSTALL_PATH="$(pwd)/circt" - ./mill __.compile + scala-cli --version + cat /home/runner/work/chisel/chisel/out/lit/2.13.14/litConfig.dest/Converter/.scala-build/stacktraces/* doc: name: Formatting diff --git a/lit/tests/Converter/Module.sc b/lit/tests/Converter/Module.sc index db79ad0fa00..87efe206d37 100644 --- a/lit/tests/Converter/Module.sc +++ b/lit/tests/Converter/Module.sc @@ -1,4 +1,4 @@ -// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s -check-prefix=FIRRTL +// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s -check-prefix=FIRRTL -check-prefix=VERILOG // SPDX-License-Identifier: Apache-2.0 import chisel3._ @@ -96,91 +96,25 @@ class Mem extends Module { println(lit.utility.panamaconverter.firrtlString(new Mem)) -// FIRRTL-LABEL: public module Sram : -// FIRRTL-NEXT: input clock : Clock -// FIRRTL-NEXT: input reset : UInt<1> class Sram extends Module { - // FIRRTL: wire mem - // FIRRTL: mem mem_sram - // FIRRTL: connect mem_sram.R0.addr, mem.readPorts[0].address - // FIRRTL-NEXT: connect mem_sram.R0.clk, clock - // FIRRTL-NEXT: connect mem.readPorts[0].data, mem_sram.R0.data - // FIRRTL-NEXT: connect mem_sram.R0.en, mem.readPorts[0].enable - // FIRRTL-NEXT: connect mem_sram.R1.addr, mem.readPorts[1].address - // FIRRTL-NEXT: connect mem_sram.R1.clk, clock - // FIRRTL-NEXT: connect mem.readPorts[1].data, mem_sram.R1.data - // FIRRTL-NEXT: connect mem_sram.R1.en, mem.readPorts[1].enable - // FIRRTL-NEXT: connect mem_sram.W0.addr, mem.writePorts[0].address - // FIRRTL-NEXT: connect mem_sram.W0.clk, clock - // FIRRTL-NEXT: connect mem_sram.W0.data, mem.writePorts[0].data - // FIRRTL-NEXT: connect mem_sram.W0.en, mem.writePorts[0].enable - // FIRRTL-NEXT: connect mem_sram.W0.mask, UInt<1>(1) - // FIRRTL-NEXT: connect mem_sram.W1.addr, mem.writePorts[1].address - // FIRRTL-NEXT: connect mem_sram.W1.clk, clock - // FIRRTL-NEXT: connect mem_sram.W1.data, mem.writePorts[1].data - // FIRRTL-NEXT: connect mem_sram.W1.en, mem.writePorts[1].enable - // FIRRTL-NEXT: connect mem_sram.W1.mask, UInt<1>(1) - // FIRRTL-NEXT: connect mem_sram.RW0.addr, mem.readwritePorts[0].address - // FIRRTL-NEXT: connect mem_sram.RW0.clk, clock - // FIRRTL-NEXT: connect mem_sram.RW0.en, mem.readwritePorts[0].enable - // FIRRTL-NEXT: connect mem.readwritePorts[0].readData, mem_sram.RW0.rdata - // FIRRTL-NEXT: connect mem_sram.RW0.wdata, mem.readwritePorts[0].writeData - // FIRRTL-NEXT: connect mem_sram.RW0.wmode, mem.readwritePorts[0].isWrite - // FIRRTL-NEXT: connect mem_sram.RW0.wmask, UInt<1>(1) - // FIRRTL-NEXT: connect mem_sram.RW1.addr, mem.readwritePorts[1].address - // FIRRTL-NEXT: connect mem_sram.RW1.clk, clock - // FIRRTL-NEXT: connect mem_sram.RW1.en, mem.readwritePorts[1].enable - // FIRRTL-NEXT: connect mem.readwritePorts[1].readData, mem_sram.RW1.rdata - // FIRRTL-NEXT: connect mem_sram.RW1.wdata, mem.readwritePorts[1].writeData - // FIRRTL-NEXT: connect mem_sram.RW1.wmode, mem.readwritePorts[1].isWrite - // FIRRTL-NEXT: connect mem_sram.RW1.wmask, UInt<1>(1) - // FIRRTL-NEXT: connect mem_sram.RW2.addr, mem.readwritePorts[2].address - // FIRRTL-NEXT: connect mem_sram.RW2.clk, clock - // FIRRTL-NEXT: connect mem_sram.RW2.en, mem.readwritePorts[2].enable - // FIRRTL-NEXT: connect mem.readwritePorts[2].readData, mem_sram.RW2.rdata - // FIRRTL-NEXT: connect mem_sram.RW2.wdata, mem.readwritePorts[2].writeData - // FIRRTL-NEXT: connect mem_sram.RW2.wmode, mem.readwritePorts[2].isWrite - // FIRRTL-NEXT: connect mem_sram.RW2.wmask, UInt<1>(1) - val mem = SRAM(1024, UInt(8.W), 2, 2, 3) - - // FIRRTL-NEXT: connect mem.readPorts[0].address, pad(UInt<7>(100), 10) - // FIRRTL-NEXT: connect mem.readPorts[0].enable, UInt<1>(1) + // VERILOG: module mem_sram_1024x8 + val mem = SRAM(1024, UInt(8.W), 1, 1, 1) + mem.readPorts(0).address := 100.U mem.readPorts(0).enable := true.B + mem.writePorts(0).address := 5.U + mem.writePorts(0).enable := true.B + mem.writePorts(0).data := 12.U + mem.readwritePorts(0).address := 5.U + mem.readwritePorts(0).enable := true.B + mem.readwritePorts(0).isWrite := true.B + mem.readwritePorts(0).writeData := 100.U - // FIRRTL-NEXT: wire foo : UInt<8> - // FIRRTL-NEXT: connect foo, mem.readPorts[0].data val foo = WireInit(UInt(8.W), mem.readPorts(0).data) - - // FIRRTL-NEXT: connect mem.writePorts[1].address, pad(UInt<3>(5), 10) - // FIRRTL-NEXT: connect mem.writePorts[1].enable, UInt<1>(1) - // FIRRTL-NEXT: connect mem.writePorts[1].data, pad(UInt<4>(12), 8) - mem.writePorts(1).address := 5.U - mem.writePorts(1).enable := true.B - mem.writePorts(1).data := 12.U - - // FIRRTL-NEXT: connect mem.readwritePorts[2].address, pad(UInt<3>(5), 10) - // FIRRTL-NEXT: connect mem.readwritePorts[2].enable, UInt<1>(1) - // FIRRTL-NEXT: connect mem.readwritePorts[2].isWrite, UInt<1>(1) - // FIRRTL-NEXT: connect mem.readwritePorts[2].writeData, pad(UInt<7>(100), 8) - mem.readwritePorts(2).address := 5.U - mem.readwritePorts(2).enable := true.B - mem.readwritePorts(2).isWrite := true.B - mem.readwritePorts(2).writeData := 100.U - - // FIRRTL-NEXT: connect mem.readwritePorts[2].address, pad(UInt<3>(5), 10) - // FIRRTL-NEXT: connect mem.readwritePorts[2].enable, UInt<1>(1) - // FIRRTL-NEXT: connect mem.readwritePorts[2].isWrite, UInt<1>(0) - mem.readwritePorts(2).address := 5.U - mem.readwritePorts(2).enable := true.B - mem.readwritePorts(2).isWrite := false.B - - // FIRRTL-NEXT: wire bar : UInt<8> - // FIRRTL-NEXT: connect bar, mem.readwritePorts[2].readData - val bar = WireInit(UInt(8.W), mem.readwritePorts(2).readData) + val bar = WireInit(UInt(8.W), mem.readwritePorts(0).readData) } -println(lit.utility.panamaconverter.firrtlString(new Sram)) +println(lit.utility.panamaconverter.verilogString(new Sram)) // FIRRTL-LABEL: public module WireAndReg : // FIRRTL-NEXT: input clock : Clock diff --git a/lit/tests/Property/Good.sc b/lit/tests/Property/Good.sc index 59ba6fb2f2f..3ed862d44a8 100644 --- a/lit/tests/Property/Good.sc +++ b/lit/tests/Property/Good.sc @@ -8,7 +8,7 @@ import chisel3.panamaom._ import lit.utility._ // SFC-FIRRTL-LABEL: circuit IntPropTest : -// SFC-FIRRTL-NEXT: module IntPropTest : +// SFC-FIRRTL: module IntPropTest : // SFC-FIRRTL-NEXT: output intProp : Integer class IntPropTest extends RawModule { val intProp = IO(Output(Property[Int]())) diff --git a/lit/tests/SmokeTest.sc b/lit/tests/SmokeTest.sc index 5f004a7f7f4..215def03ad5 100644 --- a/lit/tests/SmokeTest.sc +++ b/lit/tests/SmokeTest.sc @@ -11,14 +11,18 @@ class FooBundle extends Bundle { } // SFC-FIRRTL-LABEL: circuit FooModule : -// SFC-FIRRTL-NEXT: module FooModule : +// SFC-FIRRTL-NEXT: layer Verification, bind, "Verification" : +// SFC-FIRRTL-NEXT: layer Assert, bind, "Verification/Assert" : +// SFC-FIRRTL-NEXT: layer Assume, bind, "Verification/Assume" : +// SFC-FIRRTL-NEXT: layer Cover, bind, "Verification/Cover" : +// SFC-FIRRTL-NEXT: public module FooModule : // SFC-FIRRTL-NEXT: input clock : Clock // SFC-FIRRTL-NEXT: input reset : UInt<1> // SFC-FIRRTL-NEXT: output io : { flip foo : UInt<3>} // SFC-FIRRTL: skip // MFC-FIRRTL-LABEL: circuit FooModule : -// MFC-FIRRTL-NEXT: module FooModule : +// MFC-FIRRTL-NEXT: public module FooModule : // MFC-FIRRTL-NEXT: input clock : Clock // MFC-FIRRTL-NEXT: input reset : UInt<1> // MFC-FIRRTL-NEXT: output io : { flip foo : UInt<3> } diff --git a/panamaconverter/src/PanamaCIRCTConverter.scala b/panamaconverter/src/PanamaCIRCTConverter.scala index 0efca307a3b..642b51954ae 100644 --- a/panamaconverter/src/PanamaCIRCTConverter.scala +++ b/panamaconverter/src/PanamaCIRCTConverter.scala @@ -1339,7 +1339,7 @@ class PanamaCIRCTConverter(val circt: PanamaCIRCT, fos: Option[FirtoolOptions], .withNamedAttr("name", circt.mlirStringAttrGet(Converter.getRef(firrtlMemory.id, firrtlMemory.sourceInfo).name)) .withNamedAttr("nameKind", circt.firrtlAttrGetNameKind(FIRRTLNameKind.InterestingName)) .withNamedAttr("annotations", circt.emptyArrayAttr) - .withNamedAttr("portAnnotations", circt.emptyArrayAttr) + .withNamedAttr("portAnnotations", circt.mlirArrayAttrGet(ports.map(_ => circt.emptyArrayAttr))) .withResults(ports.map { case (_, tpe) => tpe }) .build() val results = ports.zip(op.results).map { case ((name, _), result) => name -> result }.toMap diff --git a/tests.sc b/tests.sc index 0c7eaa9981b..7e7ba5c56fc 100644 --- a/tests.sc +++ b/tests.sc @@ -89,7 +89,7 @@ trait LitModule extends Module { PathRef(T.dest) } def run(args: String*) = T.command( - os.proc("lit", litConfig().path) + os.proc("lit", litConfig().path, "-a") .call(T.dest, stdout = os.ProcessOutput.Readlines(line => T.ctx().log.info("[lit] " + line))) ) }