From ee6b214d02f992f594e121567c8330dcae41420f Mon Sep 17 00:00:00 2001 From: "mergify[bot]" <37929162+mergify[bot]@users.noreply.github.com> Date: Tue, 11 Jun 2024 16:33:58 -0700 Subject: [PATCH] Add a test for issue 4159 (#4161) (#4164) Co-authored-by: Schuyler Eldridge (cherry picked from commit 15115ea6175a8e8d0c67340109439491fb36f2a3) Co-authored-by: Jack Koenig --- src/test/scala/chiselTests/ChiselEnum.scala | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/test/scala/chiselTests/ChiselEnum.scala b/src/test/scala/chiselTests/ChiselEnum.scala index 4462d75cc1f..4e1e26c237f 100644 --- a/src/test/scala/chiselTests/ChiselEnum.scala +++ b/src/test/scala/chiselTests/ChiselEnum.scala @@ -402,6 +402,30 @@ class ChiselEnumSpec extends ChiselFlatSpec with Utils { assertTesterPasses(new CastToUIntTester) } + // This is a bug, but fixing it may break user code. + // See: https://github.com/chipsalliance/chisel/issues/4159 + it should "preserve legacy width behavior" in { + val verilog = ChiselStage.emitSystemVerilog(new RawModule { + val out1, out2, out3 = IO(Output(UInt(8.W))) + val e = EnumExample.e1 + val x = e.asUInt + val y = e.asTypeOf(UInt()) + val z = e.asTypeOf(UInt(e.getWidth.W)) + out1 := Cat(1.U, x) + out2 := Cat(1.U, y) + out3 := Cat(1.U, z) + // The bug is that the width of x is 7 but the value of out1 is 3 + x.getWidth should be(7) + x.getWidth should be(EnumExample.getWidth) + y.widthOption should be(None) + z.getWidth should be(7) + }) + // The bug is that all of these should be the same as out3, or the widths above are wrong + verilog should include("assign out1 = 8'h3;") + verilog should include("assign out2 = 8'h3;") + verilog should include("assign out3 = 8'h81;") + } + it should "cast literal UInts to enums correctly" in { assertTesterPasses(new CastFromLitTester) }