diff --git a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
index fb3f2be865..126910798a 100644
--- a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
+++ b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
@@ -135,7 +135,7 @@ class BlackBoxSourceHelper extends Transform with DependencyAPIMigration {
     //  make[1]: *** No rule to make target `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v', needed by `.../chisel-testers/test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/VAccumBlackBoxWrapper.h'.  Stop.
     //  or we end up including the same file multiple times.
     if (verilogSourcesOnly.nonEmpty) {
-      writeTextToFile(verilogSourcesOnly.map(_.getCanonicalPath).mkString("\n"), filelistFile)
+      writeTextToFile(verilogSourcesOnly.map(_.getCanonicalPath).mkString("\n") + "\n", filelistFile)
     }
 
     state
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index 45be4cb373..62160e096c 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -193,4 +193,19 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
     new File(subdir, filename) should exist
     new File(dir, filename) shouldNot exist
   }
+
+  "verilog file list" should "end with a newline" in {
+    val annos = Seq(
+      BlackBoxTargetDirAnno("test_run_dir"),
+      BlackBoxResourceAnno(moduleName, "/blackboxes/AdderExtModule.v")
+    )
+
+    execute(input, output, annos)
+
+    val filename = os.pwd / "test_run_dir" / BlackBoxSourceHelper.defaultFileListName
+    assert(os.exists(filename), "verilog file list should exist")
+    val content = os.read(filename)
+    assert(content.contains("AdderExtModule.v"))
+    assert(content.last == '\n', "Some simulators like Icarus Verilog seem to expect a trailing new line character")
+  }
 }