From a95df00ee050fa63db4db55f5b9115711e4c9f5e Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Mon, 5 Apr 2021 12:18:49 -0700 Subject: [PATCH] Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDoc --- src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala | 9 +++++---- src/main/scala/firrtl/transforms/SimplifyMems.scala | 3 ++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala b/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala index c6975712ea..dd2324a3d0 100644 --- a/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala +++ b/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala @@ -13,9 +13,7 @@ import firrtl.options.{HasShellOptions, ShellOption} * to any particular vendor; instead, they aim to emit simple Verilog that more closely reflects traditional * human-written definitions of synchronous-read memories. * - * 1) Add a [[firrtl.passes.memlib.PassthroughSimpleSyncReadMemsAnnotation]] to allow some synchronous-read memories - * and readwrite ports to pass through [[firrtl.passes.memlib.VerilogMemDelays]] without introducing explicit - * pipeline registers or splitting ports. + * 1) Enable the [[firrtl.passes.memlib.InferReadWrite]] transform to reduce port count, where applicable. * * 2) Use the [[firrtl.transforms.SimplifyMems]] transform to Lower aggregate-typed memories with always-high masks to * packed memories without splitting them into multiple independent ground-typed memories. @@ -30,7 +28,10 @@ import firrtl.options.{HasShellOptions, ShellOption} * default. This eliminates the difficulty of inferring a RAM macro that matches the strict semantics of * "write-first" ports. * - * 5) Enable the [[firrtl.passes.memlib.InferReadWrite]] transform to reduce port count, where applicable. + * 5) Add a [[firrtl.passes.memlib.PassthroughSimpleSyncReadMemsAnnotation]] to allow some synchronous-read memories + * and readwrite ports to pass through [[firrtl.passes.memlib.VerilogMemDelays]] without introducing explicit + * pipeline registers or splitting ports. + * */ object OptimizeForFPGA extends HasShellOptions { private val fpgaAnnos = Seq( diff --git a/src/main/scala/firrtl/transforms/SimplifyMems.scala b/src/main/scala/firrtl/transforms/SimplifyMems.scala index 81c40dd45b..92e19f7e0a 100644 --- a/src/main/scala/firrtl/transforms/SimplifyMems.scala +++ b/src/main/scala/firrtl/transforms/SimplifyMems.scala @@ -6,6 +6,7 @@ package transforms import firrtl.ir._ import firrtl.Mappers._ import firrtl.annotations._ +import firrtl.options.Dependency import firrtl.passes._ import firrtl.passes.memlib._ import firrtl.stage.Forms @@ -21,7 +22,7 @@ import ResolveMaskGranularity._ class SimplifyMems extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm - override def optionalPrerequisites = Seq.empty + override def optionalPrerequisites = Seq(Dependency[InferReadWrite]) override def optionalPrerequisiteOf = Forms.MidEmitters override def invalidates(a: Transform) = a match { case InferTypes => true