Fix build on scala 2.13

chipsalliance · Aug 19, 2021 · bbe94c9 · bbe94c9
1 parent 8fb1b4f
commit bbe94c9
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala b/src/main/scala/firrtl/backends/experimental/rtlil/RtlilEmitter.scala
@@ -756,7 +756,7 @@ private[firrtl] class RtlilEmitter extends SeqTransform with Emitter with Depend
               }
 
             case MemoryScalarInit(value) =>
-              for (addr <- (0 until depth.intValue())) {
+              for (addr <- (0 until depth.intValue)) {
                 initials ++= emit_cell(
                   i,
                   "$meminit_v2",