Make MemConf's MemPort serialization deterministic

[chick]

Problem: MemConf serialization of MemPorts was not deterministic
and the ordering seems to have changed as we move projects to 2.13
Downstream project can be adversely affected by changes in ordering
This changes specifies as specific ordering that should be compatible with
the historically one.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• [NA] Did you update the FIRRTL spec to include every new feature/behavior?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you state the API impact?
• Did you specify the code generation impact?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

Code cleanup

API Impact

This change should preserve existing behavior that was changing as we continue to move to 2.13
Without this change downstream users for MemConf output could break

Backend Code Generation Impact

Verilog output should not be altered

Desired Merge Strategy

Squash and Merge

Release Notes

The order of MemPort fields in serialized MemConf is now guaranteed to be in the following order:

• mrw, mwrite, rw, write, read

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels?
• Did you mark the proper milestone (1.2.x, 1.3.0, 1.4.0) ?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you mark as Please Merge?

[mwachs5]

Non-determinism and hardware generation don't mix, I agree in principle with this change have not done a deep dive on the implementation

[jackkoenig]

Generally looks good but I have a couple of suggestions