Releases: chipsalliance/firrtl
v1.3.0-RC2
Fix
(#1450) Fix dynamic SubAccess of zero-length vectors Fixes #230
(#1474) Fix InlineCasts
(#1481) Fix InlineCasts (bp #1474)
Feature
(#1471) Nuclear Option (-Xfatal-warnings) for Scaladoc Build
(#1482) Add 'did you update spec' box to PR template
(#1493) Disable unidoc -Xfatal-warning for Scala 2.11
(#1495) Add Release Notes section and check-box for checklist.
(#1497) Remove deprecated gender
v1.3.0-RC1
API Modification
(#1123) Dependency API 2 (take 3)
(#1258) Remove scala-logging fully in favor of our own logger
(#1265) Move --no-dedup from stage-global to firrtl-local
(#1266) Remove incorrect --firrtl-source option
(#1357) Omnibus Dependency API Updates
(#1387) Include Dead Modules in InstanceGraph.staticInstanceCount
(#1388) Allow self renames
(#1412) [RFC] Factor-out common test classes; package them
(#1413) Remove DiGraph.seededLinearize
(#1440) Remove dead passes.DeadCodeElimination code
(#1447) Revert Compiler.execute to public (was protected)
(#1461) Change annotation logging
Fix
(#1217) Add explicit EOF to top-level parser rule - Fixes #1154
(#1228) Use getName instead of getSimpleName
(#1241) improve the tail ir usability - bug fix for chipsalliance/chisel#1240
(#1278) {Firrtl, Circuit}Option should be Unserializable
(#1288) Make EmittedAnnotation Unserializable
(#1307) Change LoggerState.globalLevel to Warn
(#1310) Filter ResolvePaths in EliminateTargetPaths
(#1362) Change zero-width base case for Andr* - Fixes #1344
(#1366) Better register const prop through speculative de-optimization - Fixes #1240
(#1370) Rename Modules Duplicated by EliminateTargetPaths
(#1374) Fixing lint error: x + -1
(#1392) Short Circuit resolvePaths if no Targets
(#1394) EliminateTargetPaths and Unreachable Modules
(#1396) Remove last connect semantics from reset inference
(#1397) Add test: driving multiple downstream reset types with cast
(#1422) Revert inline nots
(#1437) Check for name collisions of Modules - Fixes #1436, #1096
(#1441) Don't const-prop a register's self-init - Fixes #1214
(#1454) Make InlineInstances invalidate ResolveKinds - Fixes #1453
(#1477) Support all the bases (octal/bin) outlined in the spec - Fixes #1464
Feature
(#1050) Add Support for Bitstream Preset-registers
(#1190) Logger comment tweaks
(#1191) Add check for multiple sources for same wiring pin
(#1206) Add separate Issue and PR templates
(#1211) Supply a trait to allow user annotations to provide JsonProtocol type hints
(#1216) Change findInstancesInHierarchy to return implicit top instance
(#1218) Ignore extmodule instances in Flatten - Closes #1162
(#1219) Guard initial blocks in emitted Verilog with ifndef SYNTHESIS
(#1222) Add spec for Analog type and attach statement - Closes #1194
(#1224) Move CheckResets after CheckCombLoops
(#1231) Use Mergify to automate backporting to 1.2.x
(#1238) Error on nested memory datatypes
(#1243) Make updated type info available in VerilogMemDelays - Closes #1242
(#1245) [Mergify] Automatically merge backport PRs when ready
(#1259) Cleanup testing console
(#1264) Cleanup verilog emitter casts
(#1270) Verilog emitter transform InlineNots
(#1271) Make the member 'logger' added by the trait LazyLogging protected.
(#1275) Support object transforms
(#1282) Fix incorrect ScalaDoc link
(#1284) Improve Scaladoc
(#1291) Infer resets last connect semantics
(#1296) Verilog emitter transform InlineBitExtractions
(#1297) Fix .run_formal_checks.sh skipping logic
(#1302) Dedup PassTests, add NoCircuitDedupAnnotations
(#1305) Change default LogLevel to Warn
(#1315) clean up warnings: trim unused imports
(#1317) Refactoring checkCatArgumentLegality
(#1321) add IsModule, IsMember, CompleteTarget serializers
(#1323) Dedup: check if moduleOpt exists before getting
(#1324) Fix copy-paste error in DiGraph.linearize documentation
(#1326) Update sbt-scalafix to 0.9.11
(#1327) Update sbt-assembly to 0.14.10
(#1328) Update sbt-buildinfo to 0.9.0
(#1329) Update sbt-unidoc to 0.4.2
(#1330) Update protoc-jar to 3.11.1
(#1331) Update sbt-antlr4 to 0.8.2
(#1332) Update junit to 4.13
(#1333) Update commons-text to 1.8
(#1335) Update sbt-scoverage to 1.6.1
(#1336) Update scalacheck to 1.14.3
(#1345) Update sbt-unidoc to 0.4.3
(#1354) Update sbt to 1.3.8
(#1355) Add constant prop to async regs
(#1359) Emit 'else' case for trivial-valued async reset regs to avoid latches
(#1361) Constant prop binary PrimOps with matching arguments
(#1367) Support MemConfs with very deep memories
(#1368) Mill Support
(#1375) Add reviewer checklist / update contributor checklist
(#1378) [spec] Change sub(UInt, UInt) output type to UInt
(#1381) Removed unused imports in src/test/
(#1382) Update ScalaTest deprecations.
(#1383) Update scalatest 3.1.0
(#1391) Add InstaceGraph (Un)?Reachable Helpers
(#1401) Add more docs / tests for DiGraph reachableFrom method
(#1407) sbt compatible publish for mill
(#1408) mill: add testOnly
(#1409) [spec] clarify that div-by-zero is undefined
(#1414) Update single-line when/else example in spec to match implementation - Closes #890
(#1416) Remove RenameMap logging from EliminateTargetPaths
(#1418) Fix error message for NegWidthException
(#1420) Support Java API doc Scaladoc/Unidoc References
(#1421) Check sign of primop constants where appropriate
(#1423) Clone Verilator from GitHub, fix tag name
(#1429) Make mergify open backport PRs & signal on failed cherry-picks
(#1430) Add firrtl-json serializers
(#1433) Provide an annotation mix-in that marks RTs as dontTouch
(#1439) [mergify] Update match string for labeling backported PRs
(#1446) Avoid generating out-of-bounds indices in ReplaceAccesses
(#1449) Remove toNamed (and friends) deprecation.
(#1451) [spec] Update Mid FIRRTL spec to reflect removal of subaccesses
(#1458) Add method to CheckCompLoops which returns its full netlist
(#1463) Explicitly initialize firrtl.stage.Forms to prevent multi-thread collisions - addresses #1462
(#1465) Refactor build.sbt into more normal style
(#1470) Eliminate warnings on sbt doc and sbt unidoc
(#1473) Bump to Scala 2.12.11
v1.2.4
Fix
(#1404) Short Circuit resolvePaths if no Targets (bp #1392)
(#1411) [spec] clarify that div-by-zero is undefined (bp #1409)
(#1415) Update single-line when/else example in spec to match implementation (bp #1414)
(#1419) Fix error message for NegWidthException (bp #1418)
(#1425) Revert inline nots only 1.2.x (bp #1422). Fixes #1426
(#1423) Clone Verilator from GitHub, fix tag name
(#1431) Check sign of primop constants where appropriate (bp #1421)
v1.2.3
Bug
This release contains #1270, which unfortunately introduced issue #1426.
API Modification
(#1294) Make EmittedAnnotation Unserializable (bp #1288)
(#1342) add IsModule, IsMember, CompleteTarget serializers (bp #1321)
Fix
(#1283) Fix incorrect ScalaDoc link (bp #1282)
(#1352) Fix conversion of Reference-containing expressions to ReferenceTargets (bp #1349)
(#1369) Better register const prop through speculative de-optimization (bp #1366) - fixes #1240
(#1386) Fixing lint error: x + -1 (bp #1374)
(#1398) Remove last connect semantics from reset inference (bp #1396)
Feature
(#1285) Improve Scaladoc (bp #1284)
(#1295) Verilog emitter transform InlineNots (bp #1270)
(#1299) Cleanup verilog emitter casts (bp #1264)
(#1303) Dedup PassTests, add NoCircuitDedupAnnotations (bp #1302)
(#1306) Change default LogLevel to Warn (bp #1305)
(#1313) Filter ResolvePaths in EliminateTargetPaths (bp #1310)
(#1314) Verilog emitter transform InlineBitExtractions (bp #1296)
(#1318) Refactoring checkCatArgumentLegality (bp #1317)
(#1353) Dedup: check if moduleOpt exists before getting (bp #1323)
(#1360) Emit 'else' case for trivial-valued async reset regs to avoid latches (bp #1359)
(#1363) Add constant prop to async regs (bp #1355)
(#1373) Rename Modules Duplicated by EliminateTargetPaths (bp #1370)
(#1384) Add reviewer checklist / update contributor checklist (bp #1375)
(#1385) Support MemConfs with very deep memories (bp #1367)
(#1395) Constant prop binary PrimOps with matching arguments (bp #1361)
(#1402) Add more docs / tests for DiGraph reachableFrom method (bp #1401)
v1.2.2
v1.2.1
Fix
(#1202/#1225) Fix handling of read enables for write-first (default) memories in VerilogMemDelays
Add tests for memories with latency >1, toggling enables
Add library for streamlined Verilog execution tests
Add test for #1179: comb-loops from VerilogMemDelays
Fix write-first mem enable handling in VerilogMemDelays
(#1246) Error on nested memory datatypes (bp #1238)
Feature
(#1204) Emit Verilog else-if for Register Updates
(#1208) Enhance CheckCombLoops errors with connection info
Add EdgeData trait to mix in to graphs
(#1223) Revert binary-compatibility breaking changes since 1.2.0 and enforce checking
Set up CI for 1.2.x branch
(#1226) Change findInstancesInHierarchy to return implicit top instance (bp #1216)
(#1236) [Backport #1222] Add spec for Analog type and attach statement
(#1243) Make updated type info available in VerilogMemDelays
(#1248) Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS (bp #1219)
(#1250) Add explicit EOF to top-level parser rule (bp #1217)
(#1251) Add separate Issue and PR templates (bp #1206)
(#1252) Add check for multiple sources for same wiring pin (bp #1191)
(#1253) Move CheckResets after CheckCombLoops (bp #1224)
(#1254) getSimpleName considered harmful (bp #1228)
(#1255) Ignore extmodule instances in Flatten (bp #1218)
(#1256) Try fixing travis binary compatibility check
v1.2.0
Fix
(#1183) Implement read-first memory behavior in Verilog
Implement read-first memories in VerilogMemDelays
Add read-under-write checks for memory emission
Improve read-under-write parameter support
(#1192) Restore ResolveGenders to its status as a Pass
Feature
(#1186) Absorb some instance analysis into InstanceGraph, use safer boxed Strings
(#1187) Bump sbt to 1.3.2
(#1188) [RFC] Define read-write collison for independently clocked mem ports
(#1189) Add explicit hline instead of phantom h1
(#1197) Add Block factory from argument list of Statements
(#1199) Make TopWiringTransform Idempotent
Add test for TopWiringTransform idempotency
v1.2.0-RC2
Feature
(#1073) Rename annotations in InlineInstances
update inline transform and testcases
(#1124) Gender to Flow
Update Spec from Gender to Flow
Deprecate Gender and add implicit Flow conversion
Rename gender to flow
(#1155) Bump Scala to 2.12.10
(#1167) Add cold benchmarking script
(#1174) Provide a name for each Travis build stage
(#1177) Add space, s/Github/GitHub/ in DontTouchException
(#1180) Update Travis stage names to match new versions
(#1181) Bump sbt to 1.3.0
(#1182) Speed up InlineInstances
(#1184) Faster inline renaming
v1.2.0-RC1
API Modification
(#952) Add foreach as alternative to map
(#1107) Remove deprecated ComponentName from CombinationalPath annotation
Fix
(#854) Binding support - load memory from file
Binding support
(#868) Make RemoveWires properly include registers in dependency graph
Respect register references in RemoveWires
(#876) Fix NoDedupMem to be cognizant of Module scope
(#883) Filter resource file names to avoid including the same file multiple times.
(#901) Use "" for Inline Name Mangling, Respect Namespaces
Inlining uses "", respects namespaces
Make some Uniquify methods private [firrtl]
Add cloneUnderlying method to Namespace
(#909) Verilog renaming uses "_", works on whole AST
Refactor VerilogRename -> RemoveKeywordCollisions
(#924) Fix TRAVIS_COMMIT_RANGE in .run_chisel_tests, replace ... with ..
(#936) Fix bug in TargetDirAnnotation compatibility
(#963) Remove side effect from DiGraph sum
Remove side effect from DiGraph summation
(#976) Fix NoneCompiler outputForm
Require transforms.size >= 1 for Compilers
Use IdentityTransform to construct NoneCompiler
Add IdentityTransform
(#987) Fix grouping
Fix GroupComponents to work with unused components
Make GroupComponents run ResolveKinds
(#989) Avoid enforcing time constrains during coverage tests.
(#992) Constant Propagate dshl and dshr with constant amounts
Suppress unchecked warning in Constant Propagation
Keep constant propagating expressions until done optimizing
(#1078) Add register init to RemoveWires dependencies
(#1135) Add ExpandConnects to TopWiringTransform fixup
Feature
(#548) Run CheckHighForm after all non-emitter transforms in firrtl tests
(#833) Support for load memory annotations in chisel
(#848) Make Scala 2.12.4 the default.
(#849) Constant prop add
(#851) Combine cats
(#855) Use LinkedHashSet in propagateAnnotations
(#858) Fix Travis
(#859) allowing overrides to $random
(#861) add link to repo for firrtl syntax highlighting in sublime text 3
(#864) Update DontTouchAnnotation not found error message
(#865) Instance Annotations
(#867) Stop reporting exceptions in custom transformations as internal errors
(#869) Add targetDirName test
(#872) Allow the #delay before random initialization to be overridden
(#874) Emit Verilog Comments
(#875) [F764.1] Bump scopt from 3.6.0 -> 3.7.0
Bump scopt from 3.6.0 -> 3.7.0
(#877) [F764.2] Easy conversion of String => LogLevel.value
Add LogLevel apply for String => LogLevel.Value
(#878) [F764.3] Add explicit SystemVerilogCompiler class
Add SystemVerilogCompiler class
(#879) [F764.5] Add firrtl.options package, but do not use
Add firrtl.options tests
Add firrtl.options
(#885) Bug Fixes in TopWiring
(#888) Do not remove ExtMods with no ports by default
(#889) Another TopWiring Bug Fix (Multi-Level Annotations)
(#894) Number all code examples & add specification build to Makefile
(#895) Add CODEOWNERS file
(#898) Enforce port uniqueness in Chirrtl/High Checks
(#900) Add Utils.expandPrefixes as Prefix Unique helper
(#903) add BlackBoxPathAnno
(#915) Added reference to ICCAD paper
(#918) Don't include verilog header files in "FileList" for VCS/Verilator.
(#919) [F764.6] Add, but do not use Options-mirroring Annotations
Make ClockListAnnotation a RegisteredTransform
Make InlineInstances a RegisteredTransform
Make CheckCombLoops a RegisteredTransform
Make DeadCodeElimination a RegisteredTransform
Add MemLibOptions RegisteredLibrary
Make ReplSeqMem mixin HasScoptOptions
Make InferReadWrite mixin HasScoptOptions
Add FirrtlOptions
(#921) Better error message on missing BlackBox resource
(#925) Revert "Instance Annotations"
Revert "Instance Annotations (#865)"
(#926) Instance Annotations, Try No. 2
Instance Annotations
(#927) Fix $TRAVIS_COMMIT_RANGE
(#928) Dont append to lists
Remove all uses of get_flip and deprecate
Use Vector instead of List for bulk renaming in RenameMap
Speed up LowerTypes by replacing foldLeft + List appends with flatMap
Speed up ExpandWhens by replacing foldLeft + List appends with flatMap
Speed up create_exps by replacing foldLeft + List appends with flatMap
Speed up ExpandConnects by replacing foldLeft + List appends with flatMap
(#930) fix renaming of port annotations in Uniquify
Fix renaming in UniquifyPorts
(#931) Update commandline sbt publishLocal
(#932) Better error message for UninferredWidth exception
Add prettyPrint method to Target
(#938) Add FIRRTL logo to repo and README
(#940) Bump sbt to 1.2.6; update dependencies
(#942) Memoize type of instance refs in RemoveKeywordCollisions
(#945) Change firrtl.options API, add Phase
(#946) Remove firrtl.altIR package
(#949) Make return types of utility functions more specific
(#953) Add "none" compiler
(#954) Replace Mappers with Foreachers in several passes
(#956) Add Width Constraints with Annotations
(#958) Fix bug in dedup where lots of annotations could prevent dedup
(#959) Bump SBT from 1.2.6 to 1.2.7 to fix partial recompilation issue
(#961) Small convenience tweaks to IR/WIR APIs
(#962) Enhance CheckCombLoops to support annotated ExtModule paths
(#967) Fix renaming of annotations with paths
(#969) [Top Wiring] Expand top wiring to work on aggregates
(#975) Give better error when mport references non-existant memory.
(#980) Performance fix of Uniquify for deep bundles
(#982) Update documentation links
(#984) Correctly handle dots in loaded memory paths
(#994) Improve Shl codegen; eliminate Shlw WIR node
(#996) Remove ghpages plugin
(#999) Bump copyright year
(#1000) Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles
(#1001) typo fix
(#1002) Fork all sbt tasks
Fork all sbt test and run tasks
(#1003) Add MidFIRRTL spec
(#1004) Add "mverilog" Compiler Option, MinimumVerilogEmitter
Do Shr constant propagation in Legalize
Add RemoveValidIf to -X mverilog
Add "mverilog" and "sverilog" DriverSpec tests
Add "mverilog" Compiler Option, Compiler Fixes
(#1005) Stage/Phase
Add ShellOption, DeletedWrapper
OptionsView/Viewer typeclass canonicalizations
Add tests for Annotations/Options refactor
Add FirrtlStage, make Driver compatibility layer
Improve registered library help text
(#1006) Use default test_run_dir for more DriverSpec tests.
(#1008) Use apache commons for string escaping instead of reflection
(#1009) Missed constprop opportunity
(#1010) Mem helpers
(#1011) Asynchronous Reset
(#1012) Correct Kind info from #1010
(#1014) Fix typo for -c: compiler -> circuit
(#1023) Don't let the main module become deduped out of existence.
(#1024) Prevent Flatten from stripping all annotations
(#1025) No time left for you - quickly rename deep bundles still occasionally fails.
(#1026) Added mergify configuration
(#1027) Added mergify badge to README
(#1029) Bump yosys to 0.8
(#1030) Change mergify to just require an approval
(#1031) Detect and error on registers with flip in type
(#1032) Fix almost all scaladoc warnings, add source links
Add GitHub source links to Scaladoc
Fix almost all Scaladoc warnings
(#1034) Create a simple generic GraphViz renderer for DiGraph
(#1035) Add --nodedup option to facilitate FIRRTL to verilog regression testing.
(#1039) [ExpandWhens] Don't create nodes to hold Muxes with >0 void cases
(#1041) Add a data structure for memory conf reading and writing
(#1043) Make mergify run when no reviews request changes
(#1046) Advertise FIRRTL grammar support in Atom
(#1052) More constprop on muxes
(#1056) Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation
(#1058) Convert the RemoveAccesses object into a class.
(#1060) Fix error reading empty MemConf strings
Designs with no SeqMems should produce empty MemConf strings, and this should be parsable without excepting
(#1063) Correct a typo in spec.tex
(#1065) DCE printf and stop statements with constant-0 enables
Add test for DCE of printf and stop
(#1067) Faster reg constprop
(#1068) Infer reset
(#1069) Remove redundant code
(#1071) LowerTypesSpec: additional unit test
(#1072) Remove unnecessary 'FIRRTLParser' prefix
(#1074) Use scalafix to remove unused import and deprecated procedure syntax
(#1075) Change Memory Depth to a BigInt
(#1076) Use UnknownKind instead misrepresented NodeKind
(#1079) Dependency API
Make Transform extend TransformLike
Add PhaseManager tests
Add DependencyManager and PhaseManager
Add PreservesAll stackable trait for DependencyAPI
Add a DependencyAPI to firrtl.options.Phase
Add seeded topological sort to DiGraph
(#1081) Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMain
(#1082) Bugfix: GroupComponents
(#1085) spec: mixed-input arguments for prim ops are no longer allowed
(#1087) Emit legal Verilog literals for ExtModule IntParams > 32-bit
(#1089) Analog attach order
make analog attachment order fixed with linked hash map
(#1093) Fix typo.
(#1094) Fix bad FirrtlStage deprecation warning
(#1095) Remove unused variables
(#1101) Fix typo
(#1102) Use pattern match instead of hardcode position
(#1106) Add Test for AddDefaults phase
(#1108) Remove shadow type parameter
(#1109) Implement MultiTargetAnnotation
(#1110) Make sure directory exist before writing
(#1111) Add SimplifyMems transform to lower memories without splitting
(#1113) README.md Patches
Fix custom transform example for Stage/Phase
Add Yosys 0.8 as prerequisite (sbt test needs it)
(#1114) Fix typo
(#1118) Remove some warnings
(#1121) Change Dependency API to Class[_ <: A]
Add type aliases for dependencies
(#1126) Fix RenameMap chaining
(#1129) Allow name of blackbox resource .f file to change from static value
(#1134) Filter out more fi...