fpgatest.xise

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  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
    <!-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved. -->
  </header>

  <version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>

  <files>
    <file xil_pn:name="top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation"/>
      <association xil_pn:name="Implementation"/>
    </file>
    <file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation"/>
    </file>
  </files>

  <properties>
    <property xil_pn:name="Device" xil_pn:value="xc3s100e"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E"/>
    <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Module|top"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="fpgatest"/>
    <property xil_pn:name="Package" xil_pn:value="vq100"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
    <property xil_pn:name="Project Description" xil_pn:value="test of fpga"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
    <property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
    <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
  </properties>

  <bindings/>

  <libraries/>

  <partitions>
    <partition xil_pn:name="/top"/>
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