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VGA_mem_mapped.xpr
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VGA_mem_mapped.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2017.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="C:/Zynq_Book/VGA_mem_mapped/VGA_mem_mapped.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="611d0ca1dae447b5a577dc89076c796a"/>
<Option Name="Part" Val="xc7z020clg484-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="em.avnet.com:zed:part0:1.3"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../AVNET_ZED_HDMI/2014_1/avnet_zed_hdmi_core"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../VGA_1_0_D"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
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<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/VGA_top/VGA_top.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
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<Proxy FileSetName="VGA_top_rst_ps7_0_100M_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="VGA_top.bd" FileRelPathName="ip/VGA_top_axi_gpio_0_0/VGA_top_axi_gpio_0_0.xci">
<Proxy FileSetName="VGA_top_axi_gpio_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="VGA_top.bd" FileRelPathName="ip/VGA_top_xbar_0/VGA_top_xbar_0.xci">
<Proxy FileSetName="VGA_top_xbar_0"/>
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</CompFileExtendedInfo>
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<Proxy FileSetName="VGA_top_VGA_v1_0_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="VGA_top.bd" FileRelPathName="ip/VGA_top_auto_pc_1/VGA_top_auto_pc_1.xci">
<Proxy FileSetName="VGA_top_auto_pc_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="VGA_top.bd" FileRelPathName="ip/VGA_top_auto_pc_0/VGA_top_auto_pc_0.xci">
<Proxy FileSetName="VGA_top_auto_pc_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/VGA_top/hdl/VGA_top_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="VGA_top_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
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<Filter Type="Constrs"/>
<File Path="$PPRDIR/zedboard_constraints.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/debug.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/debug.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="VGA_top_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
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<Config>
<Option Name="TopModule" Val="VGA_top_rst_ps7_0_100M_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="VGA_top_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/VGA_top_axi_gpio_0_0">
<Config>
<Option Name="TopModule" Val="VGA_top_axi_gpio_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="VGA_top_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/VGA_top_xbar_0">
<Config>
<Option Name="TopModule" Val="VGA_top_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="VGA_top_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/VGA_top_processing_system7_0_0">
<Config>
<Option Name="TopModule" Val="VGA_top_processing_system7_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="VGA_top_VGA_v1_0_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/VGA_top_VGA_v1_0_0_0">
<Config>
<Option Name="TopModule" Val="VGA_top_VGA_v1_0_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="VGA_top_auto_pc_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/VGA_top_auto_pc_1">
<Config>
<Option Name="TopModule" Val="VGA_top_auto_pc_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="VGA_top_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/VGA_top_auto_pc_0">
<Config>
<Option Name="TopModule" Val="VGA_top_auto_pc_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design">
<Option Id="FlattenHierarchy">1</Option>
</Step>
</Strategy>
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