From 6cce004f9e7d3384e1cbdce25cce4949bea731e2 Mon Sep 17 00:00:00 2001 From: Dong-Heon Jung Date: Mon, 10 Jul 2023 14:43:15 +0900 Subject: [PATCH 1/4] [RISC-V] Fix GitHub_17585 test failure --- src/coreclr/vm/riscv64/virtualcallstubcpu.hpp | 31 +++++++++---------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp b/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp index 53a3c2c0ac9187..665f9fa1b08c7d 100644 --- a/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp +++ b/src/coreclr/vm/riscv64/virtualcallstubcpu.hpp @@ -82,8 +82,7 @@ struct DispatchStub private: friend struct DispatchHolder; - DWORD _entryPoint[9]; - DWORD _pad; + DWORD _entryPoint[8]; size_t _expectedMT; PCODE _implTarget; PCODE _failTarget; @@ -102,14 +101,13 @@ struct DispatchHolder void Initialize(DispatchHolder* pDispatchHolderRX, PCODE implTarget, PCODE failTarget, size_t expectedMT) { // auipc t4,0 - // addi t4, t4, 36 - // ld t0,0(a0) ; methodTable from object in $a0 - // ld t6,0(t4) // t6 _expectedMT - // bne t6, t0, failLabel - // ld t4, 8(t4) // t4 _implTarget + // ld t0, 0(a0) // methodTable from object in $a0 + // ld t6, 32(t4) // t6 _expectedMT + // bne t6, t0, failLabel + // ld t4, 40(t4) // t4 _implTarget // jalr x0, t4, 0 // failLabel: - // ld t4, 16(t4) // t4 _failTarget + // ld t4, 48(t4) // t4 _failTarget // jalr x0, t4, 0 // // @@ -117,15 +115,14 @@ struct DispatchHolder // _implTarget // _failTarget - _stub._entryPoint[0] = DISPATCH_STUB_FIRST_DWORD; // auipc t4,0 // 0x00000e97 - _stub._entryPoint[1] = 0x028e8e93; // addi t4, t4, 40 - _stub._entryPoint[2] = 0x00053283; // ld t0, 0(a0) //; methodTable from object in $a0 - _stub._entryPoint[3] = 0x000ebf83; // ld r6, 0(t4) // t6 _expectedMT - _stub._entryPoint[4] = 0x005f9663; // bne t6, t0, failLabel - _stub._entryPoint[5] = 0x008ebe83; // ld t4, 8(t4) // t4 _implTarget - _stub._entryPoint[6] = 0x000e8067; // jalr x0, t4, 0 - _stub._entryPoint[7] = 0x010ebe83; // ld t4, 16(t4) // t4 _failTarget - _stub._entryPoint[8] = 0x000e8067; // jalr x0, t4, 0 + _stub._entryPoint[0] = DISPATCH_STUB_FIRST_DWORD; // auipc t4,0 // 0x00000e97 + _stub._entryPoint[1] = 0x00053283; // ld t0, 0(a0) // methodTable from object in $a0 + _stub._entryPoint[2] = 0x020ebf83; // ld t6, 32(t4) // t6 _expectedMT + _stub._entryPoint[3] = 0x005f9663; // bne t6, t0, failLabel + _stub._entryPoint[4] = 0x028ebe83; // ld t4, 40(t4) // t4 _implTarget + _stub._entryPoint[5] = 0x000e8067; // jalr x0, t4, 0 + _stub._entryPoint[6] = 0x030ebe83; // ld t4, 48(t4) // t4 _failTarget + _stub._entryPoint[7] = 0x000e8067; // jalr x0, t4, 0 _stub._expectedMT = expectedMT; _stub._implTarget = implTarget; From 3c69208afce1c75bdb3491cf5deaad66a0b31c54 Mon Sep 17 00:00:00 2001 From: Dong-Heon Jung Date: Tue, 11 Jul 2023 18:11:31 +0900 Subject: [PATCH 2/4] [RISC-V] Fix GitHub_23147 test failure --- src/coreclr/jit/codegenriscv64.cpp | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp index 4e6085ad5d9fd0..47fb7f63b05d20 100644 --- a/src/coreclr/jit/codegenriscv64.cpp +++ b/src/coreclr/jit/codegenriscv64.cpp @@ -6510,12 +6510,19 @@ void CodeGen::genJmpMethod(GenTree* jmp) { var_types loadType = TYP_UNDEF; + // NOTE for RISCV64: not supports the HFA. + assert(!varDsc->lvIsHfaRegArg()); if (varTypeIsStruct(varDsc)) { // Must be <= 16 bytes or else it wouldn't be passed in registers, except for HFA, // which can be bigger (and is handled above). noway_assert(EA_SIZE_IN_BYTES(varDsc->lvSize()) <= 16); - loadType = varDsc->GetLayout()->GetGCPtrType(0); + if (emitter::isFloatReg(argReg)) + { + loadType = varDsc->lvIs4Field1 ? TYP_FLOAT : TYP_DOUBLE; + } + else + loadType = varDsc->GetLayout()->GetGCPtrType(0); } else { @@ -6532,14 +6539,21 @@ void CodeGen::genJmpMethod(GenTree* jmp) regSet.AddMaskVars(genRegMask(argReg)); gcInfo.gcMarkRegPtrVal(argReg, loadType); - if (compiler->lvaIsMultiregStruct(varDsc, compiler->info.compIsVarArgs)) + if (varDsc->GetOtherArgReg() < REG_STK) { // Restore the second register. - argRegNext = genRegArgNext(argReg); + argRegNext = varDsc->GetOtherArgReg(); + + if (emitter::isFloatReg(argRegNext)) + { + loadType = varDsc->lvIs4Field2 ? TYP_FLOAT : TYP_DOUBLE; + } + else + loadType = varDsc->GetLayout()->GetGCPtrType(1); - loadType = varDsc->GetLayout()->GetGCPtrType(1); loadSize = emitActualTypeSize(loadType); - GetEmitter()->emitIns_R_S(ins_Load(loadType), loadSize, argRegNext, varNum, TARGET_POINTER_SIZE); + int offs = loadSize == EA_4BYTE ? 4 : 8; + GetEmitter()->emitIns_R_S(ins_Load(loadType), loadSize, argRegNext, varNum, offs); regSet.AddMaskVars(genRegMask(argRegNext)); gcInfo.gcMarkRegPtrVal(argRegNext, loadType); From 31053db3d607af64bc9ee9361416d1f6f8b92a2d Mon Sep 17 00:00:00 2001 From: Dong-Heon Jung Date: Wed, 12 Jul 2023 10:58:58 +0900 Subject: [PATCH 3/4] [RISC-V] Remove lvIsHfaRegArg assertion --- src/coreclr/jit/codegenriscv64.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp index 47fb7f63b05d20..9a2be7682abebe 100644 --- a/src/coreclr/jit/codegenriscv64.cpp +++ b/src/coreclr/jit/codegenriscv64.cpp @@ -6510,8 +6510,6 @@ void CodeGen::genJmpMethod(GenTree* jmp) { var_types loadType = TYP_UNDEF; - // NOTE for RISCV64: not supports the HFA. - assert(!varDsc->lvIsHfaRegArg()); if (varTypeIsStruct(varDsc)) { // Must be <= 16 bytes or else it wouldn't be passed in registers, except for HFA, From c6c0b9fceb83bf240c2c6ce9a39116c864416e53 Mon Sep 17 00:00:00 2001 From: Dong-Heon Jung Date: Fri, 14 Jul 2023 17:59:03 +0900 Subject: [PATCH 4/4] [RISC-V] Update --- src/coreclr/jit/codegenriscv64.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp index 9a2be7682abebe..6a4da5e53244bf 100644 --- a/src/coreclr/jit/codegenriscv64.cpp +++ b/src/coreclr/jit/codegenriscv64.cpp @@ -6520,7 +6520,9 @@ void CodeGen::genJmpMethod(GenTree* jmp) loadType = varDsc->lvIs4Field1 ? TYP_FLOAT : TYP_DOUBLE; } else + { loadType = varDsc->GetLayout()->GetGCPtrType(0); + } } else { @@ -6547,7 +6549,9 @@ void CodeGen::genJmpMethod(GenTree* jmp) loadType = varDsc->lvIs4Field2 ? TYP_FLOAT : TYP_DOUBLE; } else + { loadType = varDsc->GetLayout()->GetGCPtrType(1); + } loadSize = emitActualTypeSize(loadType); int offs = loadSize == EA_4BYTE ? 4 : 8;