Glitch on sclk

[terrywwgit]

I am using ftdi 232h and having an issue where the ftdi is generating and extra sclk.

sclk is running at 10Khz and the gap between the falling edge to the rising edge of the glitch is 8ns, which is long enough to trigger my spi logic and cause it to latch an extra bit.

My python code is really straight forward:

Set up the SPI port

spi = SpiController()
spi.configure("ftdi://::654321/1") #board with usb micro
spi.flush()
spi_tx_port = spi.get_port(cs=0, freq=1e4, mode=0)

    # Write packet data
    write_spi(spi_tx_port, REG_ADD_BYTES_TO_PKT, list(packet_data))

    # Indicate end of packet
    write_spi(spi_tx_port, REG_QUEUE_EOF, [0x00])

    # Strobe the TX register
    write_spi(spi_tx_port, REG_TX_STROBE_ADDR, [0x03])
    print("TX started")

This working fine two days ago with a different FPGA, but with no changes to the python code or my computer setup or the test bed setup I am getting these glitches so of course nothing works.

Any ideas or suggestions would be greatly appreciated since I am out of ideas on how to proceed with this.

I will admit (with great shame) that have to use windows and zadig for this testing, but as I said it has been working great without any issues for months up till 2 days ago.

Terry