From d097c99719f31aa68afdedde09149d6de1d0b600 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 6 Sep 2023 17:33:56 -0500 Subject: [PATCH 1/4] stm32/rcc: add lsi and lse bd abstraction --- embassy-stm32/src/rcc/bd.rs | 76 ++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs index 4d8ed82aa8..b4d21c35f8 100644 --- a/embassy-stm32/src/rcc/bd.rs +++ b/embassy-stm32/src/rcc/bd.rs @@ -1,6 +1,34 @@ +#[allow(dead_code)] +#[derive(Default)] +pub enum LseDrive { + #[cfg(any(rtc_v2f7, rtc_v2l4))] + Low = 0, + MediumLow = 0x01, + #[default] + MediumHigh = 0x02, + #[cfg(any(rtc_v2f7, rtc_v2l4))] + High = 0x03, +} + +#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))] +impl From for crate::pac::rcc::vals::Lsedrv { + fn from(value: LseDrive) -> Self { + use crate::pac::rcc::vals::Lsedrv; + + match value { + #[cfg(any(rtc_v2f7, rtc_v2l4))] + LseDrive::Low => Lsedrv::LOW, + LseDrive::MediumLow => Lsedrv::MEDIUMLOW, + LseDrive::MediumHigh => Lsedrv::MEDIUMHIGH, + #[cfg(any(rtc_v2f7, rtc_v2l4))] + LseDrive::High => Lsedrv::HIGH, + } + } +} + +#[allow(dead_code)] #[derive(Copy, Clone, Debug, PartialEq)] #[repr(u8)] -#[allow(dead_code)] pub enum RtcClockSource { /// 00: No clock NoClock = 0b00, @@ -66,6 +94,38 @@ impl BackupDomain { r } + #[allow(dead_code, unused_variables)] + #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))] + pub fn enable_lse(lse_drive: LseDrive) { + Self::modify(|w| { + #[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))] + w.set_lsedrv(lse_drive.into()); + w.set_lseon(true); + }); + + while !Self::read().lserdy() {} + } + + #[allow(dead_code)] + #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))] + pub fn enable_lsi() { + let csr = crate::pac::RCC.csr(); + + Self::modify(|_| { + #[cfg(not(rtc_v2wb))] + csr.modify(|w| w.set_lsion(true)); + + #[cfg(rtc_v2wb)] + csr.modify(|w| w.set_lsi1on(true)); + }); + + #[cfg(not(rtc_v2wb))] + while !csr.read().lsirdy() {} + + #[cfg(rtc_v2wb)] + while !csr.read().lsi1rdy() {} + } + #[cfg(any( rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5 @@ -74,7 +134,7 @@ impl BackupDomain { pub fn set_rtc_clock_source(clock_source: RtcClockSource) { let clock_source = clock_source as u8; #[cfg(any( - all(not(any(rtc_v3, rtc_v3u5)), not(rtc_v2wb)), + not(any(rtc_v3, rtc_v3u5, rtc_v2wb)), all(any(rtc_v3, rtc_v3u5), not(any(rcc_wl5, rcc_wle))) ))] let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source); @@ -86,6 +146,18 @@ impl BackupDomain { }); } + #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))] + #[allow(dead_code, unused_variables)] + pub fn configure_rtc(clock_source: RtcClockSource, lse_drive: Option) { + match clock_source { + RtcClockSource::LSI => Self::enable_lsi(), + RtcClockSource::LSE => Self::enable_lse(lse_drive.unwrap_or_default()), + _ => {} + }; + + Self::set_rtc_clock_source(clock_source); + } + #[cfg(any( rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5 From c21ad04c2ed2e5bd0c0e53ded4be8d1c4c4a1bc3 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 6 Sep 2023 17:48:12 -0500 Subject: [PATCH 2/4] stm32: extract lse/lsi into bd mod --- embassy-stm32/src/rcc/bd.rs | 6 +++--- embassy-stm32/src/rcc/l4.rs | 35 +++-------------------------------- embassy-stm32/src/rcc/wb.rs | 14 +------------- embassy-stm32/src/rcc/wl.rs | 33 ++------------------------------- 4 files changed, 9 insertions(+), 79 deletions(-) diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs index b4d21c35f8..34b88458f0 100644 --- a/embassy-stm32/src/rcc/bd.rs +++ b/embassy-stm32/src/rcc/bd.rs @@ -95,7 +95,7 @@ impl BackupDomain { } #[allow(dead_code, unused_variables)] - #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))] + #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))] pub fn enable_lse(lse_drive: LseDrive) { Self::modify(|w| { #[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))] @@ -107,7 +107,7 @@ impl BackupDomain { } #[allow(dead_code)] - #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))] + #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))] pub fn enable_lsi() { let csr = crate::pac::RCC.csr(); @@ -146,7 +146,7 @@ impl BackupDomain { }); } - #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))] + #[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))] #[allow(dead_code, unused_variables)] pub fn configure_rtc(clock_source: RtcClockSource, lse_drive: Option) { match clock_source { diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs index c6bccfd260..0083ae5bbe 100644 --- a/embassy-stm32/src/rcc/l4.rs +++ b/embassy-stm32/src/rcc/l4.rs @@ -2,13 +2,13 @@ use core::marker::PhantomData; use embassy_hal_internal::into_ref; use stm32_metapac::rcc::regs::Cfgr; -use stm32_metapac::rcc::vals::{Lsedrv, Mcopre, Mcosel}; +use stm32_metapac::rcc::vals::{Mcopre, Mcosel}; pub use super::bus::{AHBPrescaler, APBPrescaler}; use crate::gpio::sealed::AFType; use crate::gpio::Speed; use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw}; -use crate::pac::{FLASH, PWR, RCC}; +use crate::pac::{FLASH, RCC}; use crate::rcc::bd::{BackupDomain, RtcClockSource}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz; @@ -407,36 +407,7 @@ pub(crate) unsafe fn init(config: Config) { RCC.apb1enr1().modify(|w| w.set_pwren(true)); - match config.rtc_mux { - RtcClockSource::LSE => { - // 1. Unlock the backup domain - PWR.cr1().modify(|w| w.set_dbp(true)); - - // 2. Setup the LSE - RCC.bdcr().modify(|w| { - // Enable LSE - w.set_lseon(true); - // Max drive strength - // TODO: should probably be settable - w.set_lsedrv(Lsedrv::HIGH); - }); - - // Wait until LSE is running - while !RCC.bdcr().read().lserdy() {} - - BackupDomain::set_rtc_clock_source(RtcClockSource::LSE); - } - RtcClockSource::LSI => { - // Turn on the internal 32 kHz LSI oscillator - RCC.csr().modify(|w| w.set_lsion(true)); - - // Wait until LSI is running - while !RCC.csr().read().lsirdy() {} - - BackupDomain::set_rtc_clock_source(RtcClockSource::LSI); - } - _ => unreachable!(), - } + BackupDomain::configure_rtc(config.rtc_mux, None); let (sys_clk, sw) = match config.mux { ClockSrc::MSI(range) => { diff --git a/embassy-stm32/src/rcc/wb.rs b/embassy-stm32/src/rcc/wb.rs index 6496b41e19..efd9646422 100644 --- a/embassy-stm32/src/rcc/wb.rs +++ b/embassy-stm32/src/rcc/wb.rs @@ -293,18 +293,6 @@ pub(crate) fn configure_clocks(config: &Config) { while !rcc.cr().read().hsirdy() {} } - let needs_lsi = if let Some(rtc_mux) = &config.rtc { - *rtc_mux == RtcClockSource::LSI - } else { - false - }; - - if needs_lsi { - rcc.csr().modify(|w| w.set_lsi1on(true)); - - while !rcc.csr().read().lsi1rdy() {} - } - match &config.lse { Some(_) => { rcc.cfgr().modify(|w| w.set_stopwuck(true)); @@ -378,5 +366,5 @@ pub(crate) fn configure_clocks(config: &Config) { config .rtc - .map(|clock_source| BackupDomain::set_rtc_clock_source(clock_source)); + .map(|clock_source| BackupDomain::configure_rtc(clock_source, None)); } diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs index e33690d103..b3ddbae64e 100644 --- a/embassy-stm32/src/rcc/wl.rs +++ b/embassy-stm32/src/rcc/wl.rs @@ -1,5 +1,5 @@ pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale}; -use crate::pac::{FLASH, PWR, RCC}; +use crate::pac::{FLASH, RCC}; use crate::rcc::bd::{BackupDomain, RtcClockSource}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz; @@ -208,36 +208,7 @@ pub(crate) unsafe fn init(config: Config) { while FLASH.acr().read().latency() != ws {} - match config.rtc_mux { - RtcClockSource::LSE => { - // 1. Unlock the backup domain - PWR.cr1().modify(|w| w.set_dbp(true)); - - // 2. Setup the LSE - RCC.bdcr().modify(|w| { - // Enable LSE - w.set_lseon(true); - // Max drive strength - // TODO: should probably be settable - w.set_lsedrv(Lsedrv::High as u8); //---// PAM - should not be commented - }); - - // Wait until LSE is running - while !RCC.bdcr().read().lserdy() {} - - BackupDomain::set_rtc_clock_source(RtcClockSource::LSE); - } - RtcClockSource::LSI => { - // Turn on the internal 32 kHz LSI oscillator - RCC.csr().modify(|w| w.set_lsion(true)); - - // Wait until LSI is running - while !RCC.csr().read().lsirdy() {} - - BackupDomain::set_rtc_clock_source(RtcClockSource::LSI); - } - _ => unreachable!(), - } + BackupDomain::configure_rtc(config.rtc_mux, None); match config.mux { ClockSrc::HSI16 => { From 08410432b5112536ff53b5012601649f27ca9eb1 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 6 Sep 2023 17:51:40 -0500 Subject: [PATCH 3/4] stm32: fix rcc merge --- embassy-stm32/src/rcc/wl.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs index 92bb07967b..cd91c8a779 100644 --- a/embassy-stm32/src/rcc/wl.rs +++ b/embassy-stm32/src/rcc/wl.rs @@ -1,5 +1,6 @@ pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale}; use crate::pac::rcc::vals::Adcsel; +use crate::pac::{FLASH, PWR, RCC}; use crate::rcc::bd::{BackupDomain, RtcClockSource}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz; From 4550452f43648533ea6e3a5a92a5e643d59bd617 Mon Sep 17 00:00:00 2001 From: xoviat Date: Wed, 6 Sep 2023 17:53:02 -0500 Subject: [PATCH 4/4] rustfmt --- embassy-stm32/src/rcc/wl.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs index cd91c8a779..7a03d90606 100644 --- a/embassy-stm32/src/rcc/wl.rs +++ b/embassy-stm32/src/rcc/wl.rs @@ -1,6 +1,6 @@ pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale}; use crate::pac::rcc::vals::Adcsel; -use crate::pac::{FLASH, PWR, RCC}; +use crate::pac::{FLASH, RCC}; use crate::rcc::bd::{BackupDomain, RtcClockSource}; use crate::rcc::{set_freqs, Clocks}; use crate::time::Hertz;