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Fix SMT Memory Bug (bp #1942) #1945
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* smt: add test for write port collision * smt: add missing call to insertDummyAssignsForMemoryOutputs * smt: fix typo in write port code Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 4c6993b) # Conflicts: # src/main/scala/firrtl/backends/experimental/smt/FirrtlToTransitionSystem.scala
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Will re-attempt once the other smt PR backport is in. |
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This is an automated backport of pull request #1942 done by Mergify
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