-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathDECODE.vhd
585 lines (574 loc) · 16.5 KB
/
DECODE.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:14:59 11/19/2017
-- Design Name:
-- Module Name: DECODE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use WORK.def.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DECODE is
port(
--*-- decode part --*--
instruction: IN STD_LOGIC_VECTOR(15 downto 0);
op: OUT STD_LOGIC_VECTOR(3 downto 0); -- tell alu what to do
regToRead1: OUT STD_LOGIC_VECTOR(3 downto 0); -- which register to read accroding to instruction (ASel
regToRead2: OUT STD_LOGIC_VECTOR(3 downto 0); -- (BSel
regToWrite: OUT STD_LOGIC_VECTOR(3 downto 0); -- which register to write back
regWrite: OUT STD_LOGIC; -- whether to write back
memIn: OUT STD_LOGIC_VECTOR(15 downto 0); -- data to write in memory
memWrite: OUT STD_LOGIC; -- whether to write memory
memRead: OUT STD_LOGIC; -- whether to read memory
--*-- fast read & pc set part --*--
--*-- by access register files (using regToRead) --*--
dataRead1 : IN STD_LOGIC_VECTOR (15 downto 0); -- bind to FWDUnit, the true data, can bind to operand?
dataRead2 : IN STD_LOGIC_VECTOR (15 downto 0);
operand1 : OUT STD_LOGIC_VECTOR(15 downto 0); -- data send to alu
operand2 : OUT STD_LOGIC_VECTOR(15 downto 0);
rpc: IN STD_LOGIC_VECTOR (15 downto 0); -- bind back to IF
pcMuxSel : OUT STD_LOGIC; -- bind back to IF 0:PC+1 1:PCVal
pcVal : OUT STD_LOGIC_VECTOR (15 downto 0) -- bind back to IF
);
end DECODE;
architecture Behavioral of DECODE is
begin
-- combinational logic
process(instruction, dataRead1, dataRead2, rpc)
alias opCode: std_logic_vector(4 downto 0) is instruction(15 downto 11);
alias rx: std_logic_vector(2 downto 0) is instruction(10 downto 8);
alias ry: std_logic_vector(2 downto 0) is instruction(7 downto 5);
alias rz: std_logic_vector(2 downto 0) is instruction(4 downto 2);
begin
case opCode is
when "01001" => --ADDIU
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => instruction(7));
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "01000" => --ADDIU3
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= "0" & ry;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 4) <= (others => instruction(3));
operand2(3 downto 0) <= instruction(3 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "01100" => --ADDSP|BTEQZ|MTSP|SW_RS
if instruction(10 downto 8) = "011" then --ADDSP
regToRead1 <= SP;
regToRead2 <= NO_REG;
regToWrite <= SP;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => instruction(7));
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(10 downto 8) = "000" then --BTEQZ
regToRead1 <= T;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
if dataRead1 = ZERO then
pcMuxSel <= '1';
pcVal <= rpc + ((7 downto 0 => instruction(7)) & instruction(7 downto 0));
else
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
elsif instruction(10 downto 8) = "100" then --MTSP
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= SP;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_PASS_A;
operand1 <= dataRead1;
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(10 downto 8) = "010" then --SW_RS
regToRead1 <= SP;
regToRead2 <= RA;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= dataRead2;
memWrite <= '1';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => instruction(7));
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
else --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
when "11100" => --ADDU|SUBU
if instruction(1 downto 0) = "01" then --ADDU
regToRead1 <= "0" & rx;
regToRead2 <= "0" & ry;
regToWrite <= "0" & rz;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2 <= dataRead2;
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(1 downto 0) = "11" then --SUBU
regToRead1 <= "0" & rx;
regToRead2 <= "0" & ry;
regToWrite <= "0" & rz;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_SUB;
operand1 <= dataRead1;
operand2 <= dataRead2;
pcMuxSel <= '0';
pcVal <= (others => '0');
else --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
when "11101" => --AND|CMP|JALA|JR|JRRA|MFPC|OR
if instruction(4 downto 0) = "01100" then --AND
regToRead1 <= "0" & rx;
regToRead2 <= "0" & ry;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_AND;
operand1 <= dataRead1;
operand2 <= dataRead2;
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(4 downto 0) = "01010" then --CMP
regToRead1 <= "0" & rx;
regToRead2 <= "0" & ry;
regToWrite <= T;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_CMP;
operand1 <= dataRead1;
operand2 <= dataRead2;
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(7 downto 0) = "11000000" then --JALR
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= RA;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_PASS_A;
operand1 <= rpc;
operand2 <= (others => '0');
pcMuxSel <= '1';
pcVal <= dataRead1;
elsif instruction(7 downto 0) = "00000000" then --JR
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '1';
pcVal <= dataRead1;
elsif instruction(10 downto 0) = "00000100000" then --JRRA
regToRead1 <= RA;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '1';
pcVal <= dataRead1;
elsif instruction(7 downto 0) = "01000000" then --MFPC
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_PASS_A;
operand1 <= rpc;
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(4 downto 0) = "01101" then --OR
regToRead1 <= "0" & rx;
regToRead2 <= "0" & ry;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_OR;
operand1 <= dataRead1;
operand2 <= dataRead2;
pcMuxSel <= '0';
pcVal <= (others => '0');
else --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
when "00010" => --B
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '1';
pcVal <= rpc + ((4 downto 0 => instruction(10)) & instruction(10 downto 0));
when "00100" => --BEQZ
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
if dataRead1 = ZERO then
pcMuxSel <= '1';
pcVal <= rpc + ((7 downto 0 => instruction(7)) & instruction(7 downto 0));
else
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
when "00101" => --BNEZ
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
if dataRead1 = ZERO then
pcMuxSel <= '0';
pcVal <= (others => '0');
else
pcMuxSel <= '1';
pcVal <= rpc + ((7 downto 0 => instruction(7)) & instruction(7 downto 0));
end if;
when "01101" => --LI
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_PASS_A;
operand1(15 downto 8) <= (others => '0');
operand1(7 downto 0) <= instruction(7 downto 0);
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
when "10011" => --LW
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= '0' & ry;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '1';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 5) <= (others => instruction(4));
operand2(4 downto 0) <= instruction(4 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "10010" => --LW_SP
regToRead1 <= SP;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '1';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => instruction(7));
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "11110" => --MFIH|MTIH
if instruction(7 downto 0) = "00000000" then --MFIH
regToRead1 <= IH;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_PASS_A;
operand1 <= dataRead1;
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(7 downto 0) = "000000001" then --MTIH
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= IH;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_PASS_A;
operand1 <= dataRead1;
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
else --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
when "00001" => --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
when "00110" => --SLL|SRA
if instruction(1 downto 0) = "00" then --SLL
regToRead1 <= "0" & ry;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_SLL;
operand1 <= dataRead1;
operand2(15 downto 3) <= (others => '0');
operand2(2 downto 0) <= instruction(4 downto 2);
pcMuxSel <= '0';
pcVal <= (others => '0');
elsif instruction(1 downto 0) = "11" then --SRA
regToRead1 <= "0" & ry;
regToRead2 <= NO_REG;
regToWrite <= "0" & rx;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_SRA;
operand1 <= dataRead1;
operand2(15 downto 3) <= (others => '0');
operand2(2 downto 0) <= instruction(4 downto 2);
pcMuxSel <= '0';
pcVal <= (others => '0');
else --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
end if;
when "01010" => --SLTI
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= T;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_SLT;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => instruction(7));
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "01011" => --SLTUI
regToRead1 <= "0" & rx;
regToRead2 <= NO_REG;
regToWrite <= T;
regWrite <= '1';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= OP_SLTU;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => '0');
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "11011" => --SW
regToRead1 <= "0" & rx;
regToRead2 <= "0" & ry;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= dataRead2;
memWrite <= '1';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 5) <= (others => instruction(4));
operand2(4 downto 0) <= instruction(4 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when "11010" => --SW_SP
regToRead1 <= SP;
regToRead2 <= "0" & rx;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= dataRead2;
memWrite <= '1';
memRead <= '0';
op <= OP_ADD;
operand1 <= dataRead1;
operand2(15 downto 8) <= (others => instruction(7));
operand2(7 downto 0) <= instruction(7 downto 0);
pcMuxSel <= '0';
pcVal <= (others => '0');
when others => --NOP
regToRead1 <= NO_REG;
regToRead2 <= NO_REG;
regToWrite <= NO_REG;
regWrite <= '0';
memIn <= (others => '0');
memWrite <= '0';
memRead <= '0';
op <= (others => '0');
operand1 <= (others => '0');
operand2 <= (others => '0');
pcMuxSel <= '0';
pcVal <= (others => '0');
end case;
end process;
end Behavioral;