Code

Improve vensim import#300

Code

Merged

bgyori merged 9 commits intomaingyorilab/mira:mainfrom vensim-initialsgyorilab/mira:vensim-initialsCopy head branch name to clipboardFeb 29, 2024

+782-529

Commits

Commits on Feb 29, 2024

• Implement ifthenelse to piecewise

  bgyori

  committed
  395b826

• First pass at parsing out initial values

  

  cthoyt

  authored and

  bgyori

  committed
  6374191

• Handle lookup tables

  

  cthoyt

  authored and

  bgyori

  committed
  843a7df

• Update docs

  

  cthoyt

  authored and

  bgyori

  committed
  67241e1

• Switch piecewise from discrete to continuous

  

  cthoyt

  authored and

  bgyori

  committed
  c53ceee

• Handle issues with parsing ampersand character

  

  cthoyt

  authored and

  bgyori

  committed
  6af86cb

• Consolidate tests

  

  cthoyt

  authored and

  bgyori

  committed
  d380a09

• Add flag for turning on initial value parsing from INTEG expressions

  

  cthoyt

  authored and

  bgyori

  committed
  513c2d6

• Update test_system_dynamics.py

  

  cthoyt

  authored and

  bgyori

  committed
  43804b0