[Multitop, test] chip_sw_rom_ctrl_integrity_check

[johngt]

• Tests should not depend on earlgrey constants. Try removing #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" and see what doesn't compile.
• Replace any dif_rom_ctrl_init with dif_rom_ctrl_init_from_dt to avoid TOP_EARLGREY_rom_ctrl_BASE_ADDR.
• Add //hw/top:dt to deps to get all device table libraries.
• Use bazel build //hw/top:dt_api_hdr and bazel build //hw/top:dt_rom_ctrl_hdr to see the autogenerated DT headers. The _src suffix shows the C files.
• Grep for kClockFreq.*. These are top-specific but don't come from a top_earlgrey header. Replace with dt_clock_frequency(...).
• For ISRs: replace peripheral = with dt_plic_id_to_instance_id and compare to the DT instance using dt_rom_ctrl_instance_id(dt_rom_ctrl_t).
• Again for ISRs, convert the plic IRQ ID to a block-specific ID with dt_rom_ctrl_irq_from_plic_id and switch on that.

The test chip_sw_rom_ctrl_integrity_check should run and pass for Ealrgrey and should build for Darjeeling.