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    • imctk

      Public
      Incremental Model Checking Toolkit
      Rust
      Other
      25101Updated Nov 26, 2024Nov 26, 2024
    • apicula

      Public
      Project Apicula 🐝: bitstream documentation for Gowin FPGAs
      Verilog
      MIT License
      68497135Updated Nov 26, 2024Nov 26, 2024
    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      ISC License
      8953.5k454127Updated Nov 26, 2024Nov 26, 2024
    • nextpnr

      Public
      nextpnr portable FPGA place and route tool
      C++
      ISC License
      2451.3k9410Updated Nov 26, 2024Nov 26, 2024
    • Multi-platform nightly builds of open source digital design and verification tools
      Shell
      ISC License
      77868481Updated Nov 26, 2024Nov 26, 2024
    • eqy

      Public
      Equivalence checking with Yosys
      Python
      Other
      531100Updated Nov 8, 2024Nov 8, 2024
    • sby

      Public
      SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
      Python
      Other
      764084213Updated Nov 7, 2024Nov 7, 2024
    • mcy

      Public
      Mutation Cover with Yosys (MCY)
      C++
      ISC License
      97710Updated Nov 5, 2024Nov 5, 2024
    • abc

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      Other
      5932702Updated Nov 5, 2024Nov 5, 2024
    • RISC-V Formal Verification Framework
      Verilog
      ISC License
      2411233Updated Oct 16, 2024Oct 16, 2024
    • nerv

      Public
      Naive Educational RISC V processor
      SystemVerilog
      Other
      127412Updated Oct 13, 2024Oct 13, 2024
    • HTML
      1400Updated Oct 7, 2024Oct 7, 2024
    • yosys-web

      Public
      Yosys Web Page
      HTML
      6310Updated Oct 7, 2024Oct 7, 2024
    • Verilog
      ISC License
      5401Updated Sep 20, 2024Sep 20, 2024
    • mau

      Public
      Modular Application Utilities
      Python
      ISC License
      3410Updated Aug 12, 2024Aug 12, 2024
    • icestorm

      Public
      Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
      Python
      ISC License
      2251k3817Updated Jul 26, 2024Jul 26, 2024
    • picorv32

      Public
      PicoRV32 - A Size-Optimized RISC-V CPU
      Verilog
      ISC License
      7613.2k5711Updated Jun 27, 2024Jun 27, 2024
    • furo-ys

      Public
      A clean customizable documentation theme for Sphinx
      Sass
      MIT License
      322000Updated Jun 11, 2024Jun 11, 2024
    • A Verilog Synthesis Regression Test
      Shell
      83402Updated Mar 21, 2024Mar 21, 2024
    • Set up your GitHub Actions workflow with a OSS CAD Suite
      TypeScript
      ISC License
      21430Updated Mar 21, 2024Mar 21, 2024
    • sby-gui

      Public
      GUI for SymbiYosys
      C++
      ISC License
      41270Updated Mar 21, 2024Mar 21, 2024
    • Documenting the Lattice ECP5 bit-stream format.
      Python
      Other
      873993312Updated Jan 29, 2024Jan 29, 2024
    • scy

      Public
      Sequence of Covers with Yosys
      SystemVerilog
      Other
      1510Updated Jan 29, 2024Jan 29, 2024
    • Project Trellis database
      Creative Commons Zero v1.0 Universal
      101201Updated Oct 4, 2023Oct 4, 2023
    • padring

      Public
      A padring generator for ASICs
      C++
      ISC License
      82221Updated May 17, 2023May 17, 2023
    • .github

      Public
      0000Updated Apr 4, 2023Apr 4, 2023
    • yosys-manual-build

      Public archive
      Yosys manual
      Dockerfile
      0000Updated Oct 24, 2022Oct 24, 2022
    • Collection of test cases for Yosys
      Verilog
      71711Updated Jan 4, 2022Jan 4, 2022
    • fpga-toolchain

      Public archive
      Multi-platform nightly builds of open source FPGA tools
      C
      GNU General Public License v3.0
      26291212Updated Nov 3, 2021Nov 3, 2021
    • pyosys tests
      Python
      ISC License
      2410Updated Nov 27, 2020Nov 27, 2020