Exceptional values

[Ravenwater]

John Gustafson's email:

Recall that posits have two exception values, 0 and NaR.

Suppose we say every posit has n physical bits and an infinite number of trailing 0 bits, just like any finite fixed-point number. That actually simplifies the description of the fields; the termination bit of the regime, part or all of the exponent field, and part or all of the fraction field can be in the physical bits or the implied trailing 0 bits.

So what is the regime value r when a posit is all 0 bits after the sign? There are an infinite number of 0 bits because there is no terminator 1 bit, so r = –∞. Now look at our formula for "normal" posits:

Suppose you try to apply it to the exception bit patterns.

For the value 000…000 you get s = 0, f = 0, e = 0, and r = –∞. The above formula evaluates to 2^(–∞) = 0. So zero is not actually an exception value at all!

For the value 100…000 you get s = 1, f = 0, e = 0, and r = –∞. The formula evaluates to –2×2^(+∞) = –∞, which is certainly Not a Real. And that justifies why NaR < x tests True for all real x.

Of course, we still have to make 100…000 an exception value because we need a place to dump complex numbers, +∞, 0/0, and all the other indeterminate forms. But I was charmed that, in a way, the formula works universally and certainly eliminates zero as an exception value. I believe it is the first number format to unify zero with all the values of the form m × 2^k that most float-type formats describe. Cool, huh?

For purposes of hardware design, I think those two exception bit patterns are still best handled as exceptions.