Create circuit port between pin and reference layer (#2494)

ansys · Feb 17, 2023 · c3fe413 · c3fe413
1 parent 81ae0c9
commit c3fe413
Showing 1 changed file with 2 additions and 3 deletions.
diff --git a/pyaedt/edb_core/edb_data/simulation_configuration.py b/pyaedt/edb_core/edb_data/simulation_configuration.py
@@ -348,8 +348,7 @@ def cutout_subdesign_expansion(self):
 
     @cutout_subdesign_expansion.setter
     def cutout_subdesign_expansion(self, value):  # pragma: no cover
-        if isinstance(value, (int, float)):
-            self._cutout_subdesign_expansion = value
+        self._cutout_subdesign_expansion = value
 
     @property
     def cutout_subdesign_round_corner(self):
@@ -2004,7 +2003,7 @@ def _read_cfg(self):  # pragma: no cover
                                 else:
                                     print("Unprocessed value for CutoutSubdesignType '{0}'".format(value))
                             elif i.lower().startswith("cutoutsubdesignexpansion"):
-                                self.cutout_subdesign_expansion = float(value)
+                                self.cutout_subdesign_expansion = value
                             elif i.lower().startswith("cutoutsubdesignroundcorners"):
                                 self.cutout_subdesign_round_corner = self._get_bool_value(value)
                             elif i.lower().startswith("sweepinterpolating"):