Releases: riscv-non-isa/riscv-arch-test
Releases · riscv-non-isa/riscv-arch-test
3.8.13
- Fixed missing
FandZfhISA identifiers inZfh/flh-align-01RVTEST_CASE macro.
3.8.12
Corrected missing RV64 strings in RVTEST_CASE macros for Zfh fcvt.h.l and similar tests
3.8.11
- Added test suites for Zfh extensions.
- Introduced half word and half width in Nan boxing functionality to accomdate Zfh extensions.
- Added test suites for Zfinx extensions.
3.8.10
- Updated TEST_JALR_OP in test_macros.h
- The macro no longer works when rd = x0 in versions of GCC newer than 2023.12.20
- riscof throws a message /home/jstine/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b'
- The TEST_JALR_OP macro invokes LA, which does not like x0 as an operand
- replacing LA(rd, 5b) with auipc rd, 0 in test_macros.h solves the compiler issue and produces similar code but without a bunch of preceeding nops
3.8.9
- Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated.
3.8.8
- Fixed macros to allow assembling tests with LLVM.
3.8.7
- Update satp initialization macro
3.8.6
- Fixed check ISA fields to include 32/64 in Zca and CMO tests. Note that the riscv-ctg CGFs have not been updated.
- Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated.
3.8.5
- Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023
- Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E
3.8.3
- Add Zicond ISA extension support