diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_DRIVER_amcfocm4.cpp b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_DRIVER_amcfocm4.cpp index 1d752ce4f4..cf1b4ebd94 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_DRIVER_amcfocm4.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_DRIVER_amcfocm4.cpp @@ -60,7 +60,7 @@ bool embot::hw::bsp::DRIVER::init(const embot::hw::Config &config) // and then, in here we do what we must - embot::hw::dualcore::start2(); + embot::hw::dualcore::init(); return true; } diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_amcfocm4.cpp b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_amcfocm4.cpp index c46070b482..4169434d68 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_amcfocm4.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_bsp_amcfocm4.cpp @@ -66,7 +66,7 @@ bool embot::hw::bsp::specialize() { // all the rest // nothing for now - __HAL_RCC_GPIOE_CLK_ENABLE(); + return true; diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_dualcore_bsp_amcfocm4.cpp b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_dualcore_bsp_amcfocm4.cpp index d8c68e0bec..c76d048ddb 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_dualcore_bsp_amcfocm4.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/embot_hw_dualcore_bsp_amcfocm4.cpp @@ -61,8 +61,8 @@ namespace embot::hw::dualcore::bsp { } Config _config {}; bool BSP::config(const Config &c) const { return true; } - bool BSP::start() const { return true; } const Config& BSP::config() const { return _config; } + bool BSP::init() const { return true; } } #else @@ -70,10 +70,10 @@ namespace embot::hw::dualcore::bsp { namespace embot::hw::dualcore::bsp { #if defined(dualcore_BOOT_cm4master) - constexpr PROP _cm4 = { embot::hw::dualcore::CORE::cm4, embot::hw::dualcore::BOOT::cm4master }; + constexpr PROP _cm4 = { embot::hw::dualcore::CORE::cm4, embot::hw::dualcore::BOOT::cm4master, embot::hw::MTX::one}; Config _config {embot::hw::dualcore::Config::HW::forceinit, embot::hw::dualcore::Config::CMD::activate}; #elif defined(dualcore_BOOT_cm7master) - constexpr PROP _cm4 = { embot::hw::dualcore::CORE::cm4, embot::hw::dualcore::BOOT::cm7master }; + constexpr PROP _cm4 = { embot::hw::dualcore::CORE::cm4, embot::hw::dualcore::BOOT::cm7master, embot::hw::MTX::one}; Config _config {embot::hw::dualcore::Config::HW::forceinit, embot::hw::dualcore::Config::CMD::donothing}; #endif @@ -102,156 +102,36 @@ namespace embot::hw::dualcore::bsp { { return _config; } - - void init_board(); - bool BSP::start() const - { - // ok, now we see what we need to do - init_board(); - - return true; - } void mySystemClock_Config(void); void icub_SystemClock_Config(void); - bool BSP::hwinit() const + bool BSP::init() const { -//#if defined(dualcore_BOOT_cm4master) - if(embot::hw::dualcore::BOOT::cm4master == _cm4.boot) { // the cm4 is master, so it must call HAL_Init() and start the clocks - - //MPU_Config(); - //HAL_MPU_Disable(); - //SCB_EnableICache(); - //SCB_EnableDCache(); + HAL_Init(); // mySystemClock_Config(); icub_SystemClock_Config(); - #warning marco.accame: molto strano che se commento mySystemClock_Config() il LED del CM4 blinka ok ma a 64k } -//#elif defined(dualcore_BOOT_cm7master) else { // the cm4 is slave, so the cm7 has already done everything. - - //SCB_EnableICache(); - //SCB_EnableDCache(); } - -//#endif + return true; } - -//#if defined(dualcore_BOOT_cm7master) - - void waitHWmutex(uint32_t mtx) - { - volatile uint32_t m = mtx; - for(;;) - { - if(HAL_OK == HAL_HSEM_FastTake(m)) - { - break; - } - } - } - -//#endif +} // namespace embot::hw::dualcore::bsp { - void mySystemClock_Config(void); - - void init_board() - { -#if defined(dualcore_BOOT_cm4master) +// in here are the SystemClock_Config() that we use - if(embot::hw::dualcore::Config::HW::forceinit == _config.hw) - { - //MPU_Config(); -// HAL_MPU_Disable(); -// SCB_EnableICache(); -// SCB_EnableDCache(); - HAL_Init(); - mySystemClock_Config(); - #warning marco.accame: molto strano che se commento mySystemClock_Config() il LED del CM4 blinka ok ma a 64 k - } - -// SystemCoreClockUpdate(); - - // and now i process the command for the other core - - constexpr uint32_t hsem0 {0}; - constexpr uint32_t procID0 {0}; - - switch(_config.othercore) - { - case embot::hw::dualcore::Config::CMD::activateandhold: - { - // 1. init the hsems and take hsem-0 - __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); - - // 2. enable the other core - HAL_RCCEx_EnableBootCore(RCC_BOOT_C1); - } break; - - case embot::hw::dualcore::Config::CMD::release: - { - // 1. init the hsems (just in case) and release hsem-0 - __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_Release(hsem0, procID0); - } break; - - case embot::hw::dualcore::Config::CMD::activate: - { - // 1. init the hsems and take hsem-0 - __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); - - // 2. enable the other core - HAL_RCCEx_EnableBootCore(RCC_BOOT_C1); - - // 3. and release hsem-0 - HAL_HSEM_Release(hsem0, procID0); - - } break; - - case embot::hw::dualcore::Config::CMD::donothing: - default: - { - break; - } - } - - #elif defined(dualcore_BOOT_cm7master) - - // just wait until the master core activates the slave core and unlocks the HSEM 0 - __HAL_RCC_HSEM_CLK_ENABLE(); - waitHWmutex(0); - - if(embot::hw::dualcore::Config::HW::forceinit == _config.hw) - { -// //MPU_Config(); -// HAL_MPU_Disable(); -// SCB_EnableICache(); -// SCB_EnableDCache(); -// HAL_Init(); - } - - SystemCoreClockUpdate(); - - #else - #error vcew - #endif - - - } +namespace embot::hw::dualcore::bsp { // from icubtech @@ -424,6 +304,17 @@ namespace embot::hw::dualcore::bsp { } // namespace embot::hw::dualcore::bsp { + +// and in here we have .... + +extern "C" +{ + + + + +} + #endif // dualcore // - support map: end of embot::hw::dualcore diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/system_stm32h7xx-cm4-cm7-gated.c b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/system_stm32h7xx-cm4-cm7-gated.c new file mode 100644 index 0000000000..95fea9cc7b --- /dev/null +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/bsp/system_stm32h7xx-cm4-cm7-gated.c @@ -0,0 +1,1089 @@ + +#if defined(dualcore_BOOT_cm4master) + +/** + ****************************************************************************** + * @file Templates/BootCM4_CM7Gated/Common/Src/system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + + +#include "stm32hal.h" +//#include "stm32h7xx.h" + +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SDRAM mounted + on DISCO board as data memory */ +/*#define DATA_IN_ExtSDRAM*/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ +#if defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + +#ifdef CORE_CM4 + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + + +/* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + +#if defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSDRAM */ + +#endif /* CORE_CM4*/ + +#ifdef CORE_CM4 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#ifdef CORE_CM7 + + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x00000001U; + } + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#error Please #define CORE_CM4 or CORE_CM7 +#endif +#endif + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = CSI_VALUE; + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} +#if defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32h7xx.s before jump to main. + * This function configures the external memories SDRAM + * This SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0; + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB4ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAFEAFFFA; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xF03F000F; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* Configure PDx pins in Pull-up */ + GPIOD->PUPDR = 0x50150005; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAABFFA; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC00F; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* Configure PEx pins in Pull-up */ + GPIOE->PUPDR = 0x55554005; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAABFFAAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFFC00FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* Configure PFx pins in Pull-up */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC000000C; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xBFFEFAFA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0xC0030F0F; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* Configure PGx pins in Pull-up */ + GPIOG->PUPDR = 0x40010505; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0xCCC00000; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAAABFF; + /* Configure PHx pins speed to 100 MHz */ + GPIOH->OSPEEDR = 0xFFFFFC00; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* Configure PHx pins in Pull-up */ + GPIOH->PUPDR = 0x55555400; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)); + /*SDRAM Timing and access interface configuration*/ + /*LoadToActiveDelay = 2 + ExitSelfRefreshDelay = 6 + SelfRefreshTime = 4 + RowCycleDelay = 6 + WriteRecoveryTime = 2 + RPDelay = 2 + RCDDelay = 2 + SDBank = FMC_SDRAM_BANK2 + ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8 + RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 + MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16 + InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 + CASLatency = FMC_SDRAM_CAS_LATENCY_2 + WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE + SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 + ReadBurst = FMC_SDRAM_RBURST_ENABLE + ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/ + + FMC_Bank5_6_R->SDCR[0] = 0x00001800; + FMC_Bank5_6_R->SDCR[1] = 0x00000154; + FMC_Bank5_6_R->SDTR[0] = 0x00105000; + FMC_Bank5_6_R->SDTR[1] = 0x01010351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6_R->SDCMR = 0x00000009; + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6_R->SDCMR = 0x0000000A; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + + FMC_Bank5_6_R->SDCMR = 0x000000EB; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + + FMC_Bank5_6_R->SDCMR = 0x0004400C; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + /* Set refresh count */ + tmpreg = FMC_Bank5_6_R->SDRTR; + FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6_R->SDCR[1]; + FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF); + + /*FMC controller Enable*/ + FMC_Bank1_R->BTCR[0] |= 0x80000000; + + (void)(tmp); +} +#endif /* DATA_IN_ExtSDRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#elif defined(dualcore_BOOT_cm7master) + +/** + ****************************************************************************** + * @file Templates/BootCM7_CM4Gated/Common/Src/system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32hal.h" +//#include "stm32h7xx.h" + +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SDRAM mounted + on DISCO board as data memory */ +/*#define DATA_IN_ExtSDRAM*/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ +#if defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + +#ifdef CORE_CM7 + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x00000001U; + } + + + +/* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + +#if defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSDRAM */ + +#endif /* CORE_CM7*/ + +#ifdef CORE_CM4 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#ifdef CORE_CM7 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#error Please #define CORE_CM4 or CORE_CM7 +#endif +#endif + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = CSI_VALUE; + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} +#if defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32h7xx.s before jump to main. + * This function configures the external memories SDRAM + * This SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0; + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB4ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAFEAFFFA; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xF03F000F; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* Configure PDx pins in Pull-up */ + GPIOD->PUPDR = 0x50150005; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAABFFA; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC00F; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* Configure PEx pins in Pull-up */ + GPIOE->PUPDR = 0x55554005; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAABFFAAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFFC00FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* Configure PFx pins in Pull-up */ + GPIOF->PUPDR = 0x55400555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CC00CC; + GPIOG->AFR[1] = 0xC000000C; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xBFFEFAFA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0xC0030F0F; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* Configure PGx pins in Pull-up */ + GPIOG->PUPDR = 0x40010505; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0xCCC00000; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAAABFF; + /* Configure PHx pins speed to 100 MHz */ + GPIOH->OSPEEDR = 0xFFFFFC00; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* Configure PHx pins in Pull-up */ + GPIOH->PUPDR = 0x55555400; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)); + /*SDRAM Timing and access interface configuration*/ + /*LoadToActiveDelay = 2 + ExitSelfRefreshDelay = 6 + SelfRefreshTime = 4 + RowCycleDelay = 6 + WriteRecoveryTime = 2 + RPDelay = 2 + RCDDelay = 2 + SDBank = FMC_SDRAM_BANK2 + ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8 + RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 + MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16 + InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 + CASLatency = FMC_SDRAM_CAS_LATENCY_2 + WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE + SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 + ReadBurst = FMC_SDRAM_RBURST_ENABLE + ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/ + + FMC_Bank5_6_R->SDCR[0] = 0x00001800; + FMC_Bank5_6_R->SDCR[1] = 0x00000154; + FMC_Bank5_6_R->SDTR[0] = 0x00105000; + FMC_Bank5_6_R->SDTR[1] = 0x01010351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6_R->SDCMR = 0x00000009; + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6_R->SDCMR = 0x0000000A; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + + FMC_Bank5_6_R->SDCMR = 0x000000EB; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + + FMC_Bank5_6_R->SDCMR = 0x0004400C; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; + } + /* Set refresh count */ + tmpreg = FMC_Bank5_6_R->SDRTR; + FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6_R->SDCR[1]; + FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF); + + /*FMC controller Enable*/ + FMC_Bank1_R->BTCR[0] |= 0x80000000; + + (void)(tmp); +} +#endif /* DATA_IN_ExtSDRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#else + #warning pls choose either dualcore_BOOT_cm4master or dualcore_BOOT_cm7master +#endif \ No newline at end of file diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvoptx b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvoptx index 8429e03c9c..5a10083589 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvoptx +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvoptx @@ -135,7 +135,7 @@ 0 ARMRTXEVENTFLAGS - -L200 -Z20 -C0 -M1 -T1 + -L200 -Z16 -C0 -M1 -T1 0 @@ -327,7 +327,7 @@ 0 ULP2CM3 - -UP1123199 -O16846 -S12 -C0 -P00000003 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO51 -TC200000000 -TT400000000 -TP12 -TDX14 -TDD0 -TDS8001 -TDT0 -TDC1F -TIE80000001 -TIP9 -FO7 -FD10000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H745IIKx$CMSIS\Flash\STM32H7x_2048.FLM) + -UP1123199 -O462 -S12 -C0 -P00000003 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO51 -TC200000000 -TT400000000 -TP18 -TDX0 -TDD0 -TDS8001 -TDT0 -TDC1F -TIE80000001 -TIP9 -FO7 -FD10000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H745IIKx$CMSIS\Flash\STM32H7x_2048.FLM) 0 @@ -342,7 +342,7 @@ 0 ARMRTXEVENTFLAGS - -L200 -Z0 -C0 -M1 -T1 + -L200 -Z12 -C0 -M1 -T1 0 @@ -367,11 +367,6 @@ 1 SystemCoreClock,0x0A - - 1 - 1 - SystemCoreClock,0x0A - @@ -430,6 +425,12 @@ + + + OS Support\Event Viewer + 35905 + + 0 0 @@ -442,7 +443,7 @@ main - 0 + 1 0 0 0 @@ -594,7 +595,7 @@ embot::hw - 0 + 1 0 0 0 @@ -802,7 +803,7 @@ embot::app - 0 + 1 0 0 0 @@ -818,6 +819,30 @@ 0 0 + + 7 + 28 + 8 + 0 + 0 + 0 + ..\..\..\..\..\embot\app\embot_app_scope.cpp + embot_app_scope.cpp + 0 + 0 + + + 7 + 29 + 8 + 0 + 0 + 0 + ..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools\embot_tools.cpp + embot_tools.cpp + 0 + 0 + @@ -828,7 +853,7 @@ 0 8 - 28 + 30 8 0 0 @@ -840,7 +865,7 @@ 8 - 29 + 31 8 0 0 @@ -852,7 +877,7 @@ 8 - 30 + 32 8 0 0 @@ -864,7 +889,7 @@ 8 - 31 + 33 8 0 0 @@ -876,7 +901,7 @@ 8 - 32 + 34 8 0 0 @@ -888,7 +913,7 @@ 8 - 33 + 35 8 0 0 @@ -898,6 +923,18 @@ 0 0 + + 8 + 36 + 1 + 0 + 0 + 0 + ..\..\..\bsp\system_stm32h7xx-cm4-cm7-gated.c + system_stm32h7xx-cm4-cm7-gated.c + 0 + 0 + @@ -908,7 +945,7 @@ 0 9 - 34 + 37 8 0 0 diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvprojx b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvprojx index 5a75f1c1b1..fb2cd3aa4a 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvprojx +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/amcfocm4-embot-os.uvprojx @@ -340,7 +340,7 @@ -Ddualcore_BOOT_cm7master -Wno-pragma-pack -Wno-deprecated-register -DEMBOT_USE_rtos_osal USE_STM32HAL STM32HAL_BOARD_AMCFOCM4 STM32HAL_DRIVER_V1A0 - ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp;..\..\..\..\..\libs\highlevel\services\embenv\api + ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp;..\..\..\..\..\libs\highlevel\services\embenv\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools @@ -568,6 +568,16 @@ 8 ..\..\..\..\..\embot\app\embot_app_theLEDmanager.cpp + + embot_app_scope.cpp + 8 + ..\..\..\..\..\embot\app\embot_app_scope.cpp + + + embot_tools.cpp + 8 + ..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools\embot_tools.cpp + @@ -603,6 +613,11 @@ 8 ..\..\..\bsp\embot_hw_flash_amcfocm4.cpp + + system_stm32h7xx-cm4-cm7-gated.c + 1 + ..\..\..\bsp\system_stm32h7xx-cm4-cm7-gated.c + @@ -1071,7 +1086,7 @@ -Ddualcore_BOOT_cm4master -Wno-pragma-pack -Wno-deprecated-register -DEMBOT_USE_rtos_osal USE_STM32HAL STM32HAL_BOARD_AMCFOCM4 STM32HAL_DRIVER_V1A0 - ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp;..\..\..\..\..\libs\highlevel\services\embenv\api + ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp;..\..\..\..\..\libs\highlevel\services\embenv\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools @@ -1299,6 +1314,16 @@ 8 ..\..\..\..\..\embot\app\embot_app_theLEDmanager.cpp + + embot_app_scope.cpp + 8 + ..\..\..\..\..\embot\app\embot_app_scope.cpp + + + embot_tools.cpp + 8 + ..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools\embot_tools.cpp + @@ -1334,6 +1359,11 @@ 8 ..\..\..\bsp\embot_hw_flash_amcfocm4.cpp + + system_stm32h7xx-cm4-cm7-gated.c + 1 + ..\..\..\bsp\system_stm32h7xx-cm4-cm7-gated.c + diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini index 5814ff1c3a..fcc52e5620 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini @@ -12,11 +12,24 @@ FUNC void DebugSetup (void) { - _WDWORD(0x580244e0, _RDWORD(0x580244e0) | 0x00000010); // RCC_AHB1ENR: IO port E clock enable - _WDWORD(0x58021000, 0x000002A0); // GPIOE_MODER: PE2..PE4 = Alternate function mode - _WDWORD(0x58021008, 0x000003F0); // GPIOE_OSPEEDR: PE2..PE4 = 100 MHz speed - _WDWORD(0x5802100C, 0x00000000); // GPIOE_PUPDR: PE2..PE4 = No Pull-up/Pull-down - _WDWORD(0x58021020, 0x00000000); // GPIOE_AFRL: PE2..PE4 = AF0 + + _WDWORD(0x580244E0, _RDWORD(0x580244E0) | 0x0000001C); // RCC_AHB4ENR: IO port C D E clocks enabled (E is bit pos 4, D pos 3, C pos 2) + + _WDWORD(0x58021000, 0x000002A0); // GPIOE_MODER: PE2..PE4 = Alternate function mode: it must be 10b in pairs in pos = 2, 3, 4 + _WDWORD(0x58021008, 0x000003F0); // GPIOE_OSPEEDR: PE2..PE4 = 100 MHz speed. it must be 11b in pairs in pos = 2, 3, 4 + _WDWORD(0x5802100C, 0x00000000); // GPIOE_PUPDR: PE2..PE4 = No Pull-up/Pull-down. it must be 00b in pos = 2, 3, 4 + _WDWORD(0x58021020, 0x00000000); // GPIOE_AFRL: PE2..PE4 = AF0 with AF0 = 0000b in pos = 2, 3, 4 + + _WDWORD(0x58020C00, 0x00000020); // GPIOD_MODER: PD2 = Alternate function mode: it must be 10b in pairs in pos = 2 + _WDWORD(0x58020C08, 0x00000030); // GPIOD_OSPEEDR: PD2 = 100 MHz speed. it must be 11b in pairs in pos = 2 + _WDWORD(0x58020C0C, 0x00000000); // GPIOD_PUPDR: PD2 = No Pull-up/Pull-down. it must be 00b in pos = 2 + _WDWORD(0x58020C20, 0x00000000); // GPIOD_AFRL: PD2 = AF0 with AF0 = 0000b in pos = 2 + + _WDWORD(0x58020800, 0x02000000); // GPIOC_MODER: PC12 = Alternate function mode: it must be 10b in pairs in pos = 12 + _WDWORD(0x58020808, 0x03000000); // GPIOC_OSPEEDR: PC12 = 100 MHz speed. it must be 11b in pairs in pos = 12 + _WDWORD(0x5802080C, 0x00000000); // GPIOC_PUPDR: PC12 = No Pull-up/Pull-down. it must be 00b in pos = 12 + _WDWORD(0x58020824, 0x00000000); // GPIOC_AFRH: PC12 = AF0 with AF0 = 0000b in pos = 12-8=4 + // Debug MCU Configuration // DBG_SLEEP Debug Sleep Mode diff --git a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/src/main-basic.cpp b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/src/main-basic.cpp index 279622dd07..1f91ec2420 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/src/main-basic.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm4/examples/embot-os/src/main-basic.cpp @@ -20,10 +20,14 @@ #include "embot_os_theCallbackManager.h" #include "embot_app_theLEDmanager.h" +#include "embot_app_scope.h" + #include #include "embot_hw_bsp_amcfocm4.h" +embot::app::scope::Signal *signal {nullptr}; + constexpr embot::os::Event evtTick = embot::core::binary::mask::pos2mask(0); @@ -33,6 +37,8 @@ constexpr embot::core::relTime tickperiod = 1000*embot::core::time1millisec; #include "embot_hw_led.h" #include "embot_hw_sys.h" +void ON(){}; + void eventbasedthread_startup(embot::os::Thread *t, void *param) { volatile uint32_t c = embot::hw::sys::clock(embot::hw::CLOCK::syscore); @@ -48,7 +54,10 @@ void eventbasedthread_startup(embot::os::Thread *t, void *param) embot::core::print("mainthread-startup: started timer which sends evtTick to evthread every = " + embot::core::TimeFormatter(tickperiod).to_string()); - //embot::core::TimeFormatter tf(embot::core::now()); + //embot::core::TimeFormatter tf(embot::core::now()); + + constexpr embot::app::scope::SignalEViewer::Config cc{ON, embot::app::scope::SignalEViewer::Config::LABEL::one}; + signal = new embot::app::scope::SignalEViewer(cc); embot::os::Timer *tmr = new embot::os::Timer; embot::os::Action act(embot::os::EventToThread(evtTick, t)); @@ -57,6 +66,55 @@ void eventbasedthread_startup(embot::os::Thread *t, void *param) } +#include + +void compute() +{ + static constexpr size_t N {10}; + static constexpr size_t M {10}; + static float data[N][M] = {0}; + + std::memset(data, 0, sizeof(data)); + + for(size_t n=0; n(n+m)*(data[n][m] + 1.0f); + data[std::max(N, m)][std::max(M, n)] = data[n][m] * data[n][m]; + } + } + +} + +void compute2() +{ + static constexpr size_t N {10}; + static constexpr size_t M {10}; + static float data[N][M] = {0}; + + std::memset(data, 0, sizeof(data)); + + for(size_t n=0; n(n) * static_cast(m); + + for(size_t n=0; n(n+m)*(data[n][m] + 1.0f)); + data[std::max(N, m)][std::max(M, n)] = data[n][m] * data[n][m]; + } + } + +} + +void testduration() +{ + //embot::hw::sys::delay(50); + compute2(); +} void eventbasedthread_onevent(embot::os::Thread *t, embot::os::EventMask eventmask, void *param) { @@ -66,7 +124,12 @@ void eventbasedthread_onevent(embot::os::Thread *t, embot::os::EventMask eventma } if(true == embot::core::binary::mask::check(eventmask, evtTick)) - { + { + + signal->on(); + testduration(); + signal->off(); + embot::core::TimeFormatter tf(embot::core::now()); embot::core::print("mainthread-onevent: evtTick received @ time = " + tf.to_string(embot::core::TimeFormatter::Mode::full)); } diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_bsp_DRIVER_amcfocm7.cpp b/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_bsp_DRIVER_amcfocm7.cpp index e24b47e757..0cb8ad713a 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_bsp_DRIVER_amcfocm7.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_bsp_DRIVER_amcfocm7.cpp @@ -55,9 +55,8 @@ bool embot::hw::bsp::DRIVER::init(const embot::hw::Config &config) cfg.tick1ms_get = _get1millitick; stm32hal_config(&cfg); - // but start it in a special way - - embot::hw::dualcore::start2(); + // but init it in a special way + embot::hw::dualcore::init(); return true; } diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_dualcore_bsp_amcfocm7.cpp b/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_dualcore_bsp_amcfocm7.cpp index f2b0286a28..3f3f29e4bd 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_dualcore_bsp_amcfocm7.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/bsp/embot_hw_dualcore_bsp_amcfocm7.cpp @@ -70,10 +70,10 @@ namespace embot::hw::dualcore::bsp { namespace embot::hw::dualcore::bsp { #if defined(dualcore_BOOT_cm7master) - constexpr PROP _cm7 = { embot::hw::dualcore::CORE::cm7, embot::hw::dualcore::BOOT::cm7master }; + constexpr PROP _cm7 = { embot::hw::dualcore::CORE::cm7, embot::hw::dualcore::BOOT::cm7master, embot::hw::MTX::one}; Config _config {embot::hw::dualcore::Config::HW::forceinit, embot::hw::dualcore::Config::CMD::activate}; #elif defined(dualcore_BOOT_cm4master) - constexpr PROP _cm7 = { embot::hw::dualcore::CORE::cm7, embot::hw::dualcore::BOOT::cm4master }; + constexpr PROP _cm7 = { embot::hw::dualcore::CORE::cm7, embot::hw::dualcore::BOOT::cm4master, embot::hw::MTX::one}; Config _config {embot::hw::dualcore::Config::HW::forceinit, embot::hw::dualcore::Config::CMD::donothing}; #endif @@ -103,155 +103,49 @@ namespace embot::hw::dualcore::bsp { return _config; } - void init_board(); - bool BSP::start() const - { - // ok, now we see what we need to do - init_board(); - - return true; - } void mySystemClock_Config(void); void icub_SystemClock_Config(void); - bool BSP::hwinit() const + bool BSP::init() const { -//#if defined(dualcore_BOOT_cm7master) + if(embot::hw::dualcore::BOOT::cm7master == _cm7.boot) { // the cm7 is master, so it must call HAL_Init() and start the clocks //MPU_Config(); HAL_MPU_Disable(); - SCB_EnableICache(); - SCB_EnableDCache(); +// SCB_EnableICache(); +// SCB_EnableDCache(); HAL_Init(); // mySystemClock_Config(); - icub_SystemClock_Config(); -// HAL_SYSTICK_CLKSourceConfig(); + icub_SystemClock_Config(); } else { -//#elif defined(dualcore_BOOT_cm4master) // the cm7 is slave, so the cm4 has already done everything. // only thing is to enable the cache as only the cm7 can do it + // ... maybe add some MPU initialization - SCB_EnableICache(); - SCB_EnableDCache(); - HAL_Init(); - icub_SystemClock_Config(); - //mySystemClock_Config(); - //SystemCoreClockUpdate(); +// SCB_EnableICache(); +// SCB_EnableDCache(); } - -//#endif + return true; } -//#if defined(dualcore_BOOT_cm4master) - - void waitHWmutex(uint32_t mtx) - { - volatile uint32_t m = mtx; - for(;;) - { - if(HAL_OK == HAL_HSEM_FastTake(m)) - { - break; - } - } - } -//#endif + +} // namespace embot::hw::dualcore::bsp { - void mySystemClock_Config(void); - - void init_board() - { -#if defined(dualcore_BOOT_cm7master) +// in here are the SystemClock_Config() that we use - if(embot::hw::dualcore::Config::HW::forceinit == _config.hw) - { - //MPU_Config(); - HAL_MPU_Disable(); - SCB_EnableICache(); - SCB_EnableDCache(); - HAL_Init(); - mySystemClock_Config(); - } - - SystemCoreClockUpdate(); - - // and now i process the command for the other core - - constexpr uint32_t hsem0 {0}; - constexpr uint32_t procID0 {0}; - - switch(_config.othercore) - { - case embot::hw::dualcore::Config::CMD::activateandhold: - { - // 1. init the hsems and take hsem-0 - __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); - - // 2. enable the other core - HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); - } break; - - case embot::hw::dualcore::Config::CMD::release: - { - // 1. init the hsems (just in case) and release hsem-0 - __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_Release(hsem0, procID0); - } break; - - case embot::hw::dualcore::Config::CMD::activate: - { - // 1. init the hsems and take hsem-0 - __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); - - // 2. enable the other core - HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); - - // 3. and release hsem-0 - HAL_HSEM_Release(hsem0, procID0); - - } break; - - case embot::hw::dualcore::Config::CMD::donothing: - default: - { - break; - } - } - -#elif defined(dualcore_BOOT_cm4master) - - // just wait until the master core activates the slave core and unlocks the HSEM 0 - __HAL_RCC_HSEM_CLK_ENABLE(); - waitHWmutex(0); - - if(embot::hw::dualcore::Config::HW::forceinit == _config.hw) - { -// //MPU_Config(); -// HAL_MPU_Disable(); - SCB_EnableICache(); - SCB_EnableDCache(); -// HAL_Init(); - } - - SystemCoreClockUpdate(); - -#endif - - } +namespace embot::hw::dualcore::bsp { // from icubtech diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvoptx b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvoptx index 4e3d2b5822..80c1b1d3aa 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvoptx +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvoptx @@ -120,7 +120,7 @@ 0 ULP2CM3 - -UAny -O206 -S12 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC400000000 -TT100000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE80000001 -TIP9 -FO7 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H745IIKx$CMSIS\Flash\STM32H7x_2048.FLM) + -UP1123199 -O206 -S12 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65587 -TC400000000 -TT400000000 -TP18 -TDX0 -TDD0 -TDS8001 -TDT0 -TDC1F -TIE80000001 -TIP9 -FO7 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H745IIKx$CMSIS\Flash\STM32H7x_2048.FLM) 0 @@ -140,7 +140,7 @@ 0 ARMRTXEVENTFLAGS - -L200 -Z0 -C0 -M1 -T1 + -L200 -Z15 -C0 -M1 -T1 0 @@ -158,24 +158,7 @@ - - - 0 - 0 - 117 - 1 -
134250224
- 0 - 0 - 0 - 0 - 0 - 1 - ..\..\..\bsp\embot_hw_dualcore_bsp_amcfocm7.cpp - - \\amcfocm7\../../../bsp/embot_hw_dualcore_bsp_amcfocm7.cpp\117 - - + 0 @@ -240,6 +223,12 @@ + + + OS Support\Event Viewer + 35905 + + 1 0 @@ -342,14 +331,14 @@ - + .\eventviewer-amcfoc-cfg.ini BIN\ULP2CM3.DLL 0 ULP2CM3 - -UP1123199 -O16846 -S12 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO19 -TC400000000 -TT200000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE80000001 -TIP9 -FO7 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H745IIKx$CMSIS\Flash\STM32H7x_2048.FLM) + -UP1123199 -O16846 -S12 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65555 -TC400000000 -TT200000000 -TP18 -TDX0 -TDD0 -TDS8001 -TDT0 -TDC10 -TIE80000001 -TIP9 -FO7 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H745IIKx$CMSIS\Flash\STM32H7x_2048.FLM) 0 @@ -369,7 +358,7 @@ 0 ARMRTXEVENTFLAGS - -L200 -Z0 -C0 -M1 -T1 + -L200 -Z9 -C0 -M1 -T1 0 @@ -452,8 +441,14 @@ + + + OS Support\Event Viewer + 35905 + + - 1 + 0 0 0 2 @@ -816,6 +811,30 @@ 0 0 + + 7 + 26 + 8 + 0 + 0 + 0 + ..\..\..\..\..\embot\app\embot_app_scope.cpp + embot_app_scope.cpp + 0 + 0 + + + 7 + 27 + 8 + 0 + 0 + 0 + ..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools\embot_tools.cpp + embot_tools.cpp + 0 + 0 + @@ -826,7 +845,7 @@ 0 8 - 26 + 28 8 0 0 @@ -838,7 +857,7 @@ 8 - 27 + 29 8 0 0 @@ -850,7 +869,7 @@ 8 - 28 + 30 8 0 0 @@ -862,7 +881,7 @@ 8 - 29 + 31 8 0 0 @@ -874,7 +893,7 @@ 8 - 30 + 32 8 0 0 @@ -886,7 +905,7 @@ 8 - 31 + 33 8 0 0 @@ -896,6 +915,18 @@ 0 0 + + 8 + 34 + 1 + 0 + 0 + 0 + ..\..\..\bsp\system_stm32h7xx-cm4-cm7-gated.c + system_stm32h7xx-cm4-cm7-gated.c + 0 + 0 + @@ -906,7 +937,7 @@ 0 9 - 32 + 35 8 0 0 diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvprojx b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvprojx index 9fcefaec49..1ea69b4e57 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvprojx +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/amcfocm7-embot-os.uvprojx @@ -314,7 +314,7 @@ 1 - 1 + 6 0 0 1 @@ -340,7 +340,7 @@ -Ddualcore_BOOT_cm7master -Wno-pragma-pack -Wno-deprecated-register -DEMBOT_USE_rtos_osal USE_STM32HAL STM32HAL_BOARD_AMCFOCM7 STM32HAL_DRIVER_V1A0 - ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp + ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools @@ -558,6 +558,16 @@ 8 ..\..\..\..\..\embot\app\embot_app_theLEDmanager.cpp + + embot_app_scope.cpp + 8 + ..\..\..\..\..\embot\app\embot_app_scope.cpp + + + embot_tools.cpp + 8 + ..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools\embot_tools.cpp + @@ -593,6 +603,11 @@ 8 ..\..\..\bsp\embot_hw_bsp_gpio.cpp + + system_stm32h7xx-cm4-cm7-gated.c + 1 + ..\..\..\bsp\system_stm32h7xx-cm4-cm7-gated.c + @@ -1035,7 +1050,7 @@ 1 - 1 + 6 0 0 1 @@ -1061,7 +1076,7 @@ -Ddualcore_BOOT_cm4master -Wno-pragma-pack -Wno-deprecated-register -DEMBOT_USE_rtos_osal USE_STM32HAL STM32HAL_BOARD_AMCFOCM7 STM32HAL_DRIVER_V1A0 - ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp + ..\..\..\..\..\libs\lowlevel\stm32hal\api;..\..\..\..\..\libs\highlevel\abslayer\osal\api;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\core;..\..\..\..\..\embot\hw;..\..\..\..\..\embot\os;..\..\..\..\..\embot\app;..\..\..\..\..\embot\app;..\..\..\..\..\libs\midware\eventviewer\api;..\..\..\bsp;..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools @@ -1279,6 +1294,16 @@ 8 ..\..\..\..\..\embot\app\embot_app_theLEDmanager.cpp + + embot_app_scope.cpp + 8 + ..\..\..\..\..\embot\app\embot_app_scope.cpp + + + embot_tools.cpp + 8 + ..\..\..\..\..\..\..\..\..\icub-firmware-shared\embot\tools\embot_tools.cpp + @@ -1314,6 +1339,11 @@ 8 ..\..\..\bsp\embot_hw_bsp_gpio.cpp + + system_stm32h7xx-cm4-cm7-gated.c + 1 + ..\..\..\bsp\system_stm32h7xx-cm4-cm7-gated.c + diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini new file mode 100644 index 0000000000..6d70b1c68e --- /dev/null +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/proj/eventviewer-amcfoc-cfg.ini @@ -0,0 +1,82 @@ +/******************************************************************************/ +/* STM32_TP.ini: STM32 Debugger Initialization File */ +/******************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> // +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2005-2009 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + +// maybe use _WDWORD(regaddr, _RDWORD(regaddr) | val) or something similar that act only on the wanted positions +FUNC void DebugSetup (void) { + _WDWORD(0x580244E0, _RDWORD(0x580244E0) | 0x0000001C); // RCC_AHB4ENR: IO port C D E clocks enabled (E is bit pos 4, D pos 3, C pos 2) + + _WDWORD(0x58021000, 0x000002A0); // GPIOE_MODER: PE2..PE4 = Alternate function mode: it must be 10b in pairs in pos = 2, 3, 4 + _WDWORD(0x58021008, 0x000003F0); // GPIOE_OSPEEDR: PE2..PE4 = 100 MHz speed. it must be 11b in pairs in pos = 2, 3, 4 + _WDWORD(0x5802100C, 0x00000000); // GPIOE_PUPDR: PE2..PE4 = No Pull-up/Pull-down. it must be 00b in pos = 2, 3, 4 + _WDWORD(0x58021020, 0x00000000); // GPIOE_AFRL: PE2..PE4 = AF0 with AF0 = 0000b in pos = 2, 3, 4 + + _WDWORD(0x58020C00, 0x00000020); // GPIOD_MODER: PD2 = Alternate function mode: it must be 10b in pairs in pos = 2 + _WDWORD(0x58020C08, 0x00000030); // GPIOD_OSPEEDR: PD2 = 100 MHz speed. it must be 11b in pairs in pos = 2 + _WDWORD(0x58020C0C, 0x00000000); // GPIOD_PUPDR: PD2 = No Pull-up/Pull-down. it must be 00b in pos = 2 + _WDWORD(0x58020C20, 0x00000000); // GPIOD_AFRL: PD2 = AF0 with AF0 = 0000b in pos = 2 + + _WDWORD(0x58020800, 0x02000000); // GPIOC_MODER: PC12 = Alternate function mode: it must be 10b in pairs in pos = 12 + _WDWORD(0x58020808, 0x03000000); // GPIOC_OSPEEDR: PC12 = 100 MHz speed. it must be 11b in pairs in pos = 12 + _WDWORD(0x5802080C, 0x00000000); // GPIOC_PUPDR: PC12 = No Pull-up/Pull-down. it must be 00b in pos = 12 + _WDWORD(0x58020824, 0x00000000); // GPIOC_AFRH: PC12 = AF0 with AF0 = 0000b in pos = 12-8=4 + +// Debug MCU Configuration +// DBG_SLEEP Debug Sleep Mode +// DBG_STOP Debug Stop Mode +// DBG_STANDBY Debug Standby Mode +// TRACE_IOEN Trace I/O Enable +// TRACE_MODE Trace Mode +// <0=> Asynchronous +// <1=> Synchronous: TRACEDATA Size 1 +// <2=> Synchronous: TRACEDATA Size 2 +// <3=> Synchronous: TRACEDATA Size 4 +// + _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR + +// Debug MCU APB1 Freeze +// DBG_TIM2_STOP Timer 2 Stopped when Core is halted +// DBG_TIM3_STOP Timer 3 Stopped when Core is halted +// DBG_TIM4_STOP Timer 4 Stopped when Core is halted +// DBG_TIM5_STOP Timer 5 Stopped when Core is halted +// DBG_TIM6_STOP Timer 6 Stopped when Core is halted +// DBG_TIM7_STOP Timer 7 Stopped when Core is halted +// DBG_TIM12_STOP Timer 12 Stopped when Core is halted +// DBG_TIM13_STOP Timer 13 Stopped when Core is halted +// DBG_TIM14_STOP Timer 14 Stopped when Core is halted +// DBG_RTC_STOP RTC Stopped when Core is halted +// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted +// DBG_IWDG_STOP Independent Watchdog Stopped when Core is halted +// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS Timeout Mode Stopped when Core is halted +// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS Timeout Mode Stopped when Core is halted +// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS Timeout Mode Stopped when Core is halted +// DBG_CAN1_STOP CAN1 Stopped when Core is halted +// DBG_CAN2_STOP CAN2 Stopped when Core is halted +// + _WDWORD(0xE0042008, 0x06E01DFF); // DBGMCU_APB1_FZ + +// Debug MCU APB2 Freeze +// DBG_TIM1_STOP Timer 1 Stopped when Core is halted +// DBG_TIM8_STOP Timer 8 Stopped when Core is halted +// DBG_TIM9_STOP Timer 9 Stopped when Core is halted +// DBG_TIM10_STOP Timer 10 Stopped when Core is halted +// DBG_TIM11_STOP Timer 11 Stopped when Core is halted +// + _WDWORD(0xE004200C, 0x00070003); // DBGMCU_APB2_FZ + +} + +// Executed after reset via uVision's 'Reset'-button +FUNC void OnResetExec (void) { + DebugSetup(); +} + +DebugSetup(); // Debugger Setup \ No newline at end of file diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/src/main-basic.cpp b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/src/main-basic.cpp index e29adc06a4..35ffced006 100644 --- a/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/src/main-basic.cpp +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/examples/embot-os/src/main-basic.cpp @@ -22,15 +22,19 @@ #include "embot_hw_bsp_amcfocm7.h" +#include "embot_app_scope.h" + #include constexpr embot::os::Event evtTick = embot::core::binary::mask::pos2mask(0); +embot::app::scope::Signal *signal {nullptr}; constexpr embot::core::relTime tickperiod = 1000*embot::core::time1millisec; +void ON(){}; void eventbasedthread_startup(embot::os::Thread *t, void *param) { @@ -42,6 +46,10 @@ void eventbasedthread_startup(embot::os::Thread *t, void *param) //embot::core::TimeFormatter tf(embot::core::now()); + constexpr embot::app::scope::SignalEViewer::Config cc{ON, embot::app::scope::SignalEViewer::Config::LABEL::one}; + signal = new embot::app::scope::SignalEViewer(cc); + + embot::os::Timer *tmr = new embot::os::Timer; embot::os::Action act(embot::os::EventToThread(evtTick, t)); embot::os::Timer::Config cfg{tickperiod, act, embot::os::Timer::Mode::forever, 0}; @@ -49,6 +57,54 @@ void eventbasedthread_startup(embot::os::Thread *t, void *param) } +void compute() +{ + static constexpr size_t N {10}; + static constexpr size_t M {10}; + static float data[N][M] = {0}; + + std::memset(data, 0, sizeof(data)); + + for(size_t n=0; n(n+m)*(data[n][m] + 1.0f); + data[std::max(N, m)][std::max(M, n)] = data[n][m] * data[n][m]; + } + } + +} + +void compute2() +{ + static constexpr size_t N {10}; + static constexpr size_t M {10}; + static float data[N][M] = {0}; + + std::memset(data, 0, sizeof(data)); + + for(size_t n=0; n(n) * static_cast(m); + + for(size_t n=0; n(n+m)*(data[n][m] + 1.0f)); + data[std::max(N, m)][std::max(M, n)] = data[n][m] * data[n][m]; + } + } + +} + + +void testduration() +{ +// embot::hw::sys::delay(50); + compute2(); +} void eventbasedthread_onevent(embot::os::Thread *t, embot::os::EventMask eventmask, void *param) { @@ -58,9 +114,14 @@ void eventbasedthread_onevent(embot::os::Thread *t, embot::os::EventMask eventma } if(true == embot::core::binary::mask::check(eventmask, evtTick)) - { + { + signal->on(); + testduration(); + signal->off(); + embot::core::TimeFormatter tf(embot::core::now()); - embot::core::print("mainthread-onevent: evtTick received @ time = " + tf.to_string(embot::core::TimeFormatter::Mode::full)); + embot::core::print("mainthread-onevent: evtTick received @ time = " + tf.to_string(embot::core::TimeFormatter::Mode::full)); + } diff --git a/emBODY/eBcode/arch-arm/board/amcfocm7/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/emBODY/eBcode/arch-arm/board/amcfocm7/system_stm32h7xx_dualcore_boot_cm4_cm7.c new file mode 100644 index 0000000000..220784c4f1 --- /dev/null +++ b/emBODY/eBcode/arch-arm/board/amcfocm7/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -0,0 +1,395 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx_dualcore_boot_cm4_cm7.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * This provides system initialization template function is case of + * an application using a dual core STM32H7 device where + * Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is + detectable by the CPU after a WFI/WFE instruction.*/ + SCB->SCR |= SCB_SCR_SEVONPEND_Msk; + +#ifdef CORE_CM7 + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, HSECSSON, CSION, RC48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Enable CortexM7 HSEM EXTI line (line 78)*/ + EXTI_D2->EMR3 |= 0x4000UL; + + + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } + +#endif /* CORE_CM7*/ + +#ifdef CORE_CM4 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#ifdef CORE_CM7 + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#error Please #define CORE_CM4 or CORE_CM7 +#endif +#endif + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.cpp b/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.cpp index bd61732c65..b2098e2e19 100644 --- a/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.cpp +++ b/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.cpp @@ -56,11 +56,8 @@ namespace embot::hw::dualcore { bool config(const Config &c) { return false; } - bool start() - { return false; } - - bool start2() - { return false; } + bool init() + { return false; } } // namespace embot::hw::dualcore { @@ -102,15 +99,6 @@ namespace embot::hw::dualcore { return embot::hw::dualcore::bsp::getBSP().config(c); } - bool start() - { - if(false == supported()) - { - return false; - } - return embot::hw::dualcore::bsp::getBSP().start(); - } - void waitHWmutex(uint32_t mtx) { volatile uint32_t m = mtx; @@ -123,7 +111,7 @@ namespace embot::hw::dualcore { } } - bool start2() + bool init() { if(false == supported()) { @@ -133,6 +121,8 @@ namespace embot::hw::dualcore { embot::hw::dualcore::CORE co = embot::hw::dualcore::bsp::getBSP().getPROP()->core; embot::hw::dualcore::BOOT bo = embot::hw::dualcore::bsp::getBSP().getPROP()->boot; + embot::hw::MTX mtx = embot::hw::dualcore::bsp::getBSP().getPROP()->mtx; + uint32_t hsem = embot::core::tointegral(mtx); uint32_t other_RCC_BOOT_Cx = (embot::hw::dualcore::CORE::cm7 == co) ? RCC_BOOT_C2 : RCC_BOOT_C1; bool IamMaster = ((embot::hw::dualcore::CORE::cm7 == co) && (embot::hw::dualcore::BOOT::cm7master == bo)) || @@ -146,14 +136,13 @@ namespace embot::hw::dualcore { if(embot::hw::dualcore::Config::HW::forceinit == cfg.hw) { - embot::hw::dualcore::bsp::getBSP().hwinit(); + embot::hw::dualcore::bsp::getBSP().init(); } SystemCoreClockUpdate(); // and now i process the command for the other core - constexpr uint32_t hsem0 {0}; constexpr uint32_t procID0 {0}; switch(cfg.othercore) @@ -162,7 +151,7 @@ namespace embot::hw::dualcore { { // 1. init the hsems and take hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); + HAL_HSEM_FastTake(hsem); // 2. enable the other core C2 HAL_RCCEx_EnableBootCore(other_RCC_BOOT_Cx); @@ -172,20 +161,20 @@ namespace embot::hw::dualcore { { // 1. init the hsems (just in case) and release hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_Release(hsem0, procID0); + HAL_HSEM_Release(hsem, procID0); } break; case embot::hw::dualcore::Config::CMD::activate: { // 1. init the hsems and take hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); + HAL_HSEM_FastTake(hsem); // 2. enable the other core C2 HAL_RCCEx_EnableBootCore(other_RCC_BOOT_Cx); // 3. and release hsem-0 - HAL_HSEM_Release(hsem0, procID0); + HAL_HSEM_Release(hsem, procID0); } break; @@ -202,12 +191,12 @@ namespace embot::hw::dualcore { { // just wait until the master core activates the slave core and unlocks the HSEM 0 __HAL_RCC_HSEM_CLK_ENABLE(); - waitHWmutex(0); + waitHWmutex(hsem); // then i do some hw init specific to me if(embot::hw::dualcore::Config::HW::forceinit == cfg.hw) { - embot::hw::dualcore::bsp::getBSP().hwinit(); + embot::hw::dualcore::bsp::getBSP().init(); } SystemCoreClockUpdate(); @@ -218,14 +207,13 @@ namespace embot::hw::dualcore { { if(embot::hw::dualcore::Config::HW::forceinit == cfg.hw) { - embot::hw::dualcore::bsp::getBSP().hwinit(); + embot::hw::dualcore::bsp::getBSP().start(); } SystemCoreClockUpdate(); // and now i process the command for the other core - constexpr uint32_t hsem0 {0}; constexpr uint32_t procID0 {0}; switch(cfg.othercore) @@ -234,7 +222,7 @@ namespace embot::hw::dualcore { { // 1. init the hsems and take hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); + HAL_HSEM_FastTake(hsem); // 2. enable the other core C2 HAL_RCCEx_EnableBootCore(other_RCC_BOOT_Cx); @@ -244,20 +232,20 @@ namespace embot::hw::dualcore { { // 1. init the hsems (just in case) and release hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_Release(hsem0, procID0); + HAL_HSEM_Release(hsem, procID0); } break; case embot::hw::dualcore::Config::CMD::activate: { // 1. init the hsems and take hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); + HAL_HSEM_FastTake(hsem); // 2. enable the other core C2 HAL_RCCEx_EnableBootCore(other_RCC_BOOT_Cx); // 3. and release hsem-0 - HAL_HSEM_Release(hsem0, procID0); + HAL_HSEM_Release(hsem, procID0); } break; @@ -273,12 +261,12 @@ namespace embot::hw::dualcore { // just wait until the master core activates the slave core and unlocks the HSEM 0 __HAL_RCC_HSEM_CLK_ENABLE(); - waitHWmutex(0); + waitHWmutex(hsem); // then i do some hw init if(embot::hw::dualcore::Config::HW::forceinit == cfg.hw) { - embot::hw::dualcore::bsp::getBSP().hwinit(); + embot::hw::dualcore::bsp::getBSP().start(); } SystemCoreClockUpdate(); @@ -288,7 +276,7 @@ namespace embot::hw::dualcore { { if(embot::hw::dualcore::Config::HW::forceinit == cfg.hw) { - embot::hw::dualcore::bsp::getBSP().hwinit(); + embot::hw::dualcore::bsp::getBSP().start(); } SystemCoreClockUpdate(); @@ -296,7 +284,6 @@ namespace embot::hw::dualcore { // and now i process the command for the other core - constexpr uint32_t hsem0 {0}; constexpr uint32_t procID0 {0}; switch(cfg.othercore) @@ -305,7 +292,7 @@ namespace embot::hw::dualcore { { // 1. init the hsems and take hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); + HAL_HSEM_FastTake(hsem); // 2. enable the other core c1 HAL_RCCEx_EnableBootCore(other_RCC_BOOT_Cx); @@ -315,20 +302,20 @@ namespace embot::hw::dualcore { { // 1. init the hsems (just in case) and release hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_Release(hsem0, procID0); + HAL_HSEM_Release(hsem, procID0); } break; case embot::hw::dualcore::Config::CMD::activate: { // 1. init the hsems and take hsem-0 __HAL_RCC_HSEM_CLK_ENABLE(); - HAL_HSEM_FastTake(hsem0); + HAL_HSEM_FastTake(hsem); // 2. enable the other core c1 HAL_RCCEx_EnableBootCore(other_RCC_BOOT_Cx); // 3. and release hsem-0 - HAL_HSEM_Release(hsem0, procID0); + HAL_HSEM_Release(hsem, procID0); } break; @@ -344,12 +331,12 @@ namespace embot::hw::dualcore { { // just wait until the master core activates the slave core and unlocks the HSEM 0 __HAL_RCC_HSEM_CLK_ENABLE(); - waitHWmutex(0); + waitHWmutex(hsem); // then i do some hw init if(embot::hw::dualcore::Config::HW::forceinit == cfg.hw) { - embot::hw::dualcore::bsp::getBSP().hwinit(); + embot::hw::dualcore::bsp::getBSP().start(); } SystemCoreClockUpdate(); diff --git a/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.h b/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.h index 0ca8b21f3a..3b6e802856 100644 --- a/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.h +++ b/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore.h @@ -19,9 +19,9 @@ namespace embot::hw::dualcore { enum class CORE : uint8_t { cm4 = 0, cm7 = 1, none = 31, maxnumberof = 2 }; - enum class BOOT : uint8_t { cm4master = 0, cm7master = 1, none = 31 }; + enum class BOOT : uint8_t { cm4master = 0, cm7master = 1, none = 31, maxnumberof = 2 }; + - // what is actually executed .. just before embot:hw::bsp::specialize() struct Config { enum class HW : uint8_t { dontinit = 0, forceinit = 1 }; @@ -42,13 +42,9 @@ namespace embot::hw::dualcore { CORE core(); BOOT boot(); - // it must be called in main() before start() - bool config(const Config &on); - - // it must be called just after embot::hw::bsp::DRIVER::init() or even better instead that - bool start(); - - bool start2(); + + bool config(const Config &on); + bool init(); } // namespace embot::hw::dualcore { diff --git a/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore_bsp.h b/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore_bsp.h index 6f4a452022..3a6c72e06c 100644 --- a/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore_bsp.h +++ b/emBODY/eBcode/arch-arm/embot/hw/embot_hw_dualcore_bsp.h @@ -24,9 +24,10 @@ namespace embot::hw::dualcore::bsp { struct PROP { embot::hw::dualcore::CORE core {embot::hw::dualcore::CORE::cm7}; - embot::hw::dualcore::BOOT boot {embot::hw::dualcore::BOOT::cm7master}; + embot::hw::dualcore::BOOT boot {embot::hw::dualcore::BOOT::cm7master}; + embot::hw::MTX mtx {embot::hw::MTX::one}; constexpr PROP() = default; - constexpr PROP(embot::hw::dualcore::CORE c, embot::hw::dualcore::BOOT b) : core(c), boot(b) {} + constexpr PROP(embot::hw::dualcore::CORE c, embot::hw::dualcore::BOOT b, embot::hw::MTX m) : core(c), boot(b), mtx(m) {} }; struct BSP : public embot::hw::bsp::SUPP @@ -43,8 +44,7 @@ namespace embot::hw::dualcore::bsp { bool supported() const { return embot::hw::bsp::SUPP::supported(thempu); } bool config(const Config &c) const; const Config& config() const; - bool start() const; - bool hwinit() const; + bool init() const; }; const BSP& getBSP(); diff --git a/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvoptx b/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvoptx index 9b42fa753b..72076d02da 100644 --- a/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvoptx +++ b/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvoptx @@ -827,7 +827,7 @@ 1 0 - 0 + 1 18 @@ -1015,7 +1015,7 @@ 1 0 - 1 + 0 18 @@ -1150,7 +1150,7 @@ driver-stm32h7-v1A0 - 0 + 1 0 0 0 diff --git a/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvprojx b/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvprojx index e2a52354d2..ce7a6ed54c 100644 --- a/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvprojx +++ b/emBODY/eBcode/arch-arm/libs/lowlevel/stm32hal/proj/stm32hal.h7.dualcore.uvprojx @@ -9489,6 +9489,57 @@ system_stm32h7xx_dualcore_boot_cm4_cm7.c 1 ..\src\driver\stm32h7-v1A0\src\system_stm32h7xx_dualcore_boot_cm4_cm7.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + stm32h7xx_ll_gpio.c @@ -11103,6 +11154,57 @@ stm32h7xx_hal_msp.c 1 ..\src\board\amcfocm7\v1A0\src\stm32h7xx_hal_msp.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + @@ -11812,6 +11914,57 @@ system_stm32h7xx_dualcore_boot_cm4_cm7.c 1 ..\src\driver\stm32h7-v1A0\src\system_stm32h7xx_dualcore_boot_cm4_cm7.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + stm32h7xx_ll_gpio.c @@ -13357,6 +13510,57 @@ stm32h7xx_hal_msp.c 1 ..\src\board\amcfocm4\v1A0\src\stm32h7xx_hal_msp.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + +